JPH11297951A - Semiconductor integrated circuit device and method for manufacturing it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect the signal stored in an information storage capacity element with high sensitivity by preventing a parasitic capacity of bit line from increasing, related to a DRAM where memory cell size is finer. SOLUTION: By allowing the width of a bit line BL narrower than a minimum work dimension which is decided by the resolution limit of photo-lithography, a parasitic capacity formed between adjoining bit lines is reduced. In order to make the width of the bit line BL more minute, a photo-resist film 43 is cut by ashing using ozone so that the width of a bit line pattern 43a is narrower than a minimum work dimension.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a DRAM (Dynami
(c) Random Access Memory).

[0002]

2. Description of the Related Art A memory cell of a DRAM is arranged at an intersection of a plurality of word lines and a plurality of bit lines arranged in a matrix on a main surface of a semiconductor substrate. And one information storage capacitance element (capacitor) connected in series to The MISFET for selecting a memory cell mainly includes a gate oxide film, a gate electrode integrally formed with a word line, and a pair of semiconductor regions forming a source and a drain. The bit line is a MIS for selecting a memory cell.
It is arranged above the FET and is electrically connected to one of the source and the drain. The information storage capacitance element is similarly disposed above the memory cell selection MISFET, and is electrically connected to the other of the source and the drain.

As described above, in recent DRAMs, an information storage capacitor is placed above a memory cell selection MISFET in order to compensate for a decrease in the amount of charge stored in the information storage capacitor accompanying the miniaturization of memory cells. A so-called stacked capacitor structure is used. This stacked
DRAMs adopting a capacitor structure are roughly divided into a capacitor under bitline (Capacitor Under Bitline;
CUB) structure and a capacitor over bitline (COB) structure in which an information storage capacitive element is arranged above a bit line. Regarding the former, JP-A-7-192723,
The description is given in JP-A-8-204144, and the latter is described in JP-A-7-122654,
No. 06437.

[0004] Among the above two types of stacked capacitor structures, a COB structure in which an information storage capacitor is arranged above a bit line is more suitable for miniaturization of a memory cell than a CUB structure. This is because, in order to increase the amount of charge stored in the miniaturized information storage capacitor, it is necessary to make the structure three-dimensional and increase the surface area. In this case, the aspect ratio of the contact hole connecting the bit line and the memory cell selection MISFET becomes extremely large, and it becomes difficult to open the hole.

In addition, 64 megabits (Mbit) or 2
In recent large-capacity DRAMs such as 56 megabits, it has become difficult to secure the amount of stored charge simply by increasing the surface area by three-dimensionalizing the information storage capacitor.
Along with the three-dimensionalization of the capacitive element, the capacitive insulating film is made of Ta ₂ O ₅ (tantalum oxide), (Ba, Sr) TiO ₃ (barium strontium titanate; hereinafter abbreviated as BST), SrTiO
_{The use of a} high-dielectric material such as ₃ (strontium titanate; abbreviated as STO) has been studied. A DRAM in which a capacitive insulating film is formed of such a high dielectric material is disclosed in, for example, Japanese Patent Application Laid-Open Nos.
-66300.

Further, in the above-mentioned 64-256 Mbit DRAM, when a contact hole for connecting a bit line and a substrate is formed in a space of a gate electrode of a memory cell selecting MISFET having a reduced pitch, a gate is formed. A self-aligned contact that covers the top and side walls of the electrode with a silicon nitride film and uses a difference in etching rate between the silicon oxide film and the silicon nitride film to open a contact hole in a self-aligned manner with respect to the gate electrode space. (Self Align Contact; SAC) technology,
As a measure to suppress an increase in resistance due to miniaturization of a contact hole connecting a source / drain of the MISFET and a wiring, a source / drain of a MISFET constituting a peripheral circuit such as a sense amplifier or a word driver particularly required to operate at high speed is required. On the surface of TiSi ₂ (titanium silicide)
(Silicidatio) for forming a refractory metal silicide layer such as CoSi ₂ (cobalt silicide)
n) Technology adoption is considered to be inevitable. This silicidation technology is described in, for example,
No. 1,796, JP-A-6-29240, and JP-A-8-181212.

[0007]

SUMMARY OF THE INVENTION The inventor of the present invention has proposed a digital signal processing system capable of supporting 256 megabits (Mbit) and subsequent generations.
We are developing the structure and process of RAM.

In the DRAM under development by the present inventor, the gate electrode (word line) of the MISFET for memory cell selection and the M
The gate electrode of the ISFET is made of a low-resistance conductive material mainly composed of a refractory metal such as W (tungsten), and the source and drain of the MISFET which constitute a peripheral circuit as a measure to reduce the contact resistance between the substrate and the wiring A refractory metal silicide layer is formed on the surface of the substrate.

In this DRAM, the bit line is made of a low-resistance conductive material mainly composed of a refractory metal such as W as a measure against the signal delay of the bit line. The wiring of the first layer of the peripheral circuit is formed in the same step. In addition, this DRAM
As a measure to secure the amount of charge stored in the information storage capacitor, an information storage capacitor is disposed above the bit line.
The adoption of the OB structure promotes the three-dimensional formation of the capacitance element, and the capacitance insulating film is made of Ta ₂ O ₅ (tantalum oxide).
It is made of a high dielectric material such as

The process of manufacturing the above-mentioned DRAM will be briefly described. First, a low-resistance material mainly composed of a high melting point metal deposited on a main surface of a semiconductor substrate is patterned to form a MISFET for selecting a memory cell. After forming a gate electrode (word line) and a gate electrode of a MISFET of a peripheral circuit, impurities are ion-implanted into a semiconductor substrate to form a source and a drain of the MISFET. The gate electrodes of the memory cell selecting MISFET are formed such that their width and space (line & space) are the minimum processing size determined by the resolution limit of photolithography.

Next, after covering the upper portions of these MISFETs with an insulating film, first, a contact hole is formed in the insulating film above the source and drain of the memory cell selecting MISFET. A plug of crystalline silicon is embedded. This contact hole is formed using a self-aligned contact (SAC) technique utilizing a difference in etching rate between the silicon oxide film and the silicon nitride film.

Next, contact holes are formed in the insulating film on each of the gate electrode, the source, and the drain of the MISFET of the peripheral circuit, and then a Ti film or a Co film is formed on the insulating film including the inside of these contact holes. By depositing a thin film of a high melting point metal such as a high melting point metal, and subsequently heat-treating the semiconductor substrate to cause the substrate (Si) at the bottom of the contact hole to react with the high melting point metal film, a high melting point metal silicide layer is formed at the bottom of the contact hole. To form

Next, after a wiring material mainly composed of a refractory metal film such as W is deposited on the upper portion of the insulating film including the inside of the contact hole of the peripheral circuit, the wiring material and the unreacted material remaining on the surface of the insulating film are deposited. By patterning the reactive Ti film, a bit line and a first layer wiring of a peripheral circuit are formed on the insulating film. The bit line is electrically connected to one of the source and the drain of the memory cell selecting MISFET through the contact hole in which a polycrystalline silicon plug is embedded. The first layer wiring of the peripheral circuit is connected to the contact of the peripheral circuit. MISFE of peripheral circuit through hole
The gate electrode of T is electrically connected to either the source or the drain.

Next, the respective upper portions of the bit lines and the first layer wiring of the peripheral circuit are covered with an interlayer insulating film. Subsequently, the other of the source and drain of the memory cell selecting MISFET and the information storage are formed on the interlayer insulating film. After forming a through-hole for connecting to the capacitive element for storage, a conductive film such as polycrystalline silicon deposited on the through-hole is patterned to form a lower electrode of the information storage capacitive element having a three-dimensional structure. Form.

Next, after depositing a high dielectric film such as Ta ₂ O ₅ (tantalum oxide) on the surface of the lower electrode, a high temperature heat treatment is performed. High-dielectric films made of metal oxides such as Ta ₂ O ₅ , BST, and STO have a common property that they are subjected to high-temperature heat treatment at about 800 ° C. after film formation in order to obtain a high-quality film with few crystal defects. There is a need to do. Also, once the high-temperature heat treatment is performed, 4 hours to prevent the film quality from deteriorating.
It is necessary not to expose to a high temperature atmosphere of about 50 ° C. or more.

Next, after depositing a conductive film such as a TiN film on the high dielectric film, the conductive film and the underlying high dielectric film are patterned to form an upper electrode of the information storage capacitor and a capacitor. An insulating film is formed. After that, although depending on the design specifications, usually, about two layers of metal wiring mainly composed of Al (aluminum) are formed on the upper layer of the information storage capacitor element.

However, according to studies made by the present inventor, when the above-described manufacturing process is applied to a DRAM having a design rule of 0.25 μm or less, the following problems must be solved.

That is, in a DRAM having a COB structure in which an information storage capacitor is arranged above a bit line, a through hole for connecting one of the source and drain of the memory cell selection MISFET to the information storage capacitor is provided. It is arranged in a space area between a bit line and a bit line adjacent thereto. At this time, if the pitch of the bit line is set to about twice the minimum processing size determined by the resolution limit of photolithography, the width and space of the bit line (line & space)
Is about the same as the minimum processing size (0.25 μm or less). However, if the above-mentioned through-hole is arranged in such a minute space, it becomes impossible to secure a margin for mask alignment between the bit line and the through-hole, so that the conductive film embedded in the through-hole and the bit line short-circuit. Would.

As a measure to avoid such a problem,
For example, the aforementioned self-aligned contact (SAC)
Adoption of technology is conceivable. That is, the upper part and the side wall of the bit line are covered with a silicon nitride film, and the through hole is formed with respect to the space of the bit line by utilizing an etching rate difference between the silicon nitride film and the silicon oxide film in a region where the through hole is formed. The holes are formed in a self-aligned manner to prevent short circuit between the conductive film in the through hole and the bit line.

However, when the above-described self-aligned contact technology in which the periphery of the bit line is covered with a silicon nitride film is adopted, the dielectric constant of silicon nitride is twice as high as that of silicon oxide, so that the Another problem is that the capacity is increased.

As is well known, when the capacitance of the information storage capacitor is Cs, the amount of charge stored in the signal is Qs, and the capacitance of the bit line including the portion connected to the sense amplifier is Cbl, the readout of the signal Appearing read voltage (Vs)
Is as follows: Vs = Cs × Qs / (Cs + Cbl) Here, assuming that Cs and Qs are given, as the capacitance (Cbl) of the bit line increases, the readout voltage (Vs) decreases, and the detectable signal level decreases.

A DRAM manufactured according to a design rule of 0.25 μm or less has a very small memory cell size and bit lines are arranged at a narrow pitch, so that parasitic capacitance generated between adjacent bit lines is ignored. become unable. Therefore, the adoption of the self-aligned contact technique in which the periphery of the bit line is covered with the silicon nitride film further increases the capacity of the bit line and makes it more difficult to detect the signal stored in the information storage capacitor.

An object of the present invention is to provide a technology capable of preventing a bit line from increasing in capacity and detecting a signal stored in an information storage capacitor element with high sensitivity in a DRAM having a fine memory cell size. To provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0025]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

In a semiconductor integrated circuit device according to the present invention, a memory cell selecting MISFET having a gate electrode integrally formed with a word line is formed in a first region on a main surface of a semiconductor substrate. First covering MISFET
A bit line electrically connected to one of a source and a drain of the memory cell selection MISFET is formed on the insulating film, and the memory is formed on the second insulating film formed on the bit line. A DRAM having an information storage capacitor electrically connected to the other of the source and the drain of the cell selection MISFET, wherein a width of the bit line is less than a minimum dimension determined by a resolution limit of photolithography. Consists of dimensions.

According to a method of manufacturing a semiconductor integrated circuit device of the present invention, a memory cell selecting MI having a gate electrode integrally formed with a word line in a first region on a main surface of a semiconductor substrate is provided.
An SFET is formed, and the memory cell selecting MISFE is formed.
The memory cell selecting M is formed on the first insulating film covering T.
A bit line electrically connected to one of a source and a drain of the ISFET is formed, and the memory cell selecting MIS is formed on a second insulating film formed on the bit line.
A method for manufacturing a semiconductor integrated circuit device having a DRAM in which an information storage capacitor electrically connected to the other of the source and the drain of the FET is formed, the method comprising:
To (d).

(A) forming a memory cell selecting MISFET forming a memory cell of a DRAM on a main surface of a semiconductor substrate, and then depositing a first insulating film on the memory cell selecting MISFET; (b) A) a first photoresist having a pattern of bit lines arranged at a first width and a first interval above the first conductive film after depositing a first conductive film on the first insulating film; Forming a film,
(C) By ashing the first photoresist film, a bit line pattern having a second width smaller than the first width and a second space larger than the first space is provided. Forming a second photoresist film, and (d) etching the first conductive film using the second photoresist film as a mask.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, the first photoresist film is ashed by using a gas containing ozone.

Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a memory cell selecting MISFET having a gate electrode formed integrally with a word line on a main surface of a semiconductor substrate is provided.
Is formed, and the MISFE for memory cell selection is formed on the first insulating film covering the MISFET for memory cell selection.
A method of manufacturing a semiconductor integrated circuit device having a memory cell in which an information storage capacitor electrically connected to one of a source and a drain of T is formed, wherein (a) a memory cell is provided on a main surface of a semiconductor substrate. MIS for selecting memory cells constituting
After forming the FET, the memory cell selecting MISFE
Depositing a first insulating film on top of T; (b) forming a photoresist film having an opening pattern on one of the source and the drain of the memory cell selecting MISFET on the first insulating film; Thereafter, a step of widening the inner diameter of the opening pattern by etching the front photoresist film by ashing using a gas containing ozone,
(C) forming a groove corresponding to the opening pattern in the first insulating film by etching the first insulating film using the photoresist film as a mask;
(D) forming a lower electrode of the information storage capacitor by patterning the first conductive film formed along the inner wall of the concave groove.

Further, a method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps: (a) depositing a first conductive film on a main surface of a semiconductor substrate and then forming the first conductive film; Forming a first photoresist film on the upper portion, (b) exposing and developing the first photoresist film to thereby form the first photoresist film in a first region on a main surface of the semiconductor substrate Forming a first gate electrode pattern, (c) etching the first photoresist film by ashing using a gas containing ozone, thereby narrowing the width of the first gate electrode pattern;
(D) etching the first conductive film by using the first photoresist film as a mask, so that the width of the first region is smaller than the minimum processing dimension and is adjacent to the first gate electrode; The first space is larger than the width
Forming a gate electrode; and (e) removing the first photoresist film and then removing the second photoresist film on the main surface of the semiconductor substrate.
Forming a second photoresist film having a second gate electrode pattern in a region; and (f) etching the first conductive film using the second photoresist film as a mask, thereby forming a second photoresist film in the second region. Forming a second gate electrode whose width and space are substantially equal.

[0032]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to the present embodiment is formed.
As shown, a semiconductor chip 1 made of single crystal silicon
X direction (long side direction of semiconductor chip 1A) on the main surface of A
And a large number of memory arrays MARY are arranged in a matrix along the Y direction (the short side direction of the semiconductor chip 1A). Memory arrays M adjacent to each other along the X direction
A sense amplifier SA is arranged between ARY. A word driver W is provided at the center of the main surface of the semiconductor chip 1A.
D, control circuits such as data line selection circuits, input / output circuits,
Bonding pads and the like are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM. As shown, the memory array of this DRAM (MA
RY) includes a plurality of word lines W arranged in a matrix.
L (WLn-1, WLn, WLn + 1...), A plurality of bit lines BL, and a plurality of memory cells (MC) arranged at their intersections. One memory cell for storing 1-bit information is composed of one information storage capacitor C and one memory cell selection M connected in series to this.
ISFET Qs. One of the source and the drain of the memory cell selection MISFET Qs is electrically connected to the information storage capacitor C, and the other is the bit line B.
L and is electrically connected. One end of the word line WL
It is connected to a word driver WD, and one end of the bit line BL is connected to a sense amplifier SA.

FIG. 3 is a sectional view of a main part of a semiconductor substrate showing a part of a memory array and peripheral circuits of a DRAM. FIG. 4 is a schematic plan view of the semiconductor substrate showing a part of the memory array. The left part is a cross-sectional view along the line AA 'in FIG. 4, and the right part of the figure is a cross-sectional view along the line BB' in FIG. It is. FIG. 4 shows only a conductive layer (excluding a plate electrode) constituting a memory cell, and does not show an insulating film between conductive layers or a wiring formed over the memory cell.

A memory cell of the DRAM is formed in a p-type well 2 formed on a main surface of a semiconductor substrate 1 made of p-type single crystal silicon. The p-type well 2 in the region (memory array) in which the memory cell is formed is formed under the n-type well in order to prevent noise from entering from an input / output circuit or the like formed in another region of the semiconductor substrate 1. The semiconductor substrate 1 is electrically separated from the semiconductor substrate 1 by the mold semiconductor region 3.

The memory cell is a memory cell selecting MISF.
It has a stacked structure in which an information storage capacitive element C is arranged above the ETQs, and its plane dimensions are 0.44 μm in the X direction (left and right directions in FIG. 4) and in the Y direction (vertical direction in FIG. 4). 0.46 μm. It should be noted that the dimensions of the memory cell described above and the dimensions of each component of the memory cell described below are merely examples, and are not intended to limit the present invention.

MISFE for selecting a memory cell of a memory cell
TQs is of an n-channel type and is formed in the active region L of the p-type well 2. As shown in FIG. 4, the active region L is formed of an elongated island-shaped pattern extending straight along the X direction, and its dimension is 1.1 in the X direction.
0 μm and 0.24 μm in the Y direction. Each active region L has a memory cell selecting MISFET Q sharing one of a source and a drain (n-type semiconductor region 9).
Two s are formed adjacent to each other in the X direction.

The element isolation region surrounding the active region L is constituted by an element isolation groove 6 formed by embedding a silicon oxide film 5 in a shallow groove opened in the p-type well 2. The silicon oxide film 5 buried in the element isolation trench 6 is flattened so that its surface is substantially at the same height as the surface of the active region L. Since an element isolation region formed by such an element isolation groove 6 cannot have a bird's beak at an end of the active region L, an element isolation region (field) of the same size formed by a LOCOS (selective oxidation) method. The effective area is larger than that of the oxide film.

The memory cell selecting MISFET Qs mainly includes a gate oxide film 7, a gate electrode 8A, a source,
It is constituted by a pair of n-type semiconductor regions 9 constituting a drain. MISFET Qs for memory cell selection
The gate electrode 8A is integrally formed with the word line WL, and extends linearly along the Y direction with the same width and the same space. The width of the gate electrode 8A (word line WL), that is, the gate length, and two adjacent gate electrodes 8A
The space of (word line WL) is almost the same as the minimum processing size determined by the resolution limit of photolithography (for example, 0.22 μm). The gate electrode 8A (word line WL) is made of, for example, a low-resistance polycrystalline silicon film doped with an n-type impurity such as P (phosphorus), and a barrier metal such as a WN (tungsten nitride) film formed thereon. It has a polymetal structure composed of a layer and a refractory metal film such as a W (tungsten) film formed thereon. Since the gate electrode 8A (word line WL) having a polymetal structure has a lower electric resistance than a gate electrode formed of a polycrystalline silicon film or a polycide film, the signal delay of the word line can be reduced.

The peripheral circuit of the DRAM is an n-channel type MI.
It comprises an SFET Qn and a p-channel MISFET Qp. The n-channel MISFET Qn is formed in the p-type well 2 and mainly includes a gate oxide film 7, a gate electrode 8B, and a pair of n ⁺ -type semiconductor regions 10 and 10 constituting a source and a drain. Also, p
The channel type MISFET Qp is formed in the n-type well 4 and mainly includes a gate oxide film 7, a gate electrode 8C, and a pair of p ⁺ -type semiconductor regions 1 constituting a source and a drain.
1 and 11. Gate electrodes 8B, 8
C has the same polymetal structure as the gate electrode 8A (word line WL). N-channel MISFET Qn and p-channel MISFET Qp constituting peripheral circuits
Are manufactured with looser design rules than the memory cells, and the gate lengths of the gate electrodes 8B and 8C are, for example, 0.1.
32 μm.

A silicon nitride film 12 is formed above the gate electrode 8A (word line WL) of the memory cell selecting MISFET Qs. The upper and side walls of the silicon nitride film 12 and the gate electrode 8A (word line WL) are formed. A silicon nitride film 13 is formed on the side wall. Further, a silicon nitride film 12 is formed on each of the gate electrodes 8B and 8C of the MISFET of the peripheral circuit, and a side wall made of the silicon nitride film 13 is formed on each side wall of the gate electrodes 8B and 8C. The spacer 13s is formed.

As described later, the silicon nitride film 12 and the silicon nitride film 13 of the memory array are self-aligned (self-aligned) over the source and drain (n-type semiconductor regions 9 and 9) of the memory cell selection MISFET Qs. It is used as an etching stopper when forming a contact hole. Also, the side wall spacer 1 of the peripheral circuit
3s is used to make the source and drain of the n-channel MISFET Qn and the source and drain of the p-channel MISFET Qp have an LDD (Lightly Doped Drain) structure.

Memory cell selecting MISFET Qs, n-channel MISFET Qn and p-channel MISFET
An SOG film 16 is formed on each ETQp. Further, two layers of silicon oxide films 17 and 18 are formed further above the SOG film 16, and the surface of the upper silicon oxide film 18 is set to be substantially the same over the entire area of the semiconductor substrate 1. Is flattened.

The silicon oxide films 18 and 17 and the SOG film 1 are formed on a pair of n-type semiconductor regions 9 and 9 constituting the source and drain of the memory cell selecting MISFET Qs.
6 are formed. Plugs 21 made of a low-resistance polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) are embedded in these contact holes 19 and 20.

The diameter of the bottom of each of the contact holes 19 and 20 in the X direction is two opposing gate electrodes 8A.
It is defined by the space between the silicon nitride film 13 on one side wall of the (word line WL) and the silicon nitride film 13 on the other side wall. That is, the contact holes 19, 2
0 is self-aligned to the space of the gate electrode 8A (word line WL).

The diameter in the Y direction of one of the pair of contact holes 19 and 20 is substantially the same as the dimension in the Y direction of the active region L. On the other hand, the diameter of the other contact hole 19 (the contact hole on the n-type semiconductor region 9 shared by the two memory cell selecting MISFETs Qs) in the Y direction is larger than the dimension of the active region L in the Y direction. Is also big. That is, the contact hole 19 has a diameter in the Y direction in the X direction (at the upper end).
It is constituted by a substantially rectangular plane pattern having a diameter larger than the diameter, and a part thereof extends from the active region L onto the element isolation groove 6. By forming the contact hole 19 with such a pattern, when electrically connecting the bit line BL and the n-type semiconductor region 9 through the contact hole 19, the width of the bit line BL is partially increased. Therefore, it is not necessary to extend to the upper part of the active region L or part of the active region L in the direction of the bit line BL, so that the memory cell size can be reduced.

On the silicon oxide film 18, a silicon oxide film 28 is formed. A through hole 22 is formed in the silicon oxide film 28 above the contact hole 19, and a Ti film, a TiN
A plug 35 made of a conductive film in which a film and a W film are stacked is embedded. The plug 35 and the through hole 22
Plug 2 embedded in contact hole 19 below
A TiSi ₂ (titanium silicide) layer 37 generated by a reaction between a Ti film forming a part of the plug 35 and a polycrystalline silicon film forming the plug 21 is formed at the interface with the plug 1. The through hole 22 is arranged above the element isolation groove 6 deviating from the active region L.

The bit line B is formed on the silicon oxide film 28.
L is formed. The bit line BL is arranged above the element isolation groove 6, and linearly extends along the X direction with the same width and the same space. The pitch between two adjacent bit lines BL is equal to the dimension (=
0.46 μm). The bit line BL is made of a W film, and has a through hole 22 formed in the silicon oxide film 28 and an insulating film thereunder (the silicon oxide film 2).
8, 18, 17, SOG film 16 and gate oxide film 7)
One of the source and drain (2) of the memory cell selecting MISFET Qs through the contact hole 19 formed in
It is electrically connected to the n-type semiconductor region 9) shared by the memory cell selecting MISFETs Qs.

The space of the bit line BL is made as large as possible in order to reduce the parasitic capacitance formed between the bit line BL and the adjacent bit line BL as much as possible. The space of the bit line BL is, for example, 0.34 μm. In this case, the width of the bit line BL is 0.12 μm (= 10 μm), which is smaller than the minimum processing size determined by the resolution limit of photolithography.
0.46-0.34). That is, the interval between the bit lines BL is larger than the width and the interval between the word lines WL, and the width of the bit line BL is smaller than the width and the interval between the word lines WL. A method for forming the bit line BL with a width smaller than the minimum processing dimension will be described later.

By increasing the space of the bit line BL and reducing the parasitic capacitance, even if the memory cell size is reduced, the signal voltage for reading out the charge (information) stored in the information storage capacitor C is reduced. Can be bigger. Also, by increasing the space of the bit line BL, the opening margin of a through hole (through hole connecting the information storage capacitor C and the contact hole 20) 48 formed in the space region of the bit line BL described later is formed. Can be sufficiently secured, so that even if the memory cell size is reduced, the bit line BL and the through hole 48 can be formed.
It is possible to reliably prevent a short circuit with the inner conductor layer.

Further, since the bit line BL is made of metal (W), its sheet resistance can be reduced to about 2 Ω / □, so that information can be read and written at high speed. Further, since the bit line BL and the wirings 23 to 26 of the peripheral circuit described later can be formed simultaneously in the same process, the manufacturing process of the DRAM can be simplified. Further, by configuring the bit line BL with a metal (W) having high heat resistance and electromigration resistance, even if the width of the bit line BL is reduced to the resolution limit of photolithography or less, disconnection is reliably prevented. be able to.

First-layer wirings 23 to 26 are formed on the silicon oxide film 28 of the peripheral circuit. These wirings 23 to 26 are made of the same conductive material (W) as the bit line BL, and are formed simultaneously in a step of forming the bit line BL as described later. Wirings 23 to 26 are connected to the peripheral circuit through contact holes 30 to 34 formed in silicon oxide films 28, 18, 17 and SOG film 16.
It is electrically connected to ISFET (n-channel MISFETQn, p-channel MISFETQp).

MISFET of peripheral circuit and wirings 23 to 26
Inside the contact holes 30 to 34 connecting
A plug 35 made of a conductive film in which a Ti film, a TiN film, and a W film are stacked in this order from the lower layer is embedded. Also, of these contact holes 30 to 34, the MI of the peripheral circuit
At the bottom of the contact holes (30 to 33) formed above the source and drain (the n ⁺ type semiconductor region 10 and the p ⁺ type semiconductor region 11) of the SFET, a Ti film forming a part of the plug 35 and a semiconductor are formed. A TiSi ₂ layer 37 generated by a reaction with the substrate 1 (Si) is formed, thereby reducing the contact resistance between the plug 35 and the source and drain (the n ⁺ type semiconductor region 10 and the p ⁺ type semiconductor region 11). Have been.

The bit line BL and the first-layer wirings 23 to 26
A silicon oxide film 38 is formed on each of the silicon oxide films 38. The SOG is further formed on the silicon oxide film 38.
A film 39 is formed. The SOG film 39 is flattened so that its surface is substantially the same height over the entire area of the semiconductor substrate 1.

A silicon nitride film 44 is formed above the SOG film 39 of the memory array, and an information storage capacitor C is formed further above the silicon nitride film 44. The information storage capacitance element C includes a lower electrode (storage electrode) 45, an upper electrode (plate electrode) 47, and a Ta ₂ O ₅ (tantalum oxide) film 46 provided therebetween. The lower electrode 45 is made of, for example, a low-resistance polycrystalline silicon film doped with P (phosphorus).
The upper electrode 47 is made of, for example, a TiN film.

The lower electrode 45 of the information storage capacitor C is
It is composed of an elongated pattern extending straight in the X direction in FIG. 4, and its dimension is, for example, 0.77 μm in the X direction.
The m and Y directions are 0.31 μm. The lower electrode 45 is formed through a plug 49 buried in a through hole 48 penetrating the silicon nitride film 44, the SOG film 39, and the silicon oxide films 38, 28 thereunder.
The MISFET Qs for memory cell selection is electrically connected via the plug 21 to the other of the source and the drain (the n-type semiconductor region 9) of the MISFET Qs for memory cell selection. The through hole 48 formed between the lower electrode 45 and the contact hole 20 has a diameter smaller than the minimum processing dimension (for example, 0 mm) in order to reliably prevent a short circuit with the bit line BL or the plug 35 therebelow. .1
4 μm). The plug 49 embedded in the through hole 48 is made of, for example, a low-resistance polycrystalline silicon film doped with P (phosphorus).

On the SOG film 39 of the peripheral circuit, there is formed a silicon oxide film 50 having the same thickness as the lower electrode 45 of the information storage capacitor C and having a large thickness. By forming the silicon oxide film 50 of the peripheral circuit with such a large film thickness, the surface of the interlayer insulating film 56 formed on the information storage capacitor C has substantially the same height as the memory array and the peripheral circuit. become.

An interlayer insulating film 56 is formed above the information storage capacitor C, and second-layer wirings 52 and 53 are formed thereon. The interlayer insulating film 56 is composed of a silicon oxide film,
Reference numeral 3 denotes a conductive film mainly composed of Al (aluminum). Second layer wiring 53 formed in the peripheral circuit
Are electrically connected to the first layer wiring 26 through through holes 54 formed in the underlying insulating films (interlayer insulating film 56, silicon oxide film 50, SOG film 39, silicon oxide film 38). . A plug 55 made of, for example, a Ti film, a TiN film, and a W film is embedded in the through hole 54.

The second layers 52 and 53 have a second layer
A third interlayer insulating film 63 is formed, and a third
Wirings 57, 58, 59 of the layer are formed. The interlayer insulating film 63 is formed of a silicon oxide-based insulating film (for example, a three-layer insulating film including a silicon oxide film, an SOG film, and a silicon oxide film).
Reference numeral 59 denotes a conductive film mainly composed of Al, similarly to the wirings 52 and 53 of the second layer.

The third layer wiring 58 is electrically connected to the upper electrode 47 of the information storage capacitor C through through holes 60 formed in the interlayer insulating films 63 and 56 under the third layer. The third layer wiring 59 is electrically connected to the second layer wiring 53 through a through hole 61 formed in an interlayer insulating film 63 thereunder. Inside these through holes 60 and 61, for example, Ti
A plug 62 made of a film, a TiN film and a W film is embedded.

Next, an example of a method of manufacturing the DRAM having the above structure will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 6, an element isolation groove 6 is formed in an element isolation region on the main surface of a semiconductor substrate 1 made of single-crystal silicon of p-type and having a specific resistance of about 10 Ωcm. The element isolation groove 6 is etched to a depth of 3 by etching the surface of the semiconductor substrate 1.
After forming a groove of about 100 to 400 nm, and then depositing a silicon oxide film 5 on the semiconductor substrate 1 including the inside of the groove by a CVD method, the silicon oxide film 5 is subjected to chemical mechanical polishing (C
It is formed by polishing back by chemical mechanical polishing (CMP). The silicon oxide film 5 is flattened so that its surface is substantially the same height as the surface of the active region. By forming the element isolation groove 6, as shown in FIG. 7, a region (memory array) where a memory cell is formed
, An active region L having an elongated island-like pattern surrounded by the element isolation groove 6 is formed at the same time. In addition, an active region (not shown) surrounded by the element isolation trench 6 is formed simultaneously in a region where a peripheral circuit is formed.

Next, as shown in FIG. 8, an n-type impurity, for example, P (phosphorus) is ion-implanted into the semiconductor substrate 1 of the memory array to form an n-type semiconductor region 3, and then the memory array and peripheral circuits are formed. Part (n-channel MISFET Qn
And p-type impurities, for example, B (boron)
Is ion-implanted to form a p-type well 2, and an n-type impurity, for example, P (phosphorus) is ion-implanted into another part of the peripheral circuit (a region where the p-channel MISFET Qp is formed) to form an n-type well 4. Form.

Subsequently, impurities for adjusting the threshold voltage of the MISFET, for example, BF ₂ (boron fluoride) are ion-implanted into the p-type well 2 and the n-type well 4,
Next, after the respective surfaces of the p-type well 2 and the n-type well 4 are washed with a HF (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is wet-oxidized and the respective surfaces of the p-type well 2 and the n-type well 4 are formed. A clean gate oxide film 7 having a thickness of about 7 nm is formed.

Next, as shown in FIGS. 9 and 10, a gate electrode 8A (word line WL) is formed on the gate oxide film 7.
And gate electrodes 8B and 8C. Gate electrode 8
A (word line WL) and gate electrodes 8B and 8C have a film thickness 70 doped with an n-type impurity such as P (phosphorus).
A polycrystalline silicon film having a thickness of about nm is deposited on the semiconductor substrate 1 by a CVD method, and a WN (tungsten nitride) film having a thickness of about 5 nm and a W film having a thickness of about 100 nm are deposited thereon by sputtering. And a film thickness 2
After a silicon nitride film 12 of about 00 nm is deposited by a CVD method, the film is formed by patterning these films using a photoresist film as a mask. The WN film functions as a barrier layer that prevents the W film and the polycrystalline silicon film from reacting during the high-temperature heat treatment to form a high-resistance silicide layer at the interface between them. As the barrier layer, a WN film refractory metal nitride film, for example, a TiN (titanium nitride) film can be used. Gate electrode 8 having a polymetal structure mainly composed of a refractory metal film and a polycrystalline silicon film
A (word line WL) has a lower electrical resistance than a gate electrode formed of a polycrystalline silicon film or a polycide film (a laminated film of a high melting point metal silicide film and a polycrystalline silicon film), and therefore, the word line signal Delay can be reduced. The gate electrode 8A (word line WL) of the MISFET Qs for memory cell selection uses, for example, an exposure technique using a KrF excimer laser having a wavelength of 248 nm as a light source and a phase shift technique, and has a width and a space of about 0.22 μm each. Formed.

Next, as shown in FIG.
Then, a p-type impurity, for example, B (boron) is ion-implanted to form ap ^- type semiconductor region 15 in the n-type well 4 on both sides of the gate electrode 8C. Further, an n-type impurity, for example, P (phosphorus) is ion-implanted into the p-type well 2 to form an n ^- type semiconductor region 9a in the p-type well 2 on both sides of the gate electrode 8A. An n ⁻ type semiconductor region 14 is formed in the well 2. Through the steps so far, the memory cell selecting MISFET Qs is substantially completed.

Next, as shown in FIG.
After a silicon nitride film 13 having a thickness of about 50 nm is deposited thereon by the CVD method, the silicon nitride film 13 of the memory array is covered with a photoresist film (not shown), and the silicon nitride film 13 of the peripheral circuit is anisotropically etched. Thereby, the sidewall spacers 13s are formed on the side walls of the gate electrodes 8B and 8C of the peripheral circuit. This etching is performed using a gas that etches the silicon nitride film 13 with a high selectivity in order to minimize the amount of shaving of the silicon oxide film 5 and the gate oxide film 7 embedded in the element isolation trench 6. Further, in order to minimize the amount of the silicon nitride film 12 shaved on the gate electrodes 8B and 8C, the amount of over-etching is kept to a necessary minimum.

Next, as shown in FIG.
A p-type impurity, for example, B (boron) is ion-implanted into the p-type well 4 to form a p ⁺ -type semiconductor region 11 (source, drain) of the p-channel MISFET Qp. For example, As (arsenic) is ion-implanted and n ^{+ of the} n-channel type MISFET Qn is implanted.
A type semiconductor region 10 (source, drain) is formed. By the steps so far, the p-channel MISFET Qp and the n-channel MISFET Qn having the LDD structure
Is almost completed.

Next, as shown in FIG.
An SOG film 16 having a thickness of about 300 nm is spin-coated thereon,
After performing a bake treatment in an oxygen atmosphere at about 400 ° C. containing water vapor, heat treatment is further performed at 800 ° C. for about 1 minute to densify (densify) the SOG film 16. S
For the OG film 16, for example, a polysilazane-based inorganic SOG is used.

The SOG film 16 has a higher reflow property than a glass flow film such as a BPSG film and has an excellent gap fill property in a fine space. No voids are generated even when embedded in the space of 8A (word line WL). In addition, since the SOG film 16 can achieve high reflow properties without performing high-temperature and long-time heat treatment required for a BPSG film or the like, the memory cell selecting MISF
ETFETs for ETQs source / drain and peripheral circuits
(N channel MISFET Qn, p channel MIS
FET Qp) can suppress the thermal diffusion of the impurities implanted into the source and drain of the FET Qp, thereby achieving a shallow junction, and at the time of heat treatment, the metal (W) forming the gate electrode 8A (word line WL) and the gate electrodes 8B and 8C. Film) can be suppressed, so that the MISFE for memory cell selection can be suppressed.
High performance of the MISFET of the TQs and the peripheral circuit can be realized.

Next, as shown in FIG.
A silicon oxide film 17 having a thickness of about 600 nm is deposited on the upper surface of the silicon oxide film 17. Then, the silicon oxide film 17 is polished by the CMP method to flatten the surface thereof. accumulate. The upper silicon oxide film 18 is deposited in order to repair fine scratches on the surface of the lower silicon oxide film 17 generated when the upper silicon oxide film 18 is polished by the CMP method.

Next, as shown in FIG. 16, the n ⁻ type semiconductor region (source, source, etc.) of the memory cell selecting MISFET Qs is dry-etched using the photoresist film 27 as a mask.
The silicon oxide films 18, 17 on the drain (9a) are removed. This etching is performed using a gas for etching the silicon oxide film 17 with a high selectivity in order to prevent the silicon nitride film 13 under the silicon oxide film 17 from being removed.

[0074] Subsequently, as shown in FIG. 17, n by dry etching using the photoresist film 27 as a mask ^-
By removing the silicon nitride film 13 on the upper part of the n ^- type semiconductor region (source, drain) 9a and then removing the thin gate oxide film 7 thereunder, one upper part of the n ^- type semiconductor region (source, drain) 9a is removed. Contact hole 1
9, and a contact hole 20 is formed on the other upper part. The contact hole 20 is formed so that the diameter in each of the X direction and the Y direction is about 0.24 μm. Also, the other contact hole 19 (n shared by the two memory cell selecting MISFETs Qs)
As shown in FIGS. 18 and 19, the contact hole on the mold semiconductor region 9 is formed in an elongated pattern such that the diameter in the X direction is about 0.24 μm and the diameter in the Y direction is about 0.46 μm.

The etching of the silicon nitride film 13 is performed in order to minimize the shaving amount of the semiconductor substrate 1 and the element isolation groove 6.
The etching is performed using a gas that etches the silicon nitride film 13 with a high selectivity. This etching is performed under such conditions that the silicon nitride film 13 is anisotropically etched.
The silicon nitride film 13 is left on the side wall of the gate electrode 8A (word line WL). Thereby, fine contact holes 19 and 20 whose bottom diameter (diameter in the X direction) is equal to or less than the resolution limit of photolithography can be formed in a self-alignment manner with the space of the gate electrode 8A (word line WL). .

Next, after removing the photoresist film 27, the contact holes 19, 2 are etched using a hydrofluoric acid-based etching solution (for example, a mixed solution of hydrofluoric acid and ammonium fluoride).
The surface of the semiconductor substrate 1 exposed at the bottom of the substrate 0 is washed to remove dry etching residues, photoresist residues, and the like. At this time, the SOG film 16 exposed on the side walls of the contact holes 19 and 20 is also exposed to the etching solution.
SOG film 1 densified (densified) at a high temperature of about 100 ° C.
No. 6 has a higher resistance to hydrofluoric acid-based etchant than the SOG film not subjected to the densify process.
Side walls 9 and 20 are not largely undercut. As a result, the contact holes 19, 2
0 can be reliably prevented from shorting between the plugs 21 embedded in the inside of the plug.

After the contact holes 19 and 20 are formed, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 2 through the contact holes 19 and 20 to obtain a memory cell selecting MISFET.
P-type well 2 deeper than the source and drain of Qs
May be formed with an n-type semiconductor layer. Since the n-type semiconductor layer has an effect of reducing an electric field concentrated at the ends of the source and the drain, the leak current at the ends of the source and the drain can be reduced and the refresh characteristics of the memory cell can be improved.

Next, as shown in FIGS. 20 and 21,
A plug 21 is formed inside the contact holes 19 and 20. The plug 21 has a thickness 300 in which an n-type impurity (for example, As (arsenic)) is doped on the silicon oxide film 18.
After depositing a polycrystalline silicon film having a thickness of about nm by the CVD method, the polycrystalline silicon film is polished by the CMP method and left inside the contact holes 19 and 20.

Subsequently, as shown in FIGS. 22 and 23, after a silicon oxide film 28 having a thickness of about 200 nm is deposited on the silicon oxide film 18 by the CVD method, the film is formed at 800 ° C. for 1 minute in a nitrogen gas atmosphere. A degree of heat treatment is performed. By this heat treatment, the n-type impurity in the polycrystalline silicon film forming the plug 21 diffuses from the bottom of the contact holes 19 and 20 into the n ⁻ -type semiconductor region 9a of the MISFET Qs for selecting a memory cell, and the low-resistance n-type semiconductor region (Source, drain) 9 is formed.

Next, as shown in FIGS. 24 and 25,
By removing the silicon oxide film 28 above the contact hole 19 by dry etching using a photoresist film (not shown) as a mask, a through hole 22 having a diameter of about 0.24 μm is formed. This through hole 22
Are arranged above the element isolation groove 6 deviating from the active region L.

Next, as shown in FIG. 26, the silicon oxide films 28, 18, 17 and the SOG film 1 of the peripheral circuit are dry-etched using a photoresist film (not shown) as a mask.
By removing the gate oxide film 6 and the gate oxide film 7, the contact holes 30, 31 are formed above the n ⁺ type semiconductor region 10 (source, drain) of the n channel type MISFET Qn.
Are formed, and contact holes 32 and 33 are formed above the p ⁺ type semiconductor region 11 (source and drain) of the p-channel type MISFET Qp. At the same time, a contact hole 34 is formed above the gate electrode 8C of the p-channel MISFET Qp to form an n-channel MISFE.
A contact hole (not shown) is formed above the gate electrode 8B of TQn.

As described above, the etching for forming the through holes 22 and the etching for forming the contact holes 30 to 34 are performed in different steps, so that when forming the deep contact holes 30 to 34 in the peripheral circuit, the memory array is formed. Plug 2 exposed at bottom of shallow through hole 22
1 can be prevented from being cut deeply. The formation of the through holes 22 and the formation of the contact holes 30 to 34 may be performed in the reverse order.

Next, as shown in FIG. 27, a Ti film 36 having a thickness of about 40 nm is deposited on the silicon oxide film 28 including the insides of the contact holes 30 to 34 and the through holes 22. The Ti film 36 is deposited by using a highly directional sputtering method such as collimation sputtering so that a thickness of about 10 nm or more can be ensured even at the bottoms of the contact holes 30 to 34 having a large aspect ratio.

Subsequently, without exposing the Ti film 36 to the air, a heat treatment is performed at 650 ° C. for about 30 seconds in an Ar (argon) gas atmosphere, and further, 750 ° C. in a nitrogen gas atmosphere.
Heat treatment is performed at about 1 minute. By this heat treatment, FIG.
As shown in FIG. 8, the Si substrate at the bottom of the contact holes 30 to 33 reacts with the Ti film 36 to form an n-channel MIS.
The film thickness 10 is formed on the surface of the n ⁺ -type semiconductor region 10 (source and drain) of the FET Qn and the surface of the p ⁺ -type semiconductor region 11 (source and drain) of the p-channel MISFET Qp.
A TiSi ₂ layer 37 of about nm is formed. In addition, the surface of the thin Ti film 36 deposited on the sidewalls of the contact holes 30 to 34 is nitrided by the heat treatment in the nitrogen gas atmosphere, and a stable film hardly reacts with Si.

At this time, the surface of the Ti film 36 above the silicon oxide film 28 is also nitrided, but the other parts remain unreacted without being nitrided. Also, through hole 2
2 is formed on the surface of the plug 21 at the bottom of the plug 2 by the reaction between the polycrystalline silicon film constituting the plug 21 and the Ti film 36.
An Si ₂ layer 37 is formed.

At the bottom of the contact holes 30 to 33, Ti
By forming the Si ₂ layer 37, plugs 35 are formed in the contact holes 30 to 33 in the next step
And the source and drain (n ⁺
Resistance of the portion where the semiconductor region 10 and the p ⁺ type semiconductor region 11) are in contact with each other can be reduced to 1 kΩ or less.
High-speed operation of peripheral circuits such as the above becomes possible. The silicide layer at the bottom of the contact holes 30 to 33 is made of a refractory metal silicide other than TiSi ₂ , for example, CoSi ₂ (cobalt silicide), TaSi ₂ (tantalum silicide),
It can also be made of MoSi ₂ (molybdenum silicide) or the like.

Next, as shown in FIG. 29, a TiN film 40 having a thickness of about 30 nm is deposited on the Ti film 36 by the CVD method. Since the CVD method has a better step coverage than the sputtering method, the bottom of each of the contact holes 30 to 34 having a large aspect ratio has a T
An iN film 40 can be deposited. Subsequently, tungsten hexafluoride (WF ₆ ), hydrogen and monosilane (Si
A thick W film 41 having a thickness of about 300 nm is deposited on the TiN film 40 by a CVD method using H ₄ ) as a source gas, and the inside of each of the contact holes 30 to 34 and the through hole 22 is completely formed by the W film 41. Embed in

At this time, if the unreacted Ti film 36 is removed with an etching solution immediately after the formation of the TiSi ₂ layer 37,
The etchant also penetrates into the inside of the contact hole 34 formed above the gate electrode 8C of the p-channel MISFET Qp and the inside of the contact hole (not shown) formed above the gate electrode 8B of the n-channel MISFET Qn. Gate electrode 8 composed of a structure
The surfaces (W films) of B and 8C are etched. In order to prevent this, in the present embodiment, after the TiSi ₂ layer 37 is formed at the bottom of the contact holes 30 to 33, the upper part of the silicon oxide film 28 and the contact hole 30 are formed.
The TiN film 40 and the W film 41 are deposited on the unreacted Ti film 36 remaining inside the layers.

Next, as shown in FIGS. 30 and 31,
W film 4 on silicon oxide film 28 using CMP method
1. By removing (polished back) the TiN film 40 and the Ti film 36, the contact holes 30 to 34 are removed.
And the W film 4 inside each of the through holes 22.
1. A plug 35 composed of a TiN film 40 and a Ti film 36 is formed. This plug 35 is used for the silicon oxide film 2
8 may be formed by removing (etching back) the W film 41, the TiN film 40, and the Ti film 36 on the upper portion of the substrate 8 by dry etching. At this time, the silicon oxide film 2
If the removal of the Ti film 36 on the surface 8 is insufficient, the wirings (23 to 26) formed on the silicon oxide film 28 in the next step
Care must be taken because part of the silicon oxide film 28 may be peeled off from the surface of the silicon oxide film 28 during the subsequent high-temperature heat treatment.

Since the plug 35 is mainly composed of the W film 41 which is a high melting point metal, it has low resistance and high heat resistance. Also, the T film formed under the W film 41
The iN film 40 functions as a barrier layer that prevents the occurrence of defects (encroachment and wormholes) due to the reaction between tungsten hexafluoride and Si when the W film 41 is deposited by the CVD method. Functions as a barrier layer for preventing a reaction (silicidation reaction) between the W film 41 and the Si substrate in the high temperature heat treatment step. This barrier layer includes
A refractory metal nitride other than TiN (for example, a WN film) can also be used.

The plug 35 is made of Ti without using the W film 41.
The N film 40 may be mainly composed. That is, the plug 35 may be formed by embedding the thick TiN film 40 inside each of the contact holes 30 to 34 and the through hole 22. In this case, the resistance of the plug 35 is somewhat higher than in the case where the W film 41 is mainly used, but the W film 42 deposited on the silicon oxide film 28 in the next step is dry-etched to form a bit line. When forming the BL and the first-layer wirings 23 to 26 of the peripheral circuit, T
Since the iN film 40 serves as an etching stopper, the wiring 23
26 to the contact holes 30 to 34 are significantly improved, and the degree of freedom in the layout of the wirings 23 to 26 is greatly improved.

Next, the bit lines BL and the first-layer wirings 23 to 26 of the peripheral circuit are formed on the silicon oxide film 28 by the following method.

First, the surface of the silicon oxide film 28 is wet-cleaned to sufficiently remove the polishing residue, and then, as shown in FIG. 32 and FIG.
A film 42 is deposited by a sputtering method, and then a photoresist film 43 is spin-coated on the W film 42. Subsequently, the bit line pattern 43a and the wiring pattern 43b are transferred to the photoresist film 43 using an exposure light source made of a KrF excimer laser and a phase shift mask. At this time, the width and space of the bit line pattern 43a transferred to the photoresist film 43 are each 0.2.
It is about 3 μm.

Next, as shown in FIGS. 34 and 35,
By shaving the photoresist film 43 by ashing using ozone, the width of the bit line pattern 43a is reduced to 0.1.
It is thinned to about 2 μm. The ashing conditions at this time are as follows: the semiconductor substrate 1 inserted into the reaction chamber of the ashing device.
Is heated at a predetermined temperature, and nitrogen gas containing, for example, 100 g of ozone per 1 m ³ is introduced at a flow rate of 18 liters per minute.

FIG. 36 is a graph showing the relationship between the substrate temperature and the ozone ashing speed. As shown by the circles in the figure, the rate at which the photoresist film is ashed (etched) increases linearly as the substrate temperature increases. For example, one side of the width is reduced by 40 nm, and the width is reduced by a total of 80 nm on both sides. It can be seen that ashing may be performed at 162 ° C. for 1 minute. FIG. 37 shows that the substrate temperature is constant (150 ° C.).
4 is a graph showing the relationship between the ozone ashing (etching) time and the amount of dimensional shift of the resist in the case of FIG. A minus on the vertical axis indicates a decrease in the film thickness. As shown in the figure, the thickness of the photoresist film decreases linearly as the ashing time increases. For example, in order to reduce the resist pattern size by 40 nm, it is sufficient to perform ashing for 40 seconds. . FIG. 38 is a graph showing the distribution of the ozone ashing amount in the wafer surface. As shown in the figure, the average value when ashing is performed at 150 ° C. for 60 seconds is 23.7 nm, and the variation is ± 13.7 nm.

FIG. 39 is a graph showing variations in resist pattern dimensions before and after ozone ashing. Resist pattern dimensions before ashing (average value = 181.5n)
The variation in m) is ± 8.7 nm, which is three times the standard deviation. The average value of the resist pattern dimension when ashing was performed at 150 ° C. for 60 seconds was 132.3 nm, and the variation was ± 8.5 nm, which is three times the standard deviation.

On the other hand, FIG. 40 is a graph showing variations in resist pattern dimensions before and after ashing when oxygen plasma is used instead of ozone. The variation of the resist pattern dimension (average value: 175.2 nm) before ashing is ± 9.0 nm, which is three times the standard deviation. 100 ℃
The average value of the resist pattern dimension when ashing was performed for 60 seconds was 106.0 nm, and the variation was ± 19.0 nm, which was three times the standard deviation.

From the above, it can be seen that by controlling the substrate temperature and the ozone ashing time, the shaving amount of the photoresist film can be controlled with high accuracy. Although the substrate temperature at the time of ashing the photoresist film varies depending on the resist material, it is preferable that the temperature is not higher than the post-bake temperature at the time of forming the resist pattern. It has been confirmed that ashing at a temperature higher than the post-bake temperature causes deformation of the resist pattern, resulting in a defective shape. When the photoresist film is thinned by ashing using ozone, the ashing may be promoted by irradiating ozone with ultraviolet rays.

A bit line pattern 43a having a width (0.12 μm) finer than the minimum processing size is formed on the photoresist film 43.
First, a pattern is formed under the condition (width / space) where the dimensional control of width and space is the best, and then
The photoresist film 43 is shaved by the above-described ashing to reduce the width of the pattern. On the other hand, the bit line pattern 43a having a width (0.12 μm) finer than the minimum processing size.
If lithography is performed only by one lithography, high dimensional accuracy cannot be obtained, so that the width of the lithography varies.

Since the W film 42 has a high light reflectance, the photoresist film 43 may cause halation at the time of exposure, and the dimensional accuracy of the pattern (width and space) may be reduced. In order to prevent this, a thin anti-reflection film is deposited on the W film 42 before the photoresist film 4
3 may be applied. An organic material or a metal material having a low light reflectance (for example, a TiN film) is used for the antireflection film.

Next, by dry-etching the W film 42 using the photoresist film 43 as a mask, a bit line BL is formed in the memory array as shown in FIGS. First layer wiring 2
3 to 26 are formed. After that, the photoresist film 43 is removed by ashing using ozone.

Here, the results of the study on the adhesion between the silicon oxide film and various metal films deposited thereon will be described.

[0103]

[Table 1]

Table 1 shows that six types of metal films (samples 1 to 6) were deposited on the surface of a silicon oxide film deposited by a plasma CVD method, and were heat-treated in a nitrogen atmosphere at 800 ° C. for 5 minutes. It is a summary of the results of evaluating the adhesion. In all samples, W films were deposited by a sputtering method, and the film thickness was 300 nm. In addition, TiN of samples 1 to 5
All films are deposited by reactive sputtering and have a thickness of 5
It was set to 0 nm. The TiN _x films of Samples 2, 3 and 4 were deposited by changing the composition ratio (x) by the reactive sputtering method.
Specifically, the composition ratio (x) was changed by adjusting the nitrogen partial pressure of the Ar (argon) -nitrogen mixed gas. The Ti film of Sample 1 was deposited by a sputtering method, and the thickness was 50 nm.
And

As shown in the table, samples 1 to 4 peeled off at the interface, while samples 5 and 6 did not peel off at all. From this, it has been found that when high-temperature heat treatment is performed in a state in which the Ti film or the Ti compound film containing an excessive amount of Ti and the silicon oxide film are in contact with each other, film peeling occurs. Therefore, when looking at the thermochemical generation energy when generating an oxide, the energy change is such that Si is easier to form an oxide than W, and Ti is more easily to form an oxide than Si. I have. Therefore, it is presumed that the property peculiar to this substance is the cause of the above-mentioned film peeling. Further, even when Ti is present at the interface, if it is present not as a simple substance of Ti but as a stable nitrogen compound (TiN), energy for breaking the Ti—N bond is required. It seems that the cause did not occur.

In the above-described manufacturing method, the silicon oxide film 2
8, the W film 41, the TiN film 40, and the Ti film 36 are once removed to form plugs 35 inside the contact holes 30 to 34 and the inside of the through holes 22, and then a new plug is formed on the silicon oxide film 28. Is patterned to form bit lines BL and wirings 23 to 26. Therefore, according to this method, the W film 41, the TiN film 40, and the Ti film 36 are patterned to form the bit line BL.
Although the number of manufacturing steps is increased as compared with the case where the wirings 23 to 26 are formed, the bit lines BL and the wirings 23 to 26 are formed by a high-temperature heat treatment performed later when the information storage capacitor C is formed above the bit line BL. A defect that causes film peeling can be reliably prevented.

After the plug 35 is formed inside the contact holes 30 to 34 having a large aspect ratio, the W film 4 for forming the bit lines BL and the wirings 23 to 26 is formed.
According to the above-described manufacturing method in which the W film 42 is deposited on the silicon oxide film 28, it is not necessary to consider the burying of the film in the contact holes 30 to 34 when the W film 42 is deposited. Can be deposited in a thin film thickness.
That is, according to this manufacturing method, the thickness of the bit line BL can be reduced, so that the parasitic capacitance formed between the adjacent bit line BL can be further reduced.

Furthermore, the surface of the silicon oxide film 28 is
It is polished and flattened by a P method, and a thin W film 4 is formed thereon.
By depositing No. 2, the amount of over-etching when etching the W film 42 can be reduced, so that the plug 35 inside the through hole 22 having a diameter larger than the width of the photoresist film 43 can be cut deeply. Can be prevented.

The bit line BL and the wirings 23 to 26 are
It may be formed using a W film deposited by the VD method or a stacked film of the W film and the TiN film. In addition, other refractory metals (for example, Mo film, T
a film) or a single-layer film of a nitride thereof or a laminated film thereof.

Next, as shown in FIG.
And a film thickness 1 on each of the first-layer wirings 23 to 26.
A silicon oxide film 38 having a thickness of about 00 nm is deposited, and an SOG film 3 having a thickness of about 250 nm is formed on the silicon oxide film 38.
After spin coating 9, the surface of the SOG film 39 is baked in an oxygen atmosphere containing steam at about 400 ° C., and further subjected to heat treatment at 800 ° C. for about 1 minute to densify (densify) the SOG film 39. Flatten.

As described above, the surface of the silicon oxide film 28 is flattened, the thin W film 42 is deposited thereon, and the bit line BL and the first-layer wirings 23 to 26 are formed. As a result, the step on the base of the SOG film 39 can be reduced, so that the upper part of each of the bit line BL and the wirings 23 to 26 is formed of a two-layer insulating film (silicon oxide film 38, S
The flattening can be performed only by the OG film 39). That is, as in the case where the upper portions of the gate electrodes 8A, 8B, and 8C are flattened, a silicon oxide film (17) is further deposited on the SOG film (16) and the surface thereof is not polished by the CMP method. Since excellent flatness can be ensured, the manufacturing process can be shortened.

The bit line BL and the first-layer wiring 23
In the case where the level difference due to .about.26 is small, planarization can be achieved only by depositing a thick silicon oxide film 38 without using the SOG film 39. On the other hand, the bit line BL and the wiring 23
If the SOG film 39 alone does not provide sufficient flatness, the surface of the SOG film 39 is polished by the CMP method, and the SOG film 39 is further formed thereon.
A silicon oxide film for repairing fine polishing scratches on the surface of the substrate may be deposited. If the temperature for densifying the SOG film 39 cannot be increased so high, a silicon oxide film may be further deposited on the SOG film 39 to compensate for the decrease in moisture resistance.

Next, as shown in FIG.
A polycrystalline silicon film 70 having a thickness of about 200 nm
After deposition by the VD method, the polysilicon film 70 is dry-etched using the photoresist film as a mask, so that the through-hole 7 is formed above the contact hole 20.
Form one. The through hole 71 is formed so that its diameter is substantially equal to the minimum processing size (for example, 0.24 μm).

Next, as shown in FIG. 46, a side wall spacer 72 made of a polycrystalline silicon film is formed on the side wall of the through hole 71. The sidewall spacer 72 is formed by depositing a thin second polycrystalline silicon film (not shown) having a thickness of about 60 nm on the polycrystalline silicon film 70 including the inside of the through hole 71 by a CVD method, and then depositing the polycrystalline silicon film. The silicon film is anisotropically etched to make through holes 71
Formed on the side wall of the substrate. By forming the sidewall spacers 72, the through holes 71 are formed.
Is smaller than the minimum processing size (for example, 0.14 μm).
m).

Next, using the polycrystalline silicon film 70 and the sidewall spacers 72 as a mask, the insulating film (SOG film 39, silicon oxide film 38,
As shown in FIGS. 47 and 48, a through hole 48 reaching the contact hole 20 through a space region between the bit line BL and the bit line BL adjacent to the bit line BL is formed by dry-etching 8).

Since the through hole 48 is formed using the side wall spacer 71 on the side wall of the through hole 71 having an inner diameter smaller than the minimum processing size as a mask, the inner diameter is smaller than the minimum processing size (for example, 0.1 mm). 14μ
m). As a result, a sufficient alignment margin between the space region of the bit line BL and the through hole 48 can be ensured, so that the plug 49 embedded in the through hole 48 in the next step is replaced with the bit line BL or the plug under the bit line BL. It is possible to reliably prevent a short circuit with 35.

Next, as shown in FIG. 49, an approximately 200 nm-thick polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) is formed on the polycrystalline silicon film 70 including the inside of the through hole 48. (Not shown) was deposited by a CVD method, and then this polycrystalline silicon film was etched back together with the polycrystalline silicon film 70 and the sidewall spacers 72 to form a polycrystalline silicon film inside the through hole 48. The plug 49 is formed.

Next, as shown in FIG.
A silicon nitride film 44 having a thickness of about 200 nm
After the deposition by the method D, the silicon nitride film 44 of the peripheral circuit is removed by dry etching using a photoresist film (not shown) as a mask. The silicon nitride film 44 remaining in the memory array is used for the lower electrode 4 of the information storage capacitor C described later.
5 is used as an etching stopper when the silicon oxide film is etched in the step of forming 5.

Next, as shown in FIG. 51, after depositing a silicon oxide film 50 on the silicon nitride film 44 by a CVD method, using a photoresist film (not shown) as a mask, the silicon oxide film 50 and its Lower silicon nitride film 44
Is dry-etched to form through holes 48.
A concave groove 73 is formed in the upper part of. Since the lower electrode 45 of the information storage capacitor C is formed along the inner wall of the concave groove 73, in order to increase the surface area of the lower electrode 45 and increase the amount of stored charges, the thickness of the silicon oxide film 50 is increased. It is necessary to deposit with a thickness (for example, about 1.3 μm).

Next, as shown in FIG. 52, an approximately 60 nm-thick polycrystalline silicon film 45A doped with an n-type impurity (for example, P (phosphorus)) is formed on the silicon oxide film 50 including the inside of the concave groove 73. Is deposited by a CVD method. This polycrystalline silicon film 45A is used as a lower electrode material of the information storage capacitor C.

Next, as shown in FIG. 53, a 300 nm thick film is formed on the polycrystalline silicon film 45A including the inside of the concave groove 73.
After the SOG film 74 is applied by spin coating and then heat-treated at about 400 ° C. to bake the SOG film 74, the SOG film 74 outside the concave groove 73 is etched back and removed.

Next, as shown in FIG. 54, the upper part of the polycrystalline silicon film 45A of the peripheral circuit is covered with a photoresist film 75, and the polycrystalline silicon film 45A of the upper part of the silicon oxide film 50 of the memory array is etched back. As a result, the lower electrode 45 is formed along the inner wall of the concave groove 73. The lower electrode 45 may be formed of a conductive film other than the polycrystalline silicon film 45A. The conductive film for the lower electrode is
A conductive material having heat resistance and oxidation resistance not deteriorated by the high-temperature heat treatment of the capacitor insulating film performed in the next step, for example, a high melting point metal such as W or Ru (ruthenium), RuO (ruthenium oxide), IrO It is desirable to use a conductive metal oxide such as (iridium oxide).

Next, as shown in FIG. 55, the silicon oxide film 50 remaining in the gap between the grooves 73 and the SOG film 74 inside the grooves 73 are simultaneously etched with a hydrofluoric acid-based etching solution. After the removal, the cylindrical lower electrode 45 is completed by removing the polycrystalline silicon film 45A of the peripheral circuit by dry etching using a photoresist film (not shown) as a mask. Since the silicon nitride film 44 is formed at the bottom of the silicon oxide film 50 in the gap between the concave grooves, the lower SOG film 39 is not etched when the silicon oxide film 50 is wet-etched. At this time, since the surface of the peripheral circuit is covered with the polycrystalline silicon film 45A, the underlying thick silicon oxide film 50 is not etched.

Furthermore, by leaving the thick silicon oxide film 50 in the peripheral circuit, the surfaces of the interlayer insulating films 56 and 63 formed in the upper layer of the information storage capacitive element C in a later step become peripheral to the memory array. Since the height is almost the same as that of the circuit, the second-layer wirings 52 and 53 disposed above the interlayer insulating film 56 and the third-layer wirings 57 to 58 disposed above the interlayer insulating film 63. , And the formation of through holes 60 and 61 for connecting the second layer and the third layer wiring are facilitated.

Next, at 800.degree.
After forming the thin nitride film (not shown) on the surface of the lower electrode 45 by performing a heat treatment at about minute, as shown in FIG. 56, a thin film thickness of about 14nm on top of the lower electrode 45 Ta ₂ O ₅ ( A tantalum oxide film 46 is deposited. The nitride film on the surface of the lower electrode 45 is formed to prevent the polycrystalline silicon film (45A) constituting the lower electrode 45 from being oxidized by the next heat treatment. The Ta ₂ O ₅ film 46 is deposited by, for example, a CVD method using pentaethoxy tantalum (Ta (OC ₂ H ₅ ) ₅ ) as a source gas. Since the Ta ₂ O ₅ film 46 deposited by the CVD method has good step coverage, the Ta ₂ O ₅ film 46 is deposited with a substantially uniform thickness on the entire surface of the lower electrode 45 having a three-dimensional cylindrical shape.

Subsequently, a Ta film was formed in an oxidizing atmosphere at 800 ° C.
_{The 2} O ₅ film 46 is heat-treated for about 3 minutes. By performing this high-temperature heat treatment, crystal defects in the film are repaired, and a high-quality Ta ₂ O ₅ film 46 is obtained. As a result, the leakage current of the information storage capacitor C can be reduced.
A DRAM with improved refresh characteristics can be manufactured.

The lower electrode 4 of the information storage capacitive element C
5 is formed in a three-dimensional cylindrical shape to increase its surface area, and the capacitance insulating film is made of a Ta ₂ O ₅ film 46 having a dielectric constant of about 20 to 25, so that even if the memory cell is miniaturized, information can be stored even when the memory cell is miniaturized. It is possible to secure a sufficient amount of accumulated charges for holding.

The lower bit line BL and the first layer wiring 2 formed before the deposition of the Ta ₂ O ₅ film 46 are formed.
Since the W-films _{3 to} 26 have good adhesion to the silicon oxide-based insulating film, the bit lines BL and the wirings 23 to 26 are peeled off due to the high-temperature heat treatment of the Ta ₂ O ₅ film 46. Can be reliably prevented.

Further, since the bit line is formed of a W film having high heat resistance, the bit line BL formed with a fine width smaller than the minimum processing size is deteriorated due to the high temperature heat treatment of the Ta ₂ O ₅ film 46. It is possible to reliably prevent a defect such as breakage or disconnection. Further, the MISFET of the peripheral circuit and the first
Contact hole 3 for connecting with wirings 23 to 26 of the layer
By forming the plugs 35 inside 0 to 35 from a conductive material having high heat resistance (W film / TiN film / Ti film),
It is possible to prevent problems such as an increase in source / drain leakage current and an increase in contact resistance due to the high-temperature heat treatment of the a ₂ O ₅ film 46.

For example, BST, STO, BaTiO ₃ (barium titanate), PbTiO ₃ (lead titanate), PZT (PbZr)
_X Ti _1-X O ₃ ), PLT (PbLa _X Ti
_1-X O ₃ ) and a high (ferro) dielectric film made of a metal oxide such as PLZT. Since these high (ferro) dielectric films have a common property, they must be subjected to a high-temperature heat treatment of at least about 750 ° C. after film formation in order to obtain a high quality film with few crystal defects.
Even when these high (ferro) dielectric films are used, the same effects as described above can be obtained.

Next, as shown in FIG. 57, after a TiN film is deposited on the Ta ₂ O ₅ film 46 by using both the CVD method and the sputtering method, a photoresist film (not shown) is formed.
TiN film and Ta by dry etching using
By patterning the ₂ O ₅ film 46, an upper electrode 47 made of a TiN film, a capacitance insulating film made of a Ta ₂ O ₅ film 46, and a lower electrode 45 made of a polycrystalline silicon film (45A) are formed. The information storage capacitor C is completed. In addition, the memory cell selection M
A memory cell composed of the ISFET Qs and the information storage capacitor C connected in series thereto is completed. The upper electrode 47 of the information storage capacitor C may be formed of a conductive film other than the TiN film, for example, a W film.

Next, as shown in FIG. 58, after an interlayer insulating film 56 is formed over the information storage capacitor C, the interlayer insulating film 56 of the peripheral circuit is formed using a photoresist film (not shown) as a mask. By etching the silicon oxide film 50, the SOG film 39 and the silicon oxide film 39, the first
A through hole 54 is formed above the wiring 26 of the layer.
The interlayer insulating film 56 has, for example, a film thickness of 60 deposited by a CVD method.
It is composed of a silicon oxide film of about 0 nm.

Next, as shown in FIG. 59, after a plug 55 is formed inside the through hole 54, an interlayer insulating film 56 is formed.
Are formed on the second layer. The plug 55 is formed, for example, by depositing a Ti film on the interlayer insulating film 56 by a sputtering method, and further forming a Ti film on the Ti film by a CVD method.
After depositing the N film and the W film, these films are etched back and left inside the through-hole 54 to form the film. The second-layer wirings 52 and 53 are formed by sputtering a Ti film having a thickness of about 50 nm, an Al (aluminum) film having a thickness of about 500 nm, a Ti film having a thickness of about 50 nm, and a film thickness above the interlayer insulating film 56. After sequentially depositing TiN films of about 50 nm, these films are patterned and formed by dry etching using a photoresist film as a mask.

After forming the capacitive insulating film of the information storage capacitive element C, since there is no step involving a high-temperature heat treatment, the second-layer wirings 52 and 53 formed above the interlayer insulating film 56 are formed.
As a material of the above, a conductive material mainly composed of Al, which is inferior in heat resistance to a high melting point metal or a nitride thereof, but has a low electric resistance can be used. In addition, since there is no problem of film peeling due to the absence of a step involving a high-temperature heat treatment, the second-layer wirings 52 and 53 are formed on the interlayer insulating film 56 made of silicon oxide. A Ti film can be used as a barrier metal at a portion contacting the interface with the film 56.

Next, as shown in FIG. 60, after a second interlayer insulating film 63 is formed on the second layer wirings 52 and 53, the interlayer insulating film 63 on the information storage capacitor C is formed. , 5
6 is etched to form a through hole 60, and the interlayer insulating film 63 above the second layer wiring 53 of the peripheral circuit is etched to form a through hole 61. The second interlayer insulating film 63 is, for example, a silicon oxide film having a thickness of about 300 nm deposited by a CVD method and a film
It is composed of an SOG film having a thickness of about 00 nm and a silicon oxide film having a thickness of about 300 nm deposited thereon by a CVD method. The baking of the SOG film forming a part of the interlayer insulating film 63 is performed to prevent the second-layer wirings 52 and 53 mainly composed of Al and the capacitive insulating film of the information storage capacitive element C from deteriorating. At a temperature of about 400 ° C.

Thereafter, plugs 62 are formed inside the through holes 60 and 61, and then third-layer wirings 57, 58 and 59 are formed above the interlayer insulating film, whereby the above-mentioned FIGS. Is almost completed. Plug 62
Is, for example, the same conductive material (W film / T
iN film / Ti film), and the third-layer wirings 57, 5
Reference numerals 8 and 59 are made of, for example, the same conductive material (TiN film / Ti film / Al film / Ti film) as the second-layer wirings 52 and 53. Note that a dense insulating film having high water resistance (for example, plasma C) is formed over the third-layer wirings 57, 58, and 59.
Although a two-layer insulating film composed of a silicon oxide film and a silicon nitride film deposited by the VD method is deposited, the illustration is omitted.

(Embodiment 2) In this embodiment, the DRA
This is applied to the process of forming the lower electrode of the M information storage capacitor.

First, according to the process shown in FIGS. 6 to 50 of the first embodiment, SOG film 3 covering bit line BL
9, a silicon nitride film 44 is deposited, and then the silicon nitride film 44 of the peripheral circuit is removed by etching. Next, as shown in FIG. 61, a silicon oxide film 50 is deposited on the silicon nitride film 44 by a CVD method, and a photoresist film 76 is further spin-coated thereon. The pattern 76a is transferred.

Next, as shown in FIG. 62, the groove pattern 76a is formed by the ozone ashing described in the first embodiment.
After reducing the width by 40 nm, as shown in FIG.
Using the groove pattern 76a as a mask, the silicon oxide film 50 and the silicon nitride film 44 under the silicon oxide film 50 are dry-etched to form a groove 77 above the through hole 48. Since the concave groove 77 is formed by etching using a concave groove pattern 76a having a width reduced by 40 nm on one side and a total of 80 nm on both sides as a mask, the concave groove formed on the silicon oxide film 50 in the first embodiment is formed. The inner diameter is 80 nm larger than the groove 73.

Thereafter, as shown in FIG. 64, the polycrystalline silicon film deposited along the inner wall of the groove 77 is patterned to form the lower electrode of the information storage capacitor C according to the process described in the first embodiment. 78 is formed.

According to the above-described lower electrode forming method, the inner diameter of the groove 77 is 80 times larger than that of the groove 73 of the first embodiment.
Therefore, the surface area of the lower electrode 78 formed along the inner wall of the groove 77 is about 1.4 times larger than that of the lower electrode 45 formed by the method of the first embodiment. Thus, in the first embodiment, even when the thickness of the silicon oxide film 50 deposited with a large thickness (for example, about 1.3 μm) is reduced to about 0.9 μm, the same amount of accumulated charge can be secured. It becomes possible. That is, the groove 7
Since the same amount of accumulated charge can be secured even if the depth of the groove 7 is reduced, the processing time for forming the concave groove 77 can be shortened and the processing yield can be improved.

Further, as the thickness of the silicon oxide film 50 is reduced, the second-layer wiring formed on the silicon oxide film 50 in the peripheral circuit region and the first-layer wiring thereunder are reduced. The formation of connecting through holes is also facilitated. Further, at this time, by forming fine irregularities on the surface of the lower electrode 78 to increase the surface area thereof, the thickness of the silicon oxide film 50 can be reduced and the concave groove 77 can be formed more shallow.

When the narrow groove pattern 76a as described above is to be formed by only one lithography, it has been confirmed that the groove pattern collapses due to the wet processing when developing the groove pattern 76a. And a narrow groove pattern 76 by a method other than ozone ashing.
It is difficult to form a.

(Embodiment 3) In this embodiment, the DRA
This is applied to a gate processing process of an LSI in which M and logic are mixed, and the left part of FIG.
Area on the right side is a logic L
The semiconductor substrate 1 in a region where an SI is formed is shown.

First, as shown in FIG.
A gate electrode material and a silicon nitride film 83 are deposited on the gate oxide film 7 formed on each surface of the n-type well 4 and the photoresist film 8 on the gate oxide film 7.
After spin coating 4, the gate pattern 84 a of the logic LSI is transferred to the photoresist film 84. At this time, the gate pattern of the memory cell is not transferred to the area where the memory cell of the DRAM is formed. The gate electrode material is composed of a laminated film of a polycrystalline silicon film 80 doped with an n-type impurity such as P (phosphorus), a WN film 81 and a W film 82.

Next, as shown in FIG. 67, the gate pattern 84 is formed by the ozone ashing described in the first embodiment.
After reducing the width of the silicon nitride film 8 using the gate pattern 84a as a mask, as shown in FIG.
The gate electrode 85 of the logic LSI is formed by dry-etching the gate electrode material 3 and the gate electrode material thereunder. The width (gate length) of the gate electrode 85 is smaller than the minimum processing size, and the width of the gate electrode 85 is smaller than that of the adjacent gate electrode 8.
5 is larger than the above width.

Next, after removing the photoresist film 84, as shown in FIG. 69, the gate pattern 86a of the DRAM memory cell is transferred to a photoresist film 86 which has been newly applied by spin coating. 86
By dry-etching the silicon nitride film 83 and the gate electrode material under the silicon nitride film 83 using a as a mask, a gate electrode 87 (word line WL) of a DRAM memory cell having a width (gate length) and space almost equal to each other is formed. .

As described above, according to the present embodiment, the width of the gate pattern 84a can be narrowed with high accuracy by ozone ashing, so that the width (gate length) can be reduced like the gate electrode 85 of the logic LSI. However, gate processing that is smaller than the minimum processing size and whose space between the adjacent gate electrode 85 is larger than the width can be accurately performed.

As described above, the invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0150]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, the parasitic capacitance formed between adjacent bit lines can be reduced by making the width of the bit lines smaller than the minimum processing size determined by the resolution limit of photolithography. Therefore, even when the memory cell size is reduced, the signal voltage for reading out the charges (information) stored in the information storage capacitor can be increased.

Further, since the space of the bit line can be widened, a sufficient opening margin of the through hole formed in the space region of the bit line can be secured, and the size of the memory cell can be reduced. Even if
Short circuit between the bit line and the plug in the through hole can be reliably prevented.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to a first embodiment of the present invention is formed.

FIG. 2 is an equivalent circuit diagram of the DRAM according to the first embodiment of the present invention;

FIG. 3 is a cross-sectional view of a principal part of the semiconductor substrate showing a part of each of a memory array and peripheral circuits of the DRAM according to the first embodiment of the present invention;

FIG. 4 is a schematic plan view of a semiconductor substrate showing a part of a memory array of the DRAM according to the first embodiment of the present invention;

FIG. 5 is a cross-sectional view of a main part of a semiconductor substrate showing a part of the memory array of the DRAM according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 7 is an essential part plan view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

9 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention; FIG.

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 18 is a fragmentary plan view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 34 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 36 is a graph showing a relationship between a substrate temperature and an ashing speed.

FIG. 37 is a graph showing a relationship between an ashing time and a shift amount of a resist dimension when a substrate temperature is kept constant.

FIG. 38 is a graph showing a distribution of an ashing amount in a wafer surface.

FIG. 39 is a graph showing variations in resist pattern dimensions before and after ozone ashing.

FIG. 40 is a graph showing variations in resist pattern dimensions before and after oxygen plasma etching.

FIG. 41 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 42 is an essential part plan view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 43 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 44 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 45 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 46 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 47 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 48 is an essential part plan view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 49 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 50 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 51 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 52 is an essential part cross sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 53 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 54 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 55 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 56 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 57 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 58 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 59 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 60 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the first embodiment of the present invention;

FIG. 61 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 62 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 63 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 64 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to the second embodiment of the present invention;

FIG. 65 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a DRAM-logic embedded LSI according to a third embodiment of the present invention;

FIG. 66 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a DRAM-logic embedded LSI according to a third embodiment of the present invention;

FIG. 67 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a DRAM-logic embedded LSI according to a third embodiment of the present invention;

FIG. 68 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a DRAM-logic embedded LSI according to a third embodiment of the present invention;

FIG. 69 is a cross-sectional view of a principal part of a semiconductor substrate, illustrating a method for manufacturing a DRAM-logic hybrid LSI according to the third embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 p-type well 3 n-type semiconductor region 4 n-type well 5 silicon oxide film 6 element isolation trench 7 gate oxide film 8A to 8C gate electrode 9 n-type semiconductor region (source, drain) 9a n ^- type semiconductor region ( (Source, drain) 10 n ⁺ type semiconductor region (source, drain) 11 p ⁺ type semiconductor region (source, drain) 12 silicon nitride film 13 silicon nitride film 13 s sidewall spacer 14 n ⁻ type semiconductor region 15 p ⁻ type semiconductor region 16 SOG film 17 Silicon oxide film 18 Silicon oxide film 19 Contact hole 20 Contact hole 21 Plug 22 Through hole 23-26 Wiring 27 Photoresist film 28 Silicon oxide film 30-34 Contact hole 35 Plug 36 Ti film 37 TiSi ₂ layer 38 Oxidation Silicon film 39 S G film 40 TiN film 41 W film 42 W film 43 a photoresist film 43a bit line pattern 43b wiring patterns 44 silicon film 45 lower electrode 45A polycrystalline silicon nitride film 46 Ta ₂ O ₅ film 47 upper electrode 48 through hole 49 plug 50 oxide Silicon film 51 Silicon oxide film 52, 53 Wiring 54 Through hole 55 Plug 56 Interlayer insulating film 57, 58, 59 Wiring 60 Through hole 61 Through hole 62 Plug 63 Second interlayer insulating film 70 Polycrystalline silicon film 71 Through hole 72 Side wall Spacer 73 Groove 74 SOG film 75 Photoresist film 76 Photoresist film 76a Groove pattern 77 Groove 78 Lower electrode 80 Polycrystalline silicon film 81 WN film 82 W film 83 Silicon nitride film 84 Photoresist film 84a Ge Pattern 85 gate electrode 86 photoresist film 86a gate pattern 87 gate electrode BL bit line C information storage capacitor MARY memory array MC memory cell Qn n-channel MISFET Qn Qp p-channel MISFET Qp Qs MISFET SA for memory cell selection Sense amplifier WD Word driver WL Word line

Continued on the front page. (72) Inventor Keizo Kawakita 3-16, Shinmachi, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Satoru Satoru Yamada 3 shares, 6-16, Shinmachi, Ome-shi, Tokyo (72) Inventor Toshihiro Sekiguchi 3-16-1, Shinmachi, Ome-shi, Tokyo 3 Stock Company In-house Hitachi, Ltd. Device Development Center (72) Inventor ▲ yoshi ▼ ▲ taka ▼ Ome-shi, Tokyo 3-16, Shinmachi 3 Device Development Center, Hitachi, Ltd. (72) Inventor Takuya Fukuda 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Semiconductor Device Division, Hitachi, Ltd. (72) Naofumi Tokunaga, Inventor 6-16-16 Shinmachi, Ome-shi, Tokyo, Hitachi, Ltd. Device Development Center Co., Ltd. (72) Inventor Isamu Isano 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Co., Ltd. Hitachi, Ltd. Device Development Center (72) Inventor Yoshida 6-16-16 Shinmachi, Ome-shi, Tokyo, within the Device Development Center, Hitachi, Ltd. (72) Inventor Tsuyoshi Tamaru 3-16-16 Shinmachi, Ome-shi, Tokyo, Japan 3 The inventor at the Device Development Center, Hitachi, Ltd. (72) Inventor Hidekazu Goshima 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo In the semiconductor division of Hitachi, Ltd. (72) Inventor Takahiro Kumauchi 3--16, Shinmachi, Shinmachi, Ome-shi, Tokyo In the device development center of Hitachi, Ltd. (72) Inventor Tadafumi Umezawa 3-16, Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Haruhito Mitani 6-16-16, Shinmachi, Ome-shi, Tokyo 3 Hitachi, Ltd. Inside the Device Development Center

Claims (15)

[Claims] 1. A memory cell selecting MISFET having a gate electrode formed integrally with a word line is formed in a first region on a main surface of a semiconductor substrate, and a first insulation covering the memory cell selecting MISFET is formed. A bit line electrically connected to one of a source and a drain of the memory cell selection MISFET is formed on the film, and the memory cell is formed on a second insulating film formed on the bit line. A semiconductor integrated circuit device having a memory cell in which an information storage capacitor electrically connected to the other of a source and a drain of a selection MISFET is formed, wherein the width of the bit line is limited by a resolution limit of photolithography. A semiconductor integrated circuit device having a size smaller than a minimum size determined by the following formula: 2. The semiconductor integrated circuit device according to claim 1, wherein the other of the source and the drain of the memory cell selecting MISFET and the information storage capacitor are formed in a space region of the bit line adjacent to each other. A diameter of a through hole electrically connecting the semiconductor integrated circuit is smaller than a minimum dimension determined by a resolution limit of photolithography. 3. The semiconductor integrated circuit device according to claim 1, wherein a width of said bit line is about one-fourth of a pitch of a gate electrode integrally formed with said word line. Semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein the conductive film forming the bit line is a single-layer film of a refractory metal or a laminated film of a refractory metal and a nitride thereof. A semiconductor integrated circuit device characterized by the above-mentioned. 5. The semiconductor integrated circuit device according to claim 1, wherein the conductive film forming the bit line is a tungsten single-layer film. 6. The semiconductor integrated circuit device according to claim 1, wherein at least a part of a conductive film forming a gate electrode of the memory cell selecting MISFET is formed of a metal film. Semiconductor integrated circuit device. 7. The semiconductor integrated circuit device according to claim 1, wherein the capacitive insulating film of the information storage capacitive element includes a high dielectric film at least in a part thereof. Circuit device. 8. The semiconductor integrated circuit device according to claim 7, wherein said high dielectric film is a tantalum oxide film deposited by a CVD method. 9. A memory cell selecting MISFET having a gate electrode integrally formed with a word line is formed in a first region on a main surface of a semiconductor substrate, and a first insulating material covering the memory cell selecting MISFET. A bit line electrically connected to one of a source and a drain of the memory cell selection MISFET is formed on the film, and the memory cell is formed on a second insulating film formed on the bit line. A method for manufacturing a semiconductor integrated circuit device having a memory cell in which an information storage capacitor electrically connected to the other of the source and the drain of the selection MISFET is formed,
(A) forming a memory cell selecting MISFET constituting a memory cell on a main surface of a semiconductor substrate, and then depositing a first insulating film on the memory cell selecting MISFET; (b) the first insulating film Forming a first photoresist film having a pattern of bit lines arranged at a first width and a first interval on the first conductive film after depositing a first conductive film on the film; (C) ashing the first photoresist film to form a second width smaller than the first width and a second width larger than the first interval.
Forming a second photoresist film having bit line patterns arranged at intervals of (d), and (d) etching the first conductive film using the second photoresist film as a mask. A method for manufacturing a semiconductor integrated circuit device. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the first step is performed using a gas containing ozone.
A method of manufacturing a semiconductor integrated circuit device, comprising: ashing a photoresist film. 11. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein after the step (d), (e) depositing a second insulating film on the bit line, and then depositing the second insulating film on the bit line. Forming a first etching stopper film having an etching selectivity different from that of the second insulating film over the insulating film; (f)
Using the first etching stopper film as a mask, the second insulating film above the space region of the bit line adjacent to each other is etched to form a first through hole whose bottom is located above the bit line. (G) forming a second etching stopper film over the second insulating film including the inside of the first through hole, and then etching the second etching stopper film to form the first through hole; Forming a sidewall spacer on the side wall of the hole; (h) etching the second insulating film at the bottom of the first through hole using the first etching stopper film and the sidewall spacer as a mask; In the space area of the bit line adjacent to each other, the minimum determined by the resolution limit of photolithography Manufacturing a semiconductor integrated circuit device, further comprising: forming a second through-hole having a diameter equal to or less than the method, and (i) forming an information storage capacitive element above the second through-hole. Method. 12. The method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein when forming the bit line by etching the first conductive film, a second region on a main surface of the semiconductor substrate is formed. A method of manufacturing a semiconductor integrated circuit device, wherein a first layer wiring of a peripheral circuit is simultaneously formed by etching the first conductive film. 13. The method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein after etching the first conductive film, the second photoresist film is removed by ashing using a gas containing ozone. A method for manufacturing a semiconductor integrated circuit device. 14. A memory cell selecting MI having a gate electrode formed integrally with a word line on a main surface of a semiconductor substrate.
An SFET is formed, and the memory cell selecting MISFE is formed.
The memory cell selecting M is formed on the first insulating film covering T.
A method of manufacturing a semiconductor integrated circuit device having a memory cell in which an information storage capacitor electrically connected to one of a source and a drain of an ISFET is formed, wherein (a) a memory cell is provided on a main surface of a semiconductor substrate After the formation of the memory cell selecting MISFET constituting the
Depositing a first insulating film on top of the ISFET, (b)
After forming a photoresist film having an opening pattern on one of the source and the drain of the memory cell selecting MISFET on the first insulating film, the front photoresist film is formed by ashing using a gas containing ozone. (C) etching the first insulating film using the photoresist film as a mask, thereby etching the first insulating film.
Forming a groove corresponding to the opening pattern in the insulating film; and (d) patterning a first conductive film formed along an inner wall of the groove to form a lower electrode of the information storage capacitor. Forming a semiconductor integrated circuit device. 15. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: (a) depositing a first conductive film on a main surface of a semiconductor substrate and then forming a first conductive film on the first conductive film; Forming a first photoresist film; (b) exposing and developing the first photoresist film to form a first photoresist film in a first region on a main surface of the semiconductor substrate; Forming one gate electrode pattern;
(C) The first method is performed by ashing using a gas containing ozone.
Reducing the width of the first gate electrode pattern by etching the photoresist film of (d), (d).
By etching the first conductive film using the first photoresist film as a mask, the width of the first region is smaller than the minimum processing size, and the space between the first region and the adjacent first gate electrode is reduced. Forming a first gate electrode larger than the width, (e) after removing the first photoresist film, a second gate electrode pattern having a second gate electrode pattern in a second region on a main surface of the semiconductor substrate; Forming a photoresist film, and (f) etching the first conductive film using the second photoresist film as a mask, thereby forming a second gate electrode having a width and a space substantially equal to each other in the second region. Forming a.