JP2001332707A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique capable of forming a capacitance insulating film having relative permittivity higher than that of a tantalum oxide film single layer. SOLUTION: The capacitance insulating film 28 is constituted by using a lamination film wherein a first tantalum oxide film 28a, a first titanium oxide film 28b, a second tantalum oxide film 28c and a second titanium oxide film 28d are laminated in order from a lower layer. By laminating the titanium oxide films whose relative permittivities are 100-200 and the tantalum oxide films whose relative permittivities are 20-50, relative permittivity higher than that of a tantalum oxide film single layer can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technology thereof, and more particularly to a technology effective when applied to a semiconductor integrated circuit device having a capacitance element.

[0002]

2. Description of the Related Art A DRAM (Dynamic Random Access Memory) is a semiconductor memory representing a large capacity memory. The memory capacity of the DRAM tends to increase, and the area occupied by the memory cell has also been reduced in view of improving the degree of integration of the memory cell of the DRAM.

However, the storage capacity of the information storage capacitor (capacitor) in a DRAM memory cell is DRA.
It is known that a certain amount is required irrespective of the generation from the viewpoint of considering the operation margin of M, a soft error, and the like, and it cannot be generally reduced in proportion.

Therefore, a capacitor structure capable of securing a required storage capacity within a limited small occupation area is being developed. Such a capacitor structure includes a three-dimensional storage electrode (lower electrode). A three-dimensional capacitor structure in which a plate electrode (upper electrode) is formed via a capacitance insulating film is employed.

In a three-dimensional capacitor, a capacitor electrode is a memory cell selection MISFET (Metal Insulator Semiconductor).
In general, a structure arranged in an upper layer of a ctor field effect transistor) is used. As a three-dimensional capacitor structure, for example, a technology described in JP-A-7-122654,
That is, a capacitor over bit line in which a capacitor is arranged above a bit line.
ne) The structure is known.

Further, in order to secure a storage capacitor, the storage electrode is made of a metal material, for example, ruthenium (Ru), and the capacitor insulating film is an insulating material having a higher relative dielectric constant than a silicon oxide (SiO ₂ ) film. MIM (Metal Insula) formed by a film, for example, a tantalum oxide (Ta ₂ O ₅ ) film
tor Metal) structures are being considered. The MIM capacitor technology employing a tantalum oxide film is described in, for example, “Applied Physics,” Vol.
Issue, November 10, 1997, P1210-P12
14.

[0007]

According to studies made by the present inventors, a tantalum oxide film having a relative dielectric constant of about 20 to 50 has achieved a thickness of about 1.6 μm in terms of SiO ₂ . Until the beginning of the gigabit generation, it is considered to be applicable as a capacitive insulating film. However, in the generations after 4 gigabits, a capacitance insulating film having a SiO ₂ equivalent film thickness of less than 1 nm is required, and it is presumed that it is difficult to achieve a SiO ₂ equivalent film thickness of less than 1 nm with a tantalum oxide film. .

In view of this, a perovskite-based high dielectric constant film having a higher relative dielectric constant than a tantalum oxide film, for example, BST (Ba _x Sr _{1 -x} TiO ₃ ) has been developed. However, BST which is a multi-component mixed crystal
Since the relative permittivity and the leak current characteristics change depending on the composition, CVD (Chemical Vaa) is excellent in composition controllability and reproducibility.
por Deposition) technology is required. Further, in BST, a decrease in relative dielectric constant and an increase in leak current are observed due to thinning, but in order to reduce the equivalent SiO ₂ film thickness, it is necessary to suppress a decrease in relative dielectric constant and an increase in leak current. is there. Further, since the BST film is formed in an oxidizing atmosphere, it is important to develop a storage electrode structure having excellent oxidation resistance, and many problems remain for practical use.

An object of the present invention is to provide a technique capable of forming a capacitor insulating film having a higher dielectric constant than a single layer of a tantalum oxide film.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) a semiconductor integrated circuit device of the present invention, a titanium oxide film (TiO) and a laminated film of a tantalum oxide film or a titanium tantalum film _{(Ta x Ti 2-x O} 5) is constituted by an insulating film, It has. (2) A semiconductor integrated circuit device according to the present invention has an insulating film composed of a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film, and has a total thickness of about 50 nm. The following is assumed. (3) The semiconductor integrated circuit device of the present invention has a laminated film of a titanium oxide film and a tantalum oxide film, or an insulating film formed by stacking a plurality of tantalum titanate films. (4) The semiconductor integrated circuit device of the present invention has an insulating film composed of a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film, wherein the insulating film is a ruthenium film, a titanium nitride film. It is formed on an electrode composed of a film, a silicon film, or a silicon film on which projections made of silicon grains are formed. (5) A semiconductor integrated circuit device according to the present invention includes a laminated film of a titanium oxide film and a tantalum oxide film, or an insulating film formed of a tantalum titanate film, wherein the insulating film is formed of silicon. It is formed over the silicon oxynitride film. (6) The semiconductor integrated circuit device of the present invention has an insulating film composed of a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film, wherein the insulating film is a ruthenium film, a titanium nitride. A film, a silicon film, or an electrode formed of a silicon film on which a projection made of silicon grains is formed, wherein the insulating film constitutes a capacitive insulating film of a capacitive element . (7) A semiconductor integrated circuit device according to the present invention includes a laminated film of a titanium oxide film and a tantalum oxide film, or an insulating film formed of a tantalum titanate film, wherein the insulating film is formed of silicon. The insulating film and the silicon oxynitride film are formed thereover via a silicon oxynitride film, and constitute a gate insulating film of a MIS transistor. (8) In the method of manufacturing a semiconductor integrated circuit device of the present invention, when forming a laminated film of a titanium oxide film and a tantalum oxide film, a CVD method using a titanium-containing organic material or a titanium halide as a raw material is used. Depositing a titanium oxide film in an oxidizing atmosphere under reduced pressure, and then subjecting the titanium oxide film to a crystallization process;
Depositing a tantalum oxide film in an oxidizing atmosphere under a reduced pressure using method D, and then subjecting the tantalum oxide film to a crystallization process. (9) The method of manufacturing a semiconductor integrated circuit device according to the present invention is a method for manufacturing a semiconductor integrated circuit device by using a CVD method using a tantalum-containing organic material and a titanium-containing organic material or a titanium halide as raw materials in an oxidizing atmosphere under reduced pressure. After the tantalum film is deposited, a step of subjecting the tantalum titanate film to a crystallization process is provided.

According to the above-mentioned means, the capacitance insulating film constituting the information storage capacitance element is made up of a titanium oxide film having a relative dielectric constant of about 100 to 200 and a tantalum oxide film having a relative dielectric constant of about 20 to 50. With this structure, a capacitor insulating film having a higher dielectric constant than a single layer of a tantalum oxide film can be obtained. In addition, by forming a capacitor insulating film with a tantalum titanate film, titanium or titanium oxide is formed in the tantalum oxide film, so that a capacitor insulating film having a higher dielectric constant than a single layer of the tantalum oxide film can be obtained. it can.

Further, by using a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film as a gate insulating film of a MIS transistor, the gate insulating film can be reduced in SiO ₂ equivalent thickness and leak current can be reduced. Can be reduced.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for describing the embodiments, parts having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 shows Embodiment 1 of the present invention.
FIG. 2 is a cross-sectional view of a main part of a semiconductor substrate showing a DRAM as a first embodiment.
In all the drawings for describing the embodiments, components having the same function are denoted by the same reference numerals, and the repeated description thereof will be omitted. In FIG. 1, an area A shows a part of a memory array, and an area B shows a part of a peripheral circuit.

On a main surface of a semiconductor substrate 1 made of p-type single crystal silicon, a p-type well 2 of a memory array, a p-type well 3 of a peripheral circuit, and an n-type well 4 are formed.
Further, an n-type deep well 5 is formed so as to surround the p-type well 2. Note that a threshold voltage adjustment layer may be formed in each well.

An isolation region 6 is formed on the main surface of each well. The isolation region 6 is made of a silicon oxide film, and is formed in a shallow groove 7 formed on the main surface of the semiconductor substrate 1 via a thermally oxidized silicon oxide film 8.

On the main surface of the p-type well 2, a MISFET Qs for selecting a memory cell of a DRAM is formed. Also,
The main surfaces of the p-type well 3 and the n-type well 4 are respectively provided with an n-channel MISFET Qn and a p-channel MISFET Q
p is formed.

The memory cell selection MISFET Qs is p
A gate electrode 10 is formed on a main surface of the p-type well 2 via a gate insulating film 9, and an impurity semiconductor region 11 is formed on a main surface of the p-type well 2 on both sides of the gate electrode 10. Gate insulating film 9 is made of, for example, a silicon oxide film having a thickness of 7 to 8 nm and formed by thermal oxidation.
The gate electrode 10 is made of, for example, a polycrystalline silicon film 10a having a thickness of 70 nm and a titanium nitride (T
It can be a laminated film of an iN) film 10b and a 100 nm-thick tungsten (W) film 10c. Further, an n-type impurity, for example, arsenic (As) or phosphorus (P) is introduced into the impurity semiconductor region 11.

A cap insulating film 12 made of a silicon nitride film is formed on the gate electrode 10 of the memory cell selecting MISFET Qs, and the cap insulating film 12 is further covered with a silicon nitride film 13. The silicon nitride film 13 is also formed on the side wall of the gate electrode 10 and is used for a self-alignment process when forming a connection hole described later. The gate electrode 10 of the memory cell selecting MISFET Qs functions as a DRAM word line, and a word line WL is formed on the upper surface of the isolation region 6.

On the other hand, the n-channel MISFET Qn
A gate electrode 10 formed on the main surface of the p-type well 3 via the gate insulating film 9 and an impurity semiconductor region 1 formed on the main surface of the p-type well 3 on both sides of the gate electrode 10
And 4. The gate insulating film 9 and the gate electrode 10 are the same as described above. The impurity semiconductor region 14 includes a low-concentration n ^{− -type} semiconductor region 14a and a high-concentration n ^{+ -type} semiconductor region 14b.
ain) to form a structure.

Similarly, the p-channel MISFET Qp is
A gate electrode 10 formed on the main surface of the n-type well 4 and formed via the gate insulating film 9 and an impurity semiconductor region 15 formed on the main surface of the n-type well 4 on both sides of the gate electrode 10 Be composed. The gate insulating film 9 and the gate electrode 10 are the same as described above. The impurity semiconductor region 15 includes a low-concentration p ^{− -type} semiconductor region 15a and a high-concentration p ^{+ -type} semiconductor region 15b, forming a so-called LDD structure.

A cap insulating film 12 made of a silicon nitride film is formed on the gate electrode 10 of the n-channel MISFET Qn and the p-channel MISFET Qp, and a sidewall spacer 16 made of, for example, a silicon nitride film is formed on the side surface. .

Memory cell selecting MISFET Qs, n-channel MISFET Qn and p-channel MISFET
Qp is covered with an interlayer insulating film 17. Interlayer insulating film 1
7 is a SOG (Spin On Glass) film 17a, T
A silicon oxide film (hereinafter referred to as TE) formed by plasma CVD using EOS (tetraethoxysilane) as a source gas.
OS oxide film) is a CMP (Chemical Mechanical Po
TEOS oxide film 17 planarized by the lishing) method
b, TEOS oxide film 17c and silicon oxide film 17d
Laminated film.

On the interlayer insulating film 17, a bit line BL and a first layer wiring 18 (M1) are formed. Bit line B
L and the first layer wiring 18 (M1) can be, for example, a laminated film of a titanium (Ti) film 18a, a titanium nitride film 18b, and a tungsten film 18c. Thereby, the bit line BL and the first layer wiring 18 (M1)
Can be reduced to improve the performance of the DRAM. Further, the bit line BL and the first layer wiring 18 (M1) are formed simultaneously as described later. Thereby, the process can be simplified.

The bit line BL is connected via a plug 19 to the impurity semiconductor region 11 shared by a pair of memory cell selecting MISFETs Qs. Plug 19 can be, for example, a polycrystalline silicon film into which an n-type impurity has been introduced. Further, a titanium silicide (TiSi ₂ ) film 20 is formed at a connection portion between the plug 19 and the bit line BL. Thereby, the connection resistance between the bit line BL and the plug 19 can be reduced, and the connection reliability can be improved.

The first layer wiring 18 (M1) is connected to the impurity semiconductor region 14 of the n-channel MISFET Qn and the impurity semiconductor region 15 of the p-channel MISFET Qp via the connection hole 21. Also, the first layer wiring 18 (M1)
A titanium silicide film 20 is formed at the connection between the semiconductor region and the impurity semiconductor regions 14 and 15. Thereby, the connection resistance between the first layer wiring 18 (M1) and the impurity semiconductor regions 14 and 15 can be reduced, and the connection reliability can be improved.

The bit line BL and the first layer wiring 18 (M
1) is covered with a cap insulating film 22a made of a silicon nitride film and a sidewall spacer 22b, and further covered with an interlayer insulating film 23. The interlayer insulating film 23 is made of, for example, an SOG film 23a, a TE planarized by a CMP method.
It can be a stacked film of the OS oxide film 23b and the TEOS oxide film 23c.

An information storage capacitor C is formed in the memory array above the interlayer insulating film 23. Further, an insulating film 24 is formed on the interlayer insulating film 23 of the peripheral circuit. The insulating film 24 can be, for example, a laminated film of a silicon nitride film 24a and a silicon oxide film 24b.

In the impurity semiconductor region 11 opposite to the impurity semiconductor region 11 connected to the bit line BL via the plug 19 of the memory cell selecting MISFET Qs, the plug 1
A plug 25 made of the same layer as that of the plug 9 is connected. Further, an information storage capacitor C is formed above the plug 25 via the plug 26, and the information storage capacitor C is connected to the storage electrode 27 connected to the plug 26.
, A capacitance insulating film 28, and a plate electrode 29.

The storage electrode 27 is formed of an amorphous silicon film or a metal film such as a ruthenium film or a titanium nitride film. For the plate electrode 29, a metal film such as a ruthenium film, a titanium nitride film or a tungsten film, or a metal compound such as a tungsten nitride (WN) film can be used.

The capacitor insulating film 28 includes a first tantalum oxide film,
A first titanium oxide film, a second tantalum oxide film, and a second titanium oxide film are each formed of a laminated film sequentially deposited from a lower layer,
The total thickness of this laminated film is about 10 to 50 nm.
Titanium oxide film having a relative dielectric constant of 100 to 200 and 20
By laminating a tantalum oxide film having a relative dielectric constant of 50 to 50, a higher relative dielectric constant than a single layer of a tantalum oxide film can be obtained.

A second layer wiring 31 (M2) is formed above the information storage capacitor C via an insulating film 30 made of, for example, a TEOS oxide film. Second layer wiring 31 (M
2) includes, for example, a titanium film 31a and aluminum (A
1) It can be a laminated film of the film 31b and the titanium nitride film 31c.

The second layer wiring 31 (M2) is connected to the first layer wiring 18 (M1) via a plug 32. Plug 3
2 can be a laminated film of, for example, an adhesive layer 32a composed of a laminated film of a titanium film and a titanium nitride film and a tungsten film 32b formed by a CVD method.

The second layer wiring 31 (M 2) is
3 and the second-layer wiring 31
A third layer wiring 34 (M3) similar to (M2) is formed. The interlayer insulating film 33 is, for example, a TEOS oxide film 33
a, a laminated film of the SOG film 33b and the TEOS oxide film 33c. Further, the third layer wiring 34 (M3)
And the second layer wiring 31 (M2) are connected by a plug 35 similar to the plug 32.

Next, an example of a method of manufacturing the DRAM according to the first embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 2, a semiconductor substrate 1 made of a p-type silicon single crystal having a specific resistance of about 10 Ωcm.
And a shallow groove 7 is formed in the main surface of the semiconductor substrate 1. Thereafter, thermal oxidation is performed on the semiconductor substrate 1 to form a silicon oxide film 8. Further, a silicon oxide film is deposited and polished by the CMP method to leave the silicon oxide film only in the shallow groove 7, thereby forming the isolation region 6.

Next, an n-type impurity, for example, phosphorus is ion-implanted into the semiconductor substrate 1 in a region where a memory cell is formed (region A: memory array) to form a deep well 5, and a memory array and a peripheral circuit (region B) ) (A region where the n-channel MISFET Qn is formed)
For example, boron (B) is ion-implanted to form p-type wells 2 and 3, and another part of the peripheral circuit (p-channel MI
An n-type well 4 is formed by ion-implanting an n-type impurity, for example, phosphorus into a region where the SFET Qp is to be formed. Subsequent to this ion implantation, an impurity for adjusting the threshold voltage of the MISFET, for example, boron fluoride (BF ₂ ) is ion-implanted into the p-type wells 2 and 3 and the n-type well 4. The deep well 5 is formed to prevent noise from entering the p-type well 2 of the memory array through the semiconductor substrate 1 from an input / output circuit or the like.

Next, as shown in FIG.
After cleaning the surfaces of the n-type well 3 and the n-type well 4 using a hydrofluoric acid (HF) -based solution, the semiconductor substrate 1 is wet-oxidized at about 850 ° C.
A clean gate insulating film 9 having a thickness of about 7 nm is formed on each surface of the substrate.

Next, gate electrodes 10A, 10B and 10C are formed on the gate insulating film 9. Gate electrode 10A
Constitutes a part of the memory cell selection MISFET Qs, and functions as a word line WL in a region other than the active region.

For the gate electrode 10A (word line WL) and the gate electrodes 10B and 10C, a polycrystalline silicon film 10a having a thickness of about 70 nm doped with an n-type impurity such as phosphorus is deposited on the semiconductor substrate 1 by the CVD method. Then, a titanium nitride film 10b having a thickness of about 50 nm and a tungsten film 10c having a thickness of about 100 nm are deposited thereon by sputtering. Further, a cap insulating film 12 having a thickness of about 150 nm, for example, a silicon nitride film is deposited thereon by a CVD method, and then these films are patterned using a photoresist film as a mask. The titanium nitride film 10b functions as a barrier layer that prevents the tungsten film 10c and the polycrystalline silicon film 10a from reacting during high-temperature heat treatment to form a high-resistance silicide layer at the interface between the two. As the barrier layer, a tungsten nitride film or the like can be used in addition to the titanium hydride film.

Next, after removing the photoresist film, the semiconductor substrate 1 is etched using an etching solution such as hydrofluoric acid.
Dry etching residues and photoresist residues remaining on the surface of the substrate are removed. Next, the semiconductor substrate 1
A degree of oxidation treatment is performed.

Next, p-type impurity into the n-type well 4, for example boron is ion-implanted into both sides of the n-type well 4 of the gate electrode 10C p ^- forms a type semiconductor region 15a.
Further, n-type impurities in p-type well 2 and 3, for example, phosphorus is ion-implanted n to p type well 3 on both sides of the gate electrode 10B by ^- a type semiconductor region 14a is formed, the gate electrode 1
An impurity semiconductor region 11 (source, drain) is formed in the p-type well 2 on both sides of 0A. As a result, the memory cell selecting MISFET Qs is formed in the memory array.

Next, as shown in FIG. 4, a silicon nitride film 13 having a thickness of about 50 nm is deposited on the semiconductor substrate 1 by the CVD method, and then the silicon nitride film 13 of the memory array is covered with a photoresist film. By anisotropically etching the silicon nitride film 13 of the circuit, the gate electrode 10B,
A side wall spacer 16 is formed on the side wall of 10C. This etching uses an etching gas that increases the etching rate of the silicon nitride film 13 with respect to the silicon oxide film in order to minimize the amount of the silicon oxide film buried in the gate insulating film 9 and the isolation region 6. Do it. Further, in order to minimize the shaving amount of the cap insulating film 12 composed of the silicon nitride film on the gate electrodes 10B and 10C, the over-etching amount is kept to a necessary minimum.

Next, after the photoresist film is removed, a p-type impurity, for example, boron is ion-implanted into the n-type well 4 of the peripheral circuit to form a p-channel MISFET Qp.
The p ⁺ type semiconductor region 15b (source, drain) is formed, n-type impurities in p-type well 3 in the peripheral circuit, for example arsenic is ion-implanted n-channel MISFETQn n ⁺ -type semiconductor regions 14b (source, drain) To form As a result, the p-channel MISFET Q
P and n channel MISFETs Qn are formed.

Next, as shown in FIG. 5, an SOG film 17a having a thickness of about 300 nm is spin-coated on the semiconductor substrate 1, and then the semiconductor substrate 1 is heat-treated at 800.degree.
The OG film 17a is sintered (burned).

Next, a film thickness of 600 is formed on the SOG film 17a.
After depositing a TEOS oxide film 17b of about nm,
The EOS oxide film 17b is polished by the CMP method to planarize the surface. The TEOS oxide film 17b is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane as a source gas.

Next, a TEOS oxide film 17c having a thickness of about 100 nm is deposited on the TEOS oxide film 17b. The TEOS oxide film 17c is deposited in order to repair fine scratches on the surface of the TEOS oxide film 17b generated when the surface is polished by the CMP method. The TEOS oxide film 17c is deposited by, for example, a plasma CVD method using ozone and tetraethoxysilane as a source gas. TEOS oxide film 1
7b, a PSG is used instead of the TEOS oxide film 17c.
(Phospho Silicate Glass) film may be deposited.

Next, a photoresist film 36 is formed on the TEOS oxide film 17c, and this photoresist film 36 is formed.
For memory cell selection by dry etching using
TEO in the upper layer of the impurity semiconductor region 11 of the ISFET Qs
The S oxide films 17c and 17b and the SOG film 17a are removed.

The above etching is performed on the silicon nitride film 13 with the TEOS oxide films 17c, 17b and SO
The etching is performed under such a condition that the etching rate of the G film 17a is increased so that the silicon nitride film 13 covering the impurity semiconductor region 11 and the upper portion of the isolation region 6 is not completely removed.

Subsequently, the memory cell selection MISF is performed by dry etching using the photoresist film 36 as a mask.
By removing the silicon nitride film 13 and the gate insulating film 9 above the impurity semiconductor region 11 of ETQs, a connection hole 37 is formed on one upper portion of the impurity semiconductor region 11,
A connection hole 38 is formed on the other upper part.

Next, after removing the photoresist film 36, plugs 19 and 25 are formed inside the connection holes 37 and 38, respectively, as shown in FIG. Plug 19, 25
A polycrystalline silicon film doped with an n-type impurity (for example, phosphorus) is deposited on the TEOS oxide film 17c by a CVD method, and then the polycrystalline silicon film is polished by a CMP method to form the inside of the connection holes 37 and 38. To form.

Next, as shown in FIG. 7, a silicon oxide film 1 having a thickness of about 200 nm is formed on the TEOS oxide film 17c.
After depositing 7d, the semiconductor substrate 1 is heat-treated at about 800 ° C. The silicon oxide film 17d is formed of a plasma C using, for example, ozone and tetraethoxysilane as a source gas.
It is a TEOS oxide film deposited by the VD method. Further, by this heat treatment, n-type impurities in the polycrystalline silicon films forming plugs 19 and 25 diffuse from the bottoms of connection holes 37 and 38 into impurity semiconductor region 11 of MISFET Qs for memory cell selection, and impurity semiconductor region 11 is formed. The resistance is reduced.

Next, a photoresist using a photoresist film as a mask is used.
Silicon oxide on the connection hole 37 by light etching
The surface of the plug 19 is exposed by removing the film 17d. Next
After removing the photoresist film, the photoresist
Oxidation of peripheral circuits by dry etching with a mask film
Silicon films 17d, 17c, 17b, SOG film 17a and
By removing the gate insulating film 9 and the
N of MISFET Qn ⁺Above the semiconductor region 14b,
And p-channel MISFET p⁺Semiconductor region 15b
The connection hole 21 is formed in the upper part of.

Next, after removing the photoresist film, as shown in FIG. 8, a bit line BL and a first layer wiring 18 (M1) of a peripheral circuit are formed on the silicon oxide film 17d. Bit line BL and first layer wiring 18 (M1)
Is, for example, a film thickness of 50 n
A titanium film 18a having a thickness of about m and a titanium nitride film 18b having a thickness of about 50 nm are sequentially deposited by a sputtering method, and a tungsten film 18c having a thickness of about 150 nm and a silicon nitride film 22 having a thickness of about 200 nm are further formed thereon.
are sequentially deposited by the CVD method, and these films are formed by patterning these films using a photoresist film as a mask.

After removing the photoresist film, a titanium film is deposited on the silicon oxide film 17d, and then the semiconductor substrate 1 is heat-treated at about 800.degree.
Plug 1 embedded in the surface of n ^{+ type} semiconductor region 14b of channel MISFET Qn, the surface of p ^{+ type} semiconductor region 15b of p channel MISFET Qp, and connection hole 37
9, a low resistance titanium silicide layer 20 is formed.

Next, the bit line BL and the first layer wiring 18
A side wall spacer 22b is formed on the side wall of (M1). The side wall spacer 22b is connected to the bit line BL.
After a silicon nitride film is deposited on the first layer wiring 18 (M1) by a CVD method, the silicon nitride film is formed by anisotropic etching.

Next, as shown in FIG. 9, an SOG film 23a having a thickness of about 300 nm is spin-coated on the bit line BL and the upper layer of the first layer wiring 18 (M1).
Is heat-treated at 800 ° C. for about 1 minute to sinter (bake) the SOG film 23a.

Next, a film thickness of 600 is formed on the SOG film 23a.
After depositing a TEOS oxide film 23b of about nm,
The EOS oxide film 23b is polished by the CMP method to planarize the surface. The TEOS oxide film 23b is deposited by, for example, a plasma CVD method using ozone and tetraethoxysilane as a source gas.

Next, a TEOS oxide film 23c having a thickness of about 100 nm is deposited on the TEOS oxide film 23b. This TEOS oxide film 23c is deposited in order to repair fine scratches on the surface of the TEOS oxide film 23b generated when the surface is polished by the CMP method. The TEOS oxide film 23c is deposited by, for example, a plasma CVD method using ozone and tetraethoxysilane as a source gas.

Next, the plug 25 embedded in the connection hole 38 by dry etching using a photoresist film as a mask
TEOS oxide films 23c and 23b and SOG film 23
a and the silicon oxide film 17d are removed to form a through hole 39 reaching the surface of the plug 25. This etching is performed under conditions such that the etching rate of the silicon nitride film with respect to the TEOS oxide films 23c and 23b, the silicon oxide film 17d, and the SOG film 23a is increased, and even when the misalignment between the through hole 39 and the bit line BL occurs. In addition, the silicon nitride film 22a and the sidewall spacers 22b in the upper layer of the bit line BL are prevented from being cut deeply. Thereby, through hole 39 is formed in self alignment with bit line BL.

Next, after removing the photoresist film, a plug 26 is formed inside the through hole 39.
The plug 26 is formed by forming a polycrystalline silicon film doped with an n-type impurity (for example, phosphorus) on the TEOS oxide film 23c as a C layer.
After the deposition by the VD method, the polycrystalline silicon film is formed by etching back and leaving it inside the through hole 39.

Next, as shown in FIG. 10, a silicon nitride film 24a having a thickness of about 100 nm is deposited on the TEOS oxide film 23c by the CVD method.
A silicon oxide film 24b having a thickness of about 1.3 μm is deposited on the upper layer, and then the silicon oxide film 24b and the silicon nitride film 24a are removed by dry etching using a photoresist film as a mask. A groove 40 is formed. The silicon oxide film 24b is, for example, a TEOS oxide film deposited by a plasma CVD method using ozone and tetraethoxysilane as a source gas.

Next, after removing the photoresist film, as shown in FIG. 11, an amorphous silicon film 41 is formed on the silicon oxide film 24b at a temperature of about 600 ° C. by CVD.
Deposit at a temperature of. The amorphous silicon film 41 is used as a material of the storage electrode 27 of the information storage capacitor C. In addition, as the material of the storage electrode 27, in addition to the amorphous silicon film 41, a metal film such as a ruthenium film or a titanium nitride film may be used.

Next, a groove 4 is formed on the amorphous silicon film 41.
SO having a film thickness (for example, about 2 μm) larger than the depth of 0
After spin coating the G film 42, the SOG film 42 is etched back to expose the amorphous silicon film 41 on the silicon oxide film 24b.

Further, as shown in FIG. 12, by etching back the amorphous silicon film 41 above the silicon oxide film 24b, the amorphous silicon film 41 is left inside the trench 40 (the inner wall and the bottom). . Next, the SOG film 42 inside the groove 40 is wet-etched to form the storage electrode 27 of the information storage capacitor C.

Next, a capacitor insulating film 28 having a laminated structure of the information storage capacitor C is formed. First, as shown in FIG. 13, a first tantalum oxide film 28a is formed on the storage electrode 27. The first tantalum oxide film 28a is made of, for example, a heat CV having a temperature of 600 ° C. or less using an organic material such as pentaethoxy tantalum (Ta (OC ₂ H ₅ ) ₅ ) as a raw material.
Using method D, deposition is performed in an oxidizing atmosphere such as oxygen, nitrous oxide, ozone, or oxygen plasma at a reduced pressure of about 40 mTorr.

Thereafter, the semiconductor substrate 1 is subjected to a heat treatment at a temperature of 600 ° C. or more in an oxidizing atmosphere such as oxygen, dinitrogen monoxide, ozone, or oxygen plasma to modify and crystallize the first tantalum oxide film 28a. . After heat treatment at a temperature of 600 ° C. or less in an oxidizing atmosphere, heat treatment at a temperature of 600 ° C. or more in an inert gas atmosphere, or after heat treatment at a temperature of 600 ° C. or more in an inert gas atmosphere 600 in an oxidizing atmosphere
The modified crystallization treatment may be performed by performing a heat treatment at a temperature of not more than ° C.

Next, a first titanium oxide film 28b is formed on the first tantalum oxide film 28a. The first titanium oxide film 28b is formed, for example, by a CVD method using an organic material containing titanium or a halide of titanium as a raw material in an oxidizing atmosphere such as oxygen, dinitrogen monoxide, ozone, or oxygen plasma under reduced pressure. Is deposited.

Thereafter, the semiconductor substrate 1 is subjected to a heat treatment in an oxidizing atmosphere such as oxygen, nitrous oxide, ozone, or oxygen plasma to modify and crystallize the first titanium oxide film 28b. Note that, after performing the oxygen defect reforming treatment in an oxidizing atmosphere, the crystallization treatment may be performed in an inert gas atmosphere, or after performing the crystallization treatment in an inert gas atmosphere, the oxygen deficiency modifying treatment may be performed in an oxidizing atmosphere. Quality processing may be performed.

Next, a second tantalum oxide film 28c is formed on the first titanium oxide film 28b in the same manner as in the method of manufacturing the first tantalum oxide film 28a.
A second titanium oxide film 28d is formed on the second tantalum oxide film 28c in the same manner as in the method of manufacturing the titanium oxide film 28b. Thereby, the first tantalum oxide film 28a and the first
The capacitance insulating film 28 including the titanium oxide film 28b, the second tantalum oxide film 28c, and the second titanium oxide film 28d is formed.

Next, as shown in FIG.
8, a metal film having a thickness of about 150 nm, for example, a ruthenium film or a titanium nitride film is deposited by a CVD method, and then the metal film and the capacitor insulating film 28 are dry-etched using a photoresist film as a mask. By patterning, a plate electrode 29 made of a metal film, for example, a ruthenium film or a titanium nitride film, and a first tantalum oxide film 28a, a first titanium oxide film 28b, a second tantalum oxide film 28c, and a second tantalum oxide film Capacitance insulating film 28 having a laminated structure of 28d
And the storage electrode 27 made of the amorphous silicon film 41 to form the information storage capacitance element C. Thus, a DRAM memory cell composed of the memory cell selection MISFET and the information storage capacitor C connected in series to the MISFET is formed.

Next, as shown in FIG. 15, a TEOS oxide film is deposited on the plate electrode 29 to form an insulating film 30, and a connection hole connected to the first layer wiring 18 (M1) is opened in the peripheral circuit. Thus, a plug 32 is formed. The plug 32
An adhesive layer 32a made of a titanium film and a titanium nitride film is deposited on the insulating film 30, a tungsten film 32b is further deposited by a blanket CVD method, and then the tungsten film 32b and the adhesive layer 32a are formed by etching back. can do. Note that the titanium film and the titanium nitride film can be formed by a sputtering method, but can also be formed by a CVD method. Further, a titanium film 3 is formed on the insulating film 30.
1a, an aluminum film 31b and a titanium nitride film 31c are sequentially deposited by a sputtering method, and these are patterned to form a second-layer wiring 31 (M2).

Finally, the TEOS oxide film 33a, the SOG film 33b, and the TEOS oxide film are formed on the second layer wiring 31 (M2).
An oxide film 33c is sequentially deposited to form an interlayer insulating film 33,
A plug 35 is formed in the same manner as the second layer wiring 31 (M2),
Further, a third layer wiring 34 (M3) is formed, and the DRAM shown in FIG. 1 is almost completed. After that, a passivation film is deposited on the multilayer wiring and the uppermost wiring, but illustration thereof is omitted.

In the first embodiment, the capacitance insulating film 2
8 is a first tantalum oxide film 28a, a first titanium oxide film 28
b, the second tantalum oxide film 28c and the second titanium oxide film 28d have a laminated structure of four layers deposited in order from the bottom, but the first titanium oxide film 28b, the first tantalum oxide film 28a, the second titanium oxide film A stacked structure in which the film 28d and the second tantalum oxide film 28c are sequentially deposited from the lower layer may be used, or the capacitance insulating film 28 may be formed by stacking a plurality of two-layered structures including a titanium oxide film and a tantalum oxide film. Is also good.

FIG. 16 and FIG. 17 show a capacitor insulating film having a stacked structure in which n stacked layers of a titanium oxide film and a tantalum oxide film are stacked. FIG. 16 shows a capacity insulating film in which a tantalum oxide film and a titanium oxide film are alternately stacked from the lower layer, and FIG. 17 shows a capacity insulating film in which the titanium oxide film and the tantalum oxide film are alternately stacked from the lower layer. Show.

In any case, by laminating a titanium oxide film having a relative dielectric constant of 100 to 200 and a tantalum oxide film, a higher relative dielectric constant than a single layer of a tantalum oxide film can be obtained. However, if the titanium oxide film and the tantalum oxide film are excessively stacked, a problem such as a reduction in the storage capacity of the capacitor insulating film and an inability to cope with microfabrication occurs. Is set to 50 nm or less.

Further, the capacitance insulating film 28 may be constituted by a tantalum titanate film instead of the laminated film of the titanium oxide film and the tantalum oxide film (FIG. 1).
8) Alternatively, the capacitance insulating film 28 may be configured by stacking a plurality of tantalum titanate films (FIG. 19). In this tantalum titanate film, a specific dielectric constant higher than that of a single layer of the tantalum oxide film can be obtained by forming titanium or titanium oxide in the tantalum oxide film.

Next, a method for manufacturing a tantalum titanate film will be briefly described. First, for example, a CVD method using an organic material such as pentaethoxy tantalum and an organic material containing titanium or a halide of titanium as a raw material is applied to the upper layer of the storage electrode. Alternatively, it is deposited in an oxidizing atmosphere such as oxygen plasma.

Thereafter, the semiconductor substrate 1 is subjected to a heat treatment in an oxidizing atmosphere such as oxygen, dinitrogen monoxide, ozone or oxygen plasma to modify and crystallize the tantalum titanate film. Note that, after performing the oxygen defect reforming treatment in an oxidizing atmosphere, the crystallization treatment may be performed in an inert gas atmosphere, or after performing the crystallization treatment in an inert gas atmosphere, the oxygen deficiency modifying treatment may be performed in an oxidizing atmosphere. Quality processing may be performed.

As described above, according to the first embodiment, the capacitance insulating film 28 constituting the information storage capacitance element C is
Titanium oxide film having a relative dielectric constant of 0 to 200 and 20 to 5
With a stacked structure of a tantalum oxide film having a relative dielectric constant of 0, the capacitor insulating film 28 having a higher relative dielectric constant than a single layer of a tantalum oxide film can be obtained. In addition, by forming the capacitor insulating film 28 with a tantalum titanate film, titanium or titanium oxide is formed in the tantalum oxide film, and the capacitor insulating film 28 having a higher relative dielectric constant than a single layer of the tantalum oxide film is obtained. be able to.

(Embodiment 2) A method of manufacturing an information storage capacitance element having a storage electrode on which a projection made of silicon grains is formed according to Embodiment 2 will be described in the order of steps with reference to FIGS. I do.

First, in the same manufacturing method as in the first embodiment, as shown in FIG.
After the interlayer insulating film 23 is formed on the layer wiring 18 (M1), the plug 26 connected to the information storage capacitor C is formed inside the through hole 39.

Next, as shown in FIG.
After a silicon nitride film 24a is deposited on the upper layer 3 by the CVD method, a silicon oxide film 24b and a silicon nitride film 24c having a thickness of about 1.3 μm are sequentially deposited on the silicon nitride film 24a to form a three-layer structure. An insulating film 24 is formed.
The silicon nitride film 24c functions as an etching or polishing stopper. Next, a groove 40 is formed above the through hole 39 by removing the insulating film 24 by dry etching using a photoresist film as a mask.

Next, after the photoresist film is removed, the damaged layer on the surface of the plug 26 is removed, and the polycrystalline silicon film 43a containing impurities is formed on the insulating film 24.
Is deposited at a temperature of about 600 ° C. using a CVD method. Subsequently, an SOG film 42 having a thickness larger than the depth of the groove 40 is spin-coated on the upper layer of the polycrystalline silicon film 43a.
The film 42 is etched back to expose the polycrystalline silicon film 43a on the insulating film 24. In addition, a photoresist film may be used in addition to the SOG film 42. In this case,
The photoresist film is removed by the asher removal.

Further, as shown in FIG.
Is removed by an etch-back method or a polishing method, so that the polycrystalline silicon film 43a is left inside the groove 40 (the inner wall and the bottom).

Next, as shown in FIG. 22, after the SOG film 42 inside the groove 40 is wet-etched, the surface of the polycrystalline silicon film 43a is cleaned using a hydrofluoric acid-based solution, and then the CVD method is used. Si in a vacuum of 1 Pa or less
The polycrystalline silicon film 4 is irradiated with H ₄ gas for about 150 seconds.
A silicon crystal nucleus (not shown) is formed on the surface of 3a. Next, in a vacuum of 10 ⁻⁵ Pa or less, for example, 620
By performing a heat treatment at a temperature of about 150 ° C. for about 150 seconds,
The silicon crystal nuclei on the surface of the polycrystalline silicon film 43a are grown to form silicon grains 43b. The accumulation of the information storage capacitor C composed of the polycrystalline silicon film 43a and the silicon grains 43b formed on this surface is performed. An electrode 43 is formed.

Next, for example, 700
Heat treatment is performed on the semiconductor substrate 1 at about 900 ° C. for about 1 to 10 minutes to form a silicon oxynitride film 44 on the storage electrode 43. By providing the silicon oxynitride film 44, a silicon oxide film can be prevented from being formed between the storage electrode 43 and the capacitor insulating film 28, and a reduction in storage capacitance can be prevented.

Next, as shown in FIG. 23, a capacitance insulating film 28 made of a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film is formed by the same manufacturing method as in the first embodiment. After that, a plate electrode 29 made of a metal film, for example, a ruthenium film or a titanium nitride film is formed. Thus, a plate electrode 29 made of a metal film, for example, a ruthenium film or a titanium nitride film, and a laminated film of a titanium oxide film and a tantalum oxide film, or a capacitive insulating film 2 made of a tantalum titanate film
8 and a storage element 43 composed of a polycrystalline silicon film 43a and a storage electrode 43 composed of silicon grains 43b formed on the surface thereof.

In the second embodiment, the storage electrode 43
Is composed of the polycrystalline silicon film 43a, but may be composed of an amorphous silicon film.

As described above, according to the second embodiment, the titanium oxide film and the tantalum oxide film are formed on the storage electrode 43 composed of the polycrystalline silicon film 43a on which the projections made of the silicon grains 43b are formed. By forming the capacitor insulating film 28 made of a laminated film of tantalum titanate, the surface area of the storage electrode 43 increases, and the formation of the capacitor insulating film 28 having a higher relative dielectric constant than that of the single layer of the tantalum oxide film. In addition, it is possible to increase the storage capacitance of the information storage capacitor C.

(Embodiment 3) FIGS. 24 to 27 show a method of manufacturing an information storage capacitance element having a storage electrode formed of a metal film, for example, a ruthenium film or a titanium nitride film, according to a third embodiment. Will be described in the order of the steps.

First, in the same manufacturing method as in the first embodiment, as shown in FIG.
After the interlayer insulating film 23 is formed on the layer wiring 18 (M1), the plug 26 connected to the information storage capacitor C is formed inside the through hole 39.

Next, as shown in FIG.
After a silicon nitride film 24a is deposited on the upper layer 3 by the CVD method, a silicon oxide film 24b and a silicon nitride film 24c having a thickness of about 1.3 μm are sequentially deposited on the silicon nitride film 24a to form a three-layer structure. An insulating film 24 is formed.
Next, by removing the insulating film 24 by dry etching using a photoresist film as a mask, the through holes 3 are removed.
A groove 40 is formed on the upper part of the substrate 9.

Next, after removing the photoresist film, the damaged layer on the surface of the plug 26 is removed.
In order to prevent a reaction between the plug 26 and the storage electrode connected thereto, a reaction prevention layer 45 is formed on the plug 26. Next, a metal film 46a made of, for example, a ruthenium film or a titanium nitride film is formed on the insulating film 24.
Is deposited using a CVD method. Subsequently, the SOG film 42 having a thickness larger than the depth of the groove 40 is spin-coated on the upper layer of the metal film 46a, and then the SOG film 42 is etched back to expose the metal film 46a on the insulating film 24. Note that SO
In addition to the G film 42, a photoresist film may be used. In this case, the photoresist film is removed by removing the asher.

Further, as shown in FIG.
By removing the metal film 46a on the upper side of the groove 40 by an etch back method or a polishing method, the inside of the groove 40 (the inner wall and the bottom)
The metal film 46a is left. Next, as shown in FIG.
By wet-etching the SOG film 42 inside the groove 40, the storage electrode 46 of the information storage capacitor C made of the metal film 46a is formed.

Next, as shown in FIG. 27, a capacitor insulating film 28 made of a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film is formed by the same manufacturing method as in the first embodiment. After that, a plate electrode 29 made of a metal film, for example, a ruthenium film or a titanium nitride film is formed. Thus, a plate electrode 29 made of a metal film, for example, a ruthenium film or a titanium nitride film, and a laminated film of a tantalum oxide film and a titanium oxide film, or a capacitance insulating film 2 made of a tantalum titanate film
8 and a storage element 46 composed of a metal film 46a, for example, a ruthenium film or a titanium nitride film, are formed.

As described above, according to the third embodiment, the laminated film of the titanium oxide film and the tantalum oxide film or the capacitance insulating film of the tantalum titanate film is formed on the storage electrode 46 constituted by the metal film 46a. By forming the film 28,
The formation of a silicon oxide film or a nitride film on the surface of the storage electrode 46 can be prevented, and the formation of the capacitance insulating film 28 having a higher dielectric constant than that of a single layer of a tantalum oxide film allows the storage of the information storage capacitance element C. The capacity can be increased.

(Embodiment 4) A method of manufacturing an n-channel MIS transistor having a gate insulating film composed of a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film according to the fourth embodiment will be described. The steps will be described with reference to FIGS.

First, as shown in FIG. 28, a semiconductor substrate 47 made of, for example, p-type single crystal silicon is prepared.
Next, an element isolation groove 48a is formed in the semiconductor substrate 47, and an element isolation region 48 is formed by embedding an insulating film 48b in the element isolation groove 48a. Next, heat treatment is performed on the semiconductor substrate 47 at 700 to 900 ° C. for about 1 to 10 minutes in an ammonia atmosphere, for example, to form a silicon oxynitride film 49 a on the surface of the semiconductor substrate 47.

[0102] Next, as shown in FIG. 29, are sequentially deposited by CVD a first dielectric 49b ₁ and the second dielectric 49b ₂ on the upper layer of silicon oxynitride film 49a. Silicon oxynitride film 49a, first dielectric 49b ₁ and second dielectric 49b ₁
Laminated film made of the dielectric 49 ₂ constituting the gate insulating film 49. Here, the first dielectric 49b ₁ is composed of a tantalum oxide film, a second dielectric 49b ₂ is composed of a titanium oxide film. Alternatively, first dielectric 49b ₁ is composed of a titanium oxide film, the second dielectric 49b ₂ is composed of a tantalum oxide film.

Next, as shown in FIG. 30, a polycrystalline silicon film 50a doped with n-type impurities is deposited on the gate insulating film 49 by the CVD method, and then a barrier layer made of, for example, tungsten nitride is formed. For example, a high melting point metal film made of, for example, tungsten is sequentially deposited from the lower layer to form a metal film 50b having a laminated structure.

Next, the metal film 50b and the polycrystalline silicon film 50a are sequentially etched using the resist pattern as a mask to form a gate electrode 50 composed of the polycrystalline silicon film 50a and the metal film 50b.

Thereafter, an n-type impurity, for example, arsenic is implanted into the semiconductor substrate 47 by ion implantation, and a pair of low impurity concentrations forming a part of the source and the drain are formed in the semiconductor substrate 47 on both sides of the gate electrode 50. the n ^- type semiconductor region 51
To form

Next, as shown in FIG.
After a silicon nitride film is deposited on the gate electrode 7 by a CVD method, the silicon nitride film is anisotropically etched by a RIE (Reactive Ion Etching) method to form a sidewall spacer 52 on a side wall of the gate electrode 50.

Thereafter, an n-type impurity, for example, phosphorus is implanted into the semiconductor substrate 47 by ion implantation, and a pair of high-impurity impurities forming another part of the source and the drain are implanted into the semiconductor substrate 47 on both sides of the gate electrode 50. An n ^{+ type} semiconductor region 53 having a concentration is formed.

Next, as shown in FIG.
7, an interlayer insulating film 54 is deposited on the
4 is etched using the resist pattern as a mask, and a contact hole 55 is opened. Next, the interlayer insulating film 5
After depositing a metal film on the upper layer 4, the surface of the metal film is flattened by, for example, a CMP method to bury the metal film inside the contact hole 55 to form a plug 56. After that, the metal film deposited on the interlayer insulating film 54 is etched to form the wiring layer 57. This allows
The MIS transistor according to the fourth embodiment is formed.

In the fourth embodiment, the upper dielectric film of the silicon oxynitride film 49a has a two-layer structure, but may have three or more layers, or a single-layer film made of a tantalum titanate film. It may be.

As described above, according to the fourth embodiment, M
By forming the gate insulating film 49 of the IS transistor from a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film, the effective thickness (SiO ₂ equivalent film thickness) of the gate insulating film 49 can be reduced. In addition, since the overall thickness can be increased, the leakage current can be reduced.

The invention made by the inventor has been specifically described based on the embodiments of the present invention. However, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

For example, in the above embodiment, a laminated film of a titanium oxide film and a tantalum oxide film, or a tantalum titanate film is formed by using a capacitor insulating film of an information storage capacitor element and an MI layer.
Although the description has been given of the case where the present invention is applied to the gate insulating film of the S transistor, the present invention can be applied to any insulating film requiring a relative dielectric constant of about 50 to 200.

[0113]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, a single layer of a tantalum oxide film can be obtained by forming a capacitive insulating film constituting an information storage capacitor element from a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film. A capacitor insulating film having a higher relative dielectric constant can be obtained. This makes it possible to increase the storage capacitance of the information storage capacitor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate showing a DRAM having an information storage capacitor element according to a first embodiment of the present invention;

FIG. 2 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 13 is a cross-sectional view of a main part of the semiconductor substrate, showing a part of the information storage capacitor element according to the first embodiment of the present invention in an enlarged manner;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM having the information storage capacitance element according to the first embodiment of the present invention;

FIG. 16 is an enlarged cross-sectional view of a main part of the semiconductor substrate, illustrating a part of the information storage capacitor element according to the first embodiment of the present invention;

FIG. 17 is a cross-sectional view of a principal part of the semiconductor substrate, showing a part of the information storage capacitor element according to the first embodiment of the present invention in an enlarged manner;

FIG. 18 is an enlarged cross-sectional view of a main part of the semiconductor substrate, illustrating a part of the information storage capacitor element according to the first embodiment of the present invention;

FIG. 19 is an essential part cross-sectional view of the semiconductor substrate, showing a part of the information storage capacitor element according to the first embodiment of the present invention in an enlarged manner;

20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor according to the second embodiment of the present invention; FIG.

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor element according to the second embodiment of the present invention;

FIG. 22 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor element according to the second embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor according to the second embodiment of the present invention;

24 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor element according to the third embodiment of the present invention; FIG.

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor according to the third embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor element according to the third embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the information storage capacitor according to the third embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MIS transistor according to the fourth embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MIS transistor according to the fourth embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MIS transistor according to the fourth embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MIS transistor according to the fourth embodiment of the present invention;

FIG. 32 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the MIS transistor according to the fourth embodiment of the present invention;

[Explanation of symbols]

Reference Signs List 1 semiconductor substrate 2 p-type well 3 p-type well 4 n-type well 5 deep well 6 isolation region 7 shallow groove 8 silicon oxide film 9 gate insulating film 10 gate electrode 10A gate electrode 10B gate electrode 10C gate electrode 10a polycrystalline silicon film 10b titanium nitride film 10c tungsten film 11 impurity semiconductor regions 12 the cap insulating film 13 a silicon nitride film 14 doped semiconductor regions 14a n ^- type semiconductor region 14b n ⁺ type semiconductor region 15 the impurity semiconductor regions 15a p ^- type semiconductor region 15b p ⁺ -type semiconductor Region 16 Sidewall spacer 17 Interlayer insulating film 17a SOG film 17b TEOS oxide film 17c TEOS oxide film 17d Silicon oxide film 18 (M1) First layer wiring 18a Titanium film 18b Titanium nitride film 18c Tungsten film 1 Plug 20 Titanium silicide layer 21 Connection hole 22a Silicon nitride film 22b Sidewall spacer 23 Interlayer insulating film 23a SOG film 23b TEOS oxide film 23c TEOS oxide film 24 Insulating film 24a Silicon nitride film 24b Silicon oxide film 24c Silicon nitride film 25 Plug 26 Plug 27 Storage electrode 28 Capacitive insulating film 28a First tantalum oxide film 28b First titanium oxide film 28c Second tantalum oxide film 28d Second titanium oxide film 29 Plate electrode 30 Insulating film 31 (M2) Second layer wiring 31a Titanium film 31b Aluminum Film 31c Titanium nitride film 32 Plug 32a Adhesive layer 32b Tungsten film 33 Interlayer insulating film 33a TEOS oxide film 33b SOG film 33c TEOS oxide film 34 (M3) Third layer wiring 35 Plug 36 Photoresist film 37 Connection hole 38 Connection hole 39 Through hole 40 Groove 41 Amorphous silicon film 42 SOG film 43 Storage electrode 43a Polycrystalline silicon film 43b Silicon grain 44 Silicon oxynitride film 45 Reaction prevention layer 46 Storage electrode 46a Metal film 47 Semiconductor substrate 48 device below ground region 48a isolation trench 48b insulating film 49 a gate insulating film 49a of silicon oxynitride film 49b ₁ first dielectric 49b ₂ second dielectric 50 gate electrode 50a polycrystalline silicon film 50b metal film 51 n ^- Type semiconductor region 52 sidewall spacer 53 n ^{+ type} semiconductor region 54 interlayer insulating film 55 contact hole 56 plug 57 wiring layer A memory array region B peripheral circuit region WL word line BL bit line C information storage capacitor element Qs memory cell selection MISFET Qn n cha Le MISFET Qp p-channel MISFET

Continued on the front page F term (reference) 5F083 AD10 AD24 AD62 GA09 JA05 JA06 JA33 JA35 JA38 JA39 JA40 MA06 MA16 MA17 NA01 NA08 PR03 PR05 PR06 PR12 PR21 PR22 PR23 PR33 PR39 PR40 PR43 PR44 PR45 PR53 PR54 PR55

Claims (5)

[Claims] 1. A semiconductor integrated circuit device having a stacked film of a titanium oxide film and a tantalum oxide film, or an insulating film formed of a tantalum titanate film. 2. An insulating film comprising a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film, wherein the entire thickness of the insulating film is about 50 nm or less. Semiconductor integrated circuit device. 3. An insulating film comprising a laminated film of a titanium oxide film and a tantalum oxide film or a tantalum titanate film, wherein the insulating film is a ruthenium film, a titanium nitride film, a silicon film or a silicon particle. A semiconductor integrated circuit device formed on an electrode composed of a silicon film on which a protrusion made of a silicon is formed. 4. A method of manufacturing a semiconductor integrated circuit device for forming a laminated film of a titanium oxide film and a tantalum oxide film,
Depositing a titanium oxide film in an oxidizing atmosphere under reduced pressure using a CVD method using a titanium-containing organic material or a titanium halide as a raw material, and then subjecting the titanium oxide film to a crystallization treatment; C made from material
Depositing a tantalum oxide film in an oxidizing atmosphere under reduced pressure using a VD method, and then subjecting the tantalum oxide film to a crystallization process. 5. A method of depositing a tantalum titanate film in an oxidizing atmosphere under reduced pressure using a CVD method using an organic material containing tantalum and an organic material containing titanium or a halide of titanium as a raw material. A method for manufacturing a semiconductor integrated circuit device, comprising a step of subjecting a tantalum film to a crystallization process.