JP4357510B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

  The present invention relates to a technology for manufacturing a semiconductor integrated circuit device, and more particularly to a technology effective when applied to the manufacture of a semiconductor integrated circuit device in which a DRAM (Dynamic Random Access Memory) and a logic LSI are mixedly mounted.

  In recent years, a DRAM, which is a typical memory LSI, has an information storage capacitor disposed above a memory cell selection MISFET in order to compensate for a decrease in the amount of charge stored in the information storage capacitor due to the miniaturization of memory cells. The so-called stacked capacitor structure is adopted. A DRAM adopting this type of stacked capacitor structure is described in, for example, Japanese Patent Laid-Open No. 8-204144 (Patent Document 1).

On the other hand, in a high-performance logic LSI, CoSi ₂ (cobalt silicide) or TiSi is formed on the surfaces of the source and drain as a measure for suppressing an increase in resistance due to miniaturization of contact holes connecting the source and drain of MISFET and wiring. _2. Adoption of a so-called silicidation technique for forming a refractory metal silicide layer such as ₂ (titanium silicide) is underway.
JP-A-8-204144

  The inventor has been developing a so-called system LSI in which the above-described DRAM and logic LSI are formed on the same semiconductor substrate.

  The DRAM constituting a part of the system LSI includes a bit line made of a low-resistance metal material mainly composed of a refractory metal such as W (tungsten) as a bit line signal delay measure, and a wiring formation process. As a measure to reduce the above, the first layer wiring of the bit line and the peripheral circuit is formed in the same process as the first layer wiring of the logic LSI.

In addition, in this DRAM, as a measure for securing the stored charge amount of the information storage capacitor element, the information storage capacitor element is disposed above the bit line to promote the three-dimensionalization of the capacitor element, and the capacitor insulating film is made Ta. A high dielectric material such as ₂ O ₅ (tantalum oxide) is used.

  Further, in this DRAM, when a contact hole for connecting a bit line and a substrate (source or drain) is formed in the space of the gate electrode of the memory cell selection MISFET having a narrow pitch, After the sidewall is covered with a silicon nitride film, a silicon oxide film is deposited on the sidewall, and the contact hole is self-aligned with the gate electrode by utilizing the etching rate difference between the silicon oxide film and the silicon nitride film. A so-called gate-self align contact (hereinafter referred to as gate-SAC) technique is employed.

  On the other hand, the logic LSI that constitutes another part of the system LSI adopts a silicidation technology that forms a low-resistance refractory metal silicide layer on the surface of the source and drain of the MISFET in order to promote high-speed operation. To do.

  In addition, this logic LSI has contact holes for connecting the source and drain to the first layer wiring in order to cope with the reduction in area of the source and drain for the purpose of miniaturization of the element and reduction of the junction capacitance. A so-called LOCOS-Self Align Contact (hereinafter referred to as L-SAC) technology that forms in a self-aligned manner with respect to the isolation region is employed.

  In the L-SAC technique, after the MISFET is formed, the upper part is covered with a silicon nitride film, and a silicon oxide film is deposited on the upper part of the silicon nitride film. In order to form contact holes above the source and drain, the silicon oxide film is first etched using the silicon nitride film as a stopper, and then the silicon nitride film below the silicon nitride film is etched to expose the source and drain. At this time, by forming the silicon nitride film with a relatively thin film thickness, the amount by which the silicon oxide film in the element isolation region is shaved during overetching can be reduced.

  However, in the manufacturing process of the system LSI in which the DRAM and the logic LSI as described above are formed on the same semiconductor substrate, the following problems must be solved.

  That is, in order to form a contact hole in a self-aligned manner using the gate-SAC technique in the space of the gate electrode of the memory cell selection MISFET constituting the DRAM memory cell, the upper and side walls of the gate electrode are formed of silicon nitride. It must be covered with a membrane. In this case, a gate processing process is performed by forming a conductive film for a gate electrode on a semiconductor substrate, subsequently forming a silicon nitride film on the top, and then etching the silicon nitride film and its lower layer by etching using a photoresist film as a mask. By patterning the gate electrode conductive film, the gate electrode of the memory cell selecting MISFET and the gate electrode of the logic LSI MISFET are formed simultaneously.

  However, in the above process, the silicon oxide film formed on the top of the MISFET is etched to form contact holes on the top of the source or drain of the memory cell selection MISFET and on the gate electrode and source and drain of the logic LSI MISFET. When forming, the problem arises that the upper part of the gate electrode of the logic LSI MISFET cannot be opened. That is, since the silicon nitride film for L-SAC is formed on the gate electrode of the MISFET of the logic LSI in addition to the silicon nitride film for gate-SAC described above, these two layers of silicon nitride films are etched. If a contact hole is to be formed on the gate electrode, the etching of the upper portions of the source and drain becomes excessive, and the silicon oxide film in the element isolation region is deeply etched to cause a serious problem such as an increase in junction leakage current. On the other hand, if the amount of etching on the top of the source and drain is reduced in order to reduce the chipping of the element isolation region, the amount of etching on the gate electrode is insufficient, so that the bottom of the contact hole does not reach the gate electrode. Arise.

  In addition, in order to avoid the above-mentioned problem, it may be possible to form the contact hole above the gate electrode and the contact hole above the source and drain in separate steps, but this measure not only increases the process. In the miniaturized MISFET, there arises a problem that it is not possible to secure a margin for alignment between the contact hole on the gate electrode and the contact hole on the source and drain.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a technique capable of making both a DRAM gate-SAC technique and a logic LSI L-SAC technique compatible in manufacturing a semiconductor integrated circuit device in which a DRAM and a logic LSI are mixedly mounted. .

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
The method of manufacturing a semiconductor integrated circuit device according to the present invention includes a first memory cell region in which DRAM memory cells in which a first MISFET and a capacitor are connected in series are arranged in a matrix, and a plurality of second MISFETs constituting a logic LSI. A method of manufacturing a semiconductor integrated circuit device having a formed second circuit region, comprising: (a) forming a gate electrode of the first MISFET in which a first insulating layer is selectively formed in the first memory cell region; Forming a gate electrode of the second MISFET in the second circuit region; and (b) forming a sidewall spacer on each side wall of the gate electrode of the first MISFET and the gate electrode of the second MISFET, (C) After the step (b), a second insulating layer is formed on the main surface of the semiconductor substrate, and then on the second insulating layer. Forming a third insulating layer and then polishing and planarizing the third insulating layer; and (d) the third insulating layer and the second insulating layer covering a space region between the gate electrodes of the first MISFET. Forming a first opening in a self-aligned manner with respect to the gate electrode of the first MISFET to expose the surface of the source or drain of the first MISFET; and (e) an upper portion of the gate electrode of the second MISFET. Forming a second opening in the third insulating layer and the second insulating layer covering the second MISFET to expose a surface of the gate electrode of the second MISFET and covering the upper part of the source or drain of the second MISFET. Exposing the surface of the source or drain of the second MISFET by forming a third hole in the insulating layer and the second insulating layer. In the step (a), after the first insulating layer is selectively formed on the first conductive layer of the first memory cell region, a gate electrode of the first conductive layer is patterned second 1MISFET and In the step of forming the gate electrode of the second MISFET and forming the first opening, after etching the third insulating layer under a condition that an etching rate of the third insulating layer with respect to the second insulating layer is increased, In the step of anisotropically etching the second insulating layer to form side wall spacers on the side walls of the gate electrode of the first MISFET and forming the second and third openings, the second insulating layer The third insulating layer is removed by etching under conditions that increase the etching rate of the third insulating layer.

  The method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a plurality of first gate electrodes made of a first conductor layer in a first region of a main surface of a semiconductor substrate; a first insulating layer covering the first gate electrode; Forming a plurality of second gate electrodes made of the first conductor layer in a second region of the main surface of the semiconductor substrate, and forming a plurality of semiconductor regions in a third region of the main surface of the semiconductor substrate. (B) forming a second insulating layer on the main surface of the semiconductor substrate and forming a third insulating layer on the second insulating layer; (c) forming the first region in the first region; A surface of the semiconductor substrate in the first space region is exposed by forming a first opening in the third insulating layer and the second insulating layer covering the first space region between the plurality of first gate electrodes. And (d) the plurality of second gates formed in the second region. By forming a second opening in the third insulating layer and the second insulating layer covering the electrode, the surface of the second gate electrode is exposed, and the plurality of semiconductor regions formed in the third region are formed. Forming a third opening in the covering third insulating layer and the second insulating layer to expose a surface of the semiconductor region, wherein in the step (a), the plurality of second gate electrodes The first insulating layer is not formed on the upper portion, and in the step (c), the first opening is formed in a self-alignment with the first gate electrode.

  In addition, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a first memory cell region in which DRAM memory cells in which a first MISFET and a capacitor are connected in series are arranged in a matrix, and a second MISFET constituting a logic LSI. A method of manufacturing a semiconductor integrated circuit device having a plurality of second circuit regions, wherein: (a) a first conductor layer is formed on a main surface of a semiconductor substrate; Forming a gate electrode of the second MISFET in the second circuit region by selectively patterning one conductor layer, and leaving the first conductor layer in the first memory cell region; (b) the semiconductor substrate; Forming a first insulating layer on the main surface of the first memory cell, and then selectively patterning the first insulating layer and the first conductor layer in the first memory cell region to thereby form the first memory cell Forming a gate electrode of the first MISFET covered with the first insulating layer in a region and leaving the first insulating layer in the second circuit region; (c) second insulating on a main surface of the semiconductor substrate; Forming a third insulating layer on the second insulating layer after forming the layer, and polishing and planarizing the third insulating layer; (d) a space region between the gate electrodes of the first MISFET; Forming a first opening in the third insulating layer and the second insulating layer covering the first MISFET in a self-aligned manner with respect to the gate electrode of the first MISFET, thereby exposing a surface of the source or drain of the first MISFET (E) forming a second opening in the third insulating layer, the second insulating layer, and the first insulating layer covering an upper portion of the gate electrode of the second MISFET, whereby a surface of the gate electrode of the second MISFET A third opening is formed in the third insulating layer, the second insulating layer, and the first insulating layer that are exposed and covers an upper portion of the source or drain of the second MISFET, thereby forming a source or drain of the second MISFET. The step of forming the first opening includes etching the third insulating layer under a condition that an etching rate of the third insulating layer with respect to the second insulating layer is increased; Forming the sidewall spacers on the sidewalls of the gate electrode of the first MISFET by anisotropically etching the two insulating layers, and forming the second and third apertures; After etching the third insulating layer under the condition that the etching rate of the third insulating layer is increased, the second insulating layer and the first insulating layer are etched. And are removed.

  In addition, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a first memory cell region in which DRAM memory cells in which a first MISFET and a capacitor are connected in series are arranged in a matrix, and a second MISFET constituting a logic LSI. A method of manufacturing a semiconductor integrated circuit device having a plurality of second circuit regions, wherein: (a) a first conductor layer is formed on a main surface of a semiconductor substrate, and then the first conductor layer is patterned. Forming a gate electrode of the second MISFET in the second circuit region and leaving the first conductor layer in the first memory cell region; and (b) a sidewall spacer on a sidewall of the gate electrode of the second MISFET. (C) forming the source and drain of the second MISFET on the semiconductor substrate on both sides of the gate electrode of the second MISFET; (D) forming a refractory metal layer on the main surface of the semiconductor substrate, and then heat-treating the semiconductor substrate to thereby form surfaces of the gate electrode, the source, and the drain of the second MISFET; Forming a silicide layer on a surface of the first conductor layer remaining in the first memory cell region; (e) after forming a first insulating layer on a main surface of the semiconductor substrate; By selectively patterning the first insulating layer and the first conductor layer in a region, a gate electrode of the first MISFET covered with the first insulating layer is formed in the first memory cell region, and the first Leaving the first insulating layer in two circuit regions; (f) forming a second insulating layer on the main surface of the semiconductor substrate; then forming a third insulating layer on the second insulating layer; Polish third insulation layer And (g) a first self-aligned with the gate electrode of the first MISFET in the third insulating layer and the second insulating layer covering the space region between the gate electrodes of the first MISFET. (H) exposing the surface of the source or drain of the first MISFET by forming an opening; (h) the third insulating layer, the second insulating layer, and the first covering the top of the gate electrode of the second MISFET; By forming a second opening in the insulating layer, the surface of the gate electrode of the second MISFET is exposed, and the third insulating layer, the second insulating layer, and the second covering the upper part of the source or drain of the second MISFET. Forming a third opening in one insulating layer to expose a surface of the source or drain of the second MISFET, and forming the first opening In the forming step, after the third insulating layer is etched under a condition that the etching rate of the third insulating layer with respect to the second insulating layer is increased, the second insulating layer is anisotropically etched, In the step of forming a side wall spacer on the side wall of the gate electrode of the first MISFET and forming the second and third openings, the first insulating layer is etched under a condition that an etching rate of the third insulating layer with respect to the second insulating layer is increased. After the three insulating layers are etched, the second insulating layer and the first insulating layer are removed by etching.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the manufacture of a semiconductor integrated circuit device in which a DRAM and a logic LSI are mixedly mounted, both the DRAM gate-SAC technology and the logic LSI L-SAC technology can be made compatible. Can be manufactured with high yield.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
This embodiment is applied to a system LSI manufacturing method in which a DRAM is arranged in a first area of a main surface of a semiconductor substrate, a logic LSI is arranged in a second area, and an SRAM is arranged in a third area. is there.

As shown in FIG. 1, a DRAM memory cell (MC) constituting a part of a system LSI is arranged at an intersection of a word line WL (WL _n−1 , WL _n , WL _{n + 1} ...) And a bit line BL. The memory cell selection MISFET Qs and one information storage capacitive element C connected in series to the memory cell selection MISFET Qs. One of the source and drain of the memory cell selection MISFET Qs formed of an n-channel type MISFET is electrically connected to the information storage capacitor element C, and the other is electrically connected to the bit line BL. One end of the word line WL is connected to the word driver WD of the peripheral circuit, and one end of the bit line BL is also connected to the sense amplifier SA of the peripheral circuit.

As shown in FIG. 2, an SRAM memory cell (MC) constituting another part of the system LSI includes a pair of complementary data lines (data line DL, data line / (bar) DL) and a word line WL. Are constituted by a pair of driving MISFETs Qd ₁ and Qd ₂ , a pair of load MISFETs Qp ₁ and Qp _2, and a pair of transfer MISFETs Qt ₁ and Qt ₂ . The drive MISFETs Qd ₁ and Qd ₂ and the transfer MISFETs Qt ₁ and Qt ₂ are configured by n-channel MISFETs, and the load MISFETs Qp ₁ and Qp ₂ are configured by p-channel MISFETs.

Of the six MISFETs constituting the SRAM memory cell (MC), the driving MISFET Qd ₁ and the load MISFET Qp ₁ constitute a CMOS inverter INV ₁ , and the driving MISFET Qd ₂ and the load MISFET Qp ₂ are CMOS inverters. INV ₂ is configured. The mutual input / output terminals (storage nodes A and B) of the pair of CMOS inverters INV ₁ and INV ₂ form a flip-flop circuit as an information storage unit that stores 1-bit information. One of the input and output terminals of the flip-flop circuit (storage node A) is connected for transfer MISFET Qt ₁ of the source region and electrically, the other input-output terminal (the storage node B), the source region of the transfer MISFET Qt ₂ And are electrically connected.

The drain region of the transfer MISFET Qt ₁ is connected to the data line DL, and the drain region of the transfer MISFET Qt ₂ is connected to the data line / DL. One end of the flip-flop circuit (the source regions of the load MISFETs Qp ₁ and Qp ₂ ) is connected to the power supply voltage (Vcc), and the other end (the source regions of the drive MISFETs Qd ₁ and Qd ₂ ) is connected to the reference voltage (Vss). )It is connected to the.

  Although illustration is omitted, a logic LSI that constitutes another part of the system LSI includes an n-channel MISFET and a p-channel MISFET.

  Next, an example of a method for manufacturing the system LSI will be described in the order of steps with reference to FIGS. In these figures, the left region is a part of the DRAM formation region (only the memory cell is shown), the central region is a part of the logic LSI formation region (only the n-channel MISFET is shown), and the right region is A part of the SRAM formation region (only a part of each of the driving MISFET and the load MISFET is shown) is shown.

  In order to manufacture the system LSI of the present embodiment, first, as shown in FIG. 3, after forming the element isolation trench 2 on the main surface of the semiconductor substrate 1 made of, for example, p-type single crystal silicon, A p-type impurity (for example, boron) is ion-implanted in one part and an n-type impurity (for example, phosphorus) is ion-implanted in the other part to form the p-type well 3 and the n-type well 4. Subsequently, a gate oxide film 5 is formed on the surfaces of the active regions of the p-type well 3 and the n-type well 4 by heat-treating the semiconductor substrate 1. The element isolation trench 2 is formed by etching the semiconductor substrate 1 in the element isolation region, and then depositing a silicon oxide film 6 on the semiconductor substrate 1 by a CVD method. It is formed by flattening by a mechanical polishing method and leaving only in the groove.

  Next, as shown in FIG. 4, a gate electrode conductive film 8 is formed on the gate oxide film 5, and a silicon nitride film 9 having a thickness of about 200 nm is deposited thereon by CVD. The gate electrode conductive film 8 is composed of a laminated film (polycide film) of a polycrystalline silicon film having a thickness of about 100 nm and a tungsten silicide film having a thickness of about 100 nm deposited by, for example, a CVD method. The polycrystalline silicon film is doped with an n-type impurity (for example, arsenic). In the case where the n-channel MISFET and the p-channel MISFET have a dual gate structure, after depositing a polycrystalline silicon film not containing impurities, an n-type impurity (in the polycrystalline silicon film in the n-channel MISFET formation region ( For example, arsenic) is doped, and a polycrystalline silicon film in the p channel MISFET formation region is doped with a p type impurity (for example, boron). In addition to the polycide film, the gate electrode conductive film 8 may be composed of, for example, a laminated film (polymetal film) of a polycrystalline silicon film, a tungsten nitride film, and a tungsten film.

  Next, as shown in FIG. 5, the silicon nitride film 9 in the DRAM formation region is patterned by etching using a photoresist film as a mask, thereby nitriding in the same pattern as the gate electrode 8A (word line WL) to be formed later. A silicon film 9 is formed. In this step, the silicon nitride film 9 in a region where a contact hole is formed on the gate electrode in a later step is also selectively removed.

  Next, as shown in FIG. 6, the gate electrode conductive film 8 is patterned by etching using the silicon nitride film 9 and the photoresist film 10 as a mask, so that the gate electrode 8A (word) of the MISFET Qs for memory cell selection of the DRAM is formed. Line WL), the gate electrode 8B of the n-channel type MISFET Qn of the logic LSI, the gate electrode 8C of the SRAM driving MISFET Qd, and the gate electrode 8D of the load MISFET Qp. Note that the silicon nitride film 9 is removed in advance in the step shown in FIG. 5 and covered with the photoresist film 10 at the time of gate processing at one end of the DRAM word line WL (wiring lead area indicated by the arrow in FIG. 6). This prevents the silicon nitride film 9 from remaining on the upper portion (FIG. 6).

  As described above, the manufacturing method according to the present embodiment leaves the silicon nitride film 9 only on the gate electrode 8A (word line WL) of the MISFET for memory cell selection of the DRAM (excluding the wiring drawing region of the word line WL). The silicon nitride film 9 is not left above the gate electrode 8B of the MISFET constituting the logic LSI and the gate electrodes 8C, 8D constituting the memory cell of the SRAM.

Next, as shown in FIG. 7, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 3 to form an n-type semiconductor region 11 constituting the source and drain of the memory cell selection MISFET Qs. At the same time, an n ⁻ type semiconductor region 12 is formed in the p type well 3 on both sides of the gate electrode 8B of the n channel MISFET Qn. Subsequently, a p ^- type semiconductor region 13 is formed in the n-type well 4 on both sides of the gate electrode 8D of the load MISFET Qp by ion-implanting a p-type impurity (for example, boron) into the n-type well 4. The DRAM memory cell selection MISFET Qs is substantially completed by the steps so far.

Next, as shown in FIG. 8, the silicon nitride film deposited on the semiconductor substrate 1 by the CVD method is processed by anisotropic etching, so that the side wall spacer made of the silicon nitride film is formed on the side walls of the gate electrodes 8A to 8D. 15 is formed. Subsequently, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 3 in the logic LSI formation region, thereby forming the n ⁺ -type semiconductor region 16 in the p-type well 3 on both sides of the gate electrode 8B of the n-channel MISFET Qn. Form. Further, by implanting a p-type impurity (for example, boron) into the n-type well 4 in the SRAM formation region, the p ⁺ -type semiconductor region 17 is formed in the n-type well 4 on both sides of the gate electrode 8D of the load MISFET Qp. Through the steps so far, the n channel type MISFET Qn of the logic LSI having the source and drain of the LDD (Lightly Doped Drain) structure composed of the n ⁻ type semiconductor region 12 and the n ⁺ type semiconductor region 16, the p ⁻ type semiconductor region 13 and The load MISFET Qp of the SRAM having the source and drain of the LDD structure composed of the p ⁺ type semiconductor region 17 is substantially completed.

Next, as shown in FIG. 9, the surface of the semiconductor substrate 1 is thinly etched with a hydrofluoric acid-based etchant, and the source and drain (n-type semiconductor region 11) of the memory cell selection MISFET Qs, the n-channel type MISFET Qn After the source and drain (n ⁺ type semiconductor region 16) and the source and drain (p ⁺ type semiconductor region 17) of the load MISFET Qp are exposed, a film thickness of about 5 to 10 nm deposited on the semiconductor substrate 1 by the CVD method is formed. By etching the thin silicon oxide film 19, the silicon oxide film 19 is left above the source and drain (n-type semiconductor region 11) of the memory cell selection MISFET Qs, and the source and drain (n ⁺ type semiconductor of the n-channel MISFET Qn). Region 16) and the source and drain of the load MISFET Qp (p ⁺ type semiconductor region) The silicon oxide film 19 on the surface of 17) is removed. The thin silicon oxide film 19 may be formed by thermally oxidizing the semiconductor substrate 1.

Next, as shown in FIG. 10, after depositing a Co (cobalt) film 20a on the semiconductor substrate 1 by a sputtering method, the semiconductor substrate 1 is subjected to heat treatment, whereby the source and drain (n ⁺ type) of the n-channel type MISFET Qn. A Co silicide layer 20 is formed on the surface of the semiconductor region 16) and the source and drain (p ⁺ type semiconductor region 17) of the load MISFET Qp. At this time, since the surfaces of the source and drain (n-type semiconductor region 11) of the memory cell selection MISFET Qs are covered with the silicon oxide film 19, the Co silicide layer 20 is not formed.

As described above, in the manufacturing method of the present embodiment, the source of the MISFET (n channel type MISFET Qn) constituting the logic LSI, the drain (n ⁺ type semiconductor region 16), and the source of the load MISFET Qp constituting the SRAM memory cell. By forming the Co silicide layer 20 on the surface of the drain (p ⁺ -type semiconductor region 17), the resistance of the source and drain is reduced and high speed operation of the logic LSI and SRAM is realized. On the other hand, by not forming the Co silicide layer 20 on the surface of the source and drain of the memory cell selection MISFET Qs constituting the DRAM memory cell, the leakage current of the memory cell is reduced and the deterioration of the refresh characteristic is prevented. The silicide layer may be formed using a refractory metal (for example, Ti) other than Co.

  Next, as shown in FIG. 11, a silicon nitride film 21 having a thickness of about 100 nm is deposited on the semiconductor substrate 1 by a CVD method, and then a silicon oxide film having a thickness of about 600 nm is deposited on the silicon nitride film 21 by a CVD method. After the film 22 is deposited, the surface of the silicon oxide film 22 is planarized by the CMP method.

  Next, as shown in FIG. 12, the silicon oxide film 22 above the source and drain (n-type semiconductor region 11) of the memory cell selection MISFET Qs is removed by etching using the photoresist film 23 as a mask. This etching is performed using a gas that etches the silicon oxide film 22 with a high selectivity with respect to the silicon nitride film 21 in order to prevent the silicon nitride film 21 below the silicon oxide film 22 from being removed.

  Next, as shown in FIG. 13, the silicon nitride film 21 above the source and drain (n-type semiconductor region 11) of the memory cell selection MISFET Qs is removed by etching using the photoresist film 23 as a mask. By removing the thin silicon oxide film 19 below, a contact hole 24 is formed in one upper part of the source and drain (n-type semiconductor region 11), and a contact hole 25 is formed in the other upper part.

  The above-described etching of the silicon nitride film 21 is performed using a gas that etches the silicon nitride film 21 with a high selectivity with respect to the silicon oxide film or silicon in order to minimize the scraping amount of the semiconductor substrate 1. Further, this etching is performed under the condition that the silicon nitride film 21 is anisotropically etched so that the silicon nitride film 21 is left on the side wall of the gate electrode 8A (word line WL). As a result, contact holes 24 and 25 having a diameter smaller than the space of the gate electrode 8A (word line WL) are formed in a self-aligned manner with respect to the gate electrode 8A (word line WL).

  Next, as shown in FIG. 14, plugs 26 are formed inside the contact holes 24 and 25. The plug 26 is formed by depositing a polycrystalline silicon film having a thickness of about 300 nm doped with an n-type impurity (for example, arsenic) on the silicon oxide film 22 by a CVD method, and then planarizing the polycrystalline silicon film by a CMP method. It is formed by leaving only inside the contact holes 24 and 25.

  Next, as shown in FIG. 15, after depositing a silicon oxide film 27 having a thickness of about 200 nm on the silicon oxide film 22 by a CVD method, the semiconductor substrate 1 is heat-treated in an inert gas atmosphere. Due to this heat treatment, n-type impurities in the polycrystalline silicon film constituting the plug 26 diffuse from the bottoms of the contact holes 24 and 25 into the n-type semiconductor region 11 (source, drain) of the memory cell selection MISFET Qs. The resistance of the n-type semiconductor region 11 is reduced.

Next, as shown in FIG. 16, the silicon oxide film 27 is etched using the photoresist film as a mask, thereby forming a through hole 30 above the contact hole 24. Subsequently, as shown in FIG. 17, the silicon oxide film 27 and the silicon oxide film 22 are etched using the photoresist film as a mask, and then the silicon nitride film 21 is etched, so that the upper portion of the wiring extraction region of the word line WL is formed. A contact hole 31 is formed, contact holes 32 and 33 are formed above the gate electrode 8B of the n-channel type MISFET Qn and the n ⁺ type semiconductor region 16, and the gate electrode 8C of the driving MISFET Qd and the p ⁺ type semiconductor of the load MISFET Qp. A contact hole 34 is formed in a region straddling the region 17.

  In the etching of the silicon oxide film 27 and the silicon oxide film 22, the silicon oxide films 27 and 22 are etched with a high selectivity with respect to the silicon nitride film 21 in order to prevent the lower silicon nitride film 21 from being removed. Use gas. In addition, the etching of the silicon nitride film 21 is performed on the silicon nitride film 21 with respect to the silicon oxide films 6 and 22 in order to minimize the scraping amount of the silicon oxide film 6 embedded in the element isolation trench 2 and the semiconductor substrate 1. This is done using a gas that etches with a high selectivity. As a result, the contact hole 33 is formed in self-alignment with the element isolation trench 2.

According to the manufacturing method described above, since the silicon nitride film 9 is not formed above the gate electrode 8B of the n-channel type MISFET Qn constituting the logic LSI, the contact hole 32 and the n ⁺ -type semiconductor region 16 above the gate electrode 8B are formed. The upper contact hole 33 can be formed simultaneously. Further, since the silicon nitride film 9 is not formed on the gate electrode 8C of the driving MISFET Qd constituting the SRAM memory cell, the gate electrode 8C of the driving MISFET Qd and the load are formed when the contact holes 32 and 33 are formed. A contact hole 34 can be simultaneously formed in a region straddling the p ⁺ type semiconductor region 17 of the MISFET Qp.

  Next, as shown in FIG. 18, plugs 36 are formed in the through holes 30 and the contact holes 31 to 34. The plug 36 is formed by depositing a titanium nitride film and a tungsten film on the silicon oxide film 27 by the CVD method, and then planarizing these films by the CMP method and leaving them only in the through holes 30 and the contact holes 31 to 34. To form.

  Next, as shown in FIG. 19, a tungsten film having a thickness of about 100 nm is deposited on the silicon oxide film 27 by a CVD method (or sputtering method), and then the tungsten film is patterned to form the through hole 30. Bit lines BL are formed on the upper portions, and wirings 37 to 40 are formed on the upper portions of the contact holes 31 to 34.

  Next, as shown in FIG. 20, a silicon oxide film 41 having a film thickness of about 300 nm is deposited on the bit line BL and the wirings 37 to 40 by the CVD method, and then the silicon oxide film 41 and the photoresist film are used as a mask. By etching the silicon oxide film 27, a through hole 42 is formed above the contact hole 25. Subsequently, a plug 43 made of a polycrystalline silicon film is formed inside the through hole 42 in the same manner as when the plug 26 is formed inside the contact holes 24 and 25.

  Next, as shown in FIG. 21, a silicon nitride film 44 having a thickness of about 200 nm is deposited on the silicon oxide film 41 by the CVD method, and then etched in a region other than the DRAM formation region by using a photoresist film as a mask. The silicon nitride film 44 is removed. The silicon nitride film 44 remaining in the DRAM formation region is used as an etching stopper when the silicon oxide film (45) is etched in the step of forming the lower electrode 47 of the information storage capacitor element C to be described later.

  Next, as shown in FIG. 22, after a silicon oxide film 45 is deposited on the silicon nitride film 44 by a CVD method, the silicon oxide film 45 and the silicon nitride film 44 are etched using the photoresist film as a mask. A concave groove 46 is formed in the upper portion of the through hole 42. Since the lower electrode 47 of the information storage capacitor C is formed along the inner wall of the concave groove 46, the silicon oxide film 45 is made thicker in order to increase the surface area of the lower electrode 47 and increase the amount of stored charge. Deposited with a film thickness (for example, about 1.3 μm).

  Next, as shown in FIG. 23, a polycrystalline silicon film 47a having a thickness of about 60 nm doped with an n-type impurity (for example, phosphorus) is deposited on the upper portion of the silicon oxide film 45 including the inside of the concave groove 46 by the CVD method. . This polycrystalline silicon film 47a is used as a lower electrode material of the information storage capacitive element C. Subsequently, a spin-on-glass film 48 having a film thickness of about 300 nm is spin-coated on the polycrystalline silicon film 47a, and then the spin-on-glass film 48 is etched back (or planarized by CMP) so that only the inside of the groove 46 is formed. To leave.

  Next, as shown in FIG. 24, the polycrystalline silicon film 47a in a region other than the DRAM formation region is covered with a photoresist film 49, and the polycrystalline silicon film 47a above the silicon oxide film 45 is removed by etching. A lower electrode 47 is formed along the inner wall of the concave groove 46. The lower electrode 47 may be formed using a conductive material other than polycrystalline silicon, for example, a refractory metal such as tungsten or ruthenium, or a conductive metal oxide such as ruthenium oxide or iridium oxide. Further, the surface area of the lower electrode 47 may be further increased by roughening the surface.

  Next, as shown in FIG. 25, the silicon oxide film 45 remaining in the gap between the concave groove 46 and the adjacent concave groove 46 and the spin-on-glass film 48 inside the concave groove 46 are removed with a hydrofluoric acid-based etching solution. After that, by removing the polycrystalline silicon film 47a in the region other than the DRAM formation region by etching using the photoresist film as a mask, the cylindrical lower electrode 47 is completed. Since the silicon nitride film 44 is formed on the bottom of the silicon oxide film 45 in the gap of the concave groove 46, the lower silicon oxide film 41 is not etched when the silicon oxide film 45 is wet etched. At this time, since the polycrystalline silicon film 47a is formed on the silicon oxide film 45 in the region other than the DRAM formation region, the silicon oxide film 45 in this region is not etched.

Next, as shown in FIG. 26, a thin tantalum oxide film 50 having a thickness of about 14 nm is deposited on the upper portion of the lower electrode 47 by the CVD method, and then, for example, the CVD method and the sputtering method are formed on the tantalum oxide film 50. After depositing the titanium nitride film in combination, the titanium nitride film and the tantalum oxide film 50 are patterned by etching using the photoresist film as a mask, so that the upper electrode 51 made of the titanium nitride film and the tantalum oxide film 50 are made. A DRAM information storage capacitive element C composed of a capacitive insulating film and a lower electrode 47 made of a polycrystalline silicon film (47a) is completed. The capacitive insulating film of the information storage capacitive element C is, for example, BST, STO, BaTiO ₃ (barium titanate), PbTiO ₃ (lead titanate), PZT (PbZr _X Ti _1-X O ₃ ), PLT (PbLa _X Ti _1-X O ₃ ), PLZT, and other high oxide (strong) dielectric materials made of metal oxides can also be used. The upper electrode 51 can also be formed using a conductive material other than titanium nitride, such as tungsten. Furthermore, the information storage capacitor element C may have a shape other than those described above, for example, a fin shape.

  Next, as shown in FIG. 27, a silicon oxide film 52 having a thickness of about 600 nm is deposited on the information storage capacitor C by the CVD method, and then the silicon oxide film 52 and its lower layer are formed using the photoresist film as a mask. By etching the silicon oxide films 45 and 41, a through hole 53 is formed above the first-layer wiring 38.

  Next, as shown in FIG. 28, after the plug 54 is formed in the through hole 53, second-layer wirings 55 to 57 are formed on the silicon oxide film 52. The plug 54 is formed, for example, by depositing a titanium nitride film and a W film on the silicon oxide film 52 by a CVD method and then etching back these films to leave only the inside of the through hole 53. Further, the second-layer wirings 55 to 57 are formed on the silicon oxide film 52 by a sputtering method with a Ti film having a thickness of about 50 nm, an Al (aluminum) film having a thickness of about 500 nm, a Ti film having a thickness of about 50 nm, and the like. After sequentially depositing a titanium nitride film having a thickness of about 50 nm, these films are patterned by dry etching using a photoresist film as a mask.

  Although illustration is omitted, after that, about 1 to 2 layers of wiring are formed on the second layer wirings 55 to 57 via an interlayer insulating film, and a dense passivation film (water resistance is high) For example, the system LSI of the present embodiment is substantially completed by forming a two-layer insulating film (a silicon oxide film and a silicon nitride film deposited by plasma CVD).

  As described above, in the manufacturing method of the present embodiment, after the silicon nitride film 9 is left only in the upper part of the region where the gate electrode 8A (word line WL) of the memory cell selection MISFET for DRAM is formed, the silicon nitride film The gate electrode 8A (word line WL) and the gate electrodes 8B to 8D of the logic LSI and SRAM are simultaneously formed by etching using the mask 9 and the photoresist film 10 as a mask.

Thereby, the contact hole 32 above the gate electrode 8B of the n-channel type MISFET Qn constituting the logic LSI and the contact hole 33 above the n ⁺ -type semiconductor region 16 (source or drain) can be formed simultaneously.

  In the manufacturing method of the present embodiment, the processing of the gate electrode 8A (word line WL) having the silicon nitride film 9 on the upper portion and the processing of the gate electrodes 8B to 8D not having the silicon nitride film 9 on the upper portion are simultaneously performed. In order to do so, the increase in process can also be almost ignored.

(Embodiment 2)
A method of manufacturing a system LSI according to the present embodiment will be described in the order of steps with reference to FIGS. 29 to 39 (cross-sectional views of a semiconductor substrate). In these figures, the left region is a part of the DRAM formation region (only the memory cell is shown), the central region is a part of the logic LSI formation region (only the n-channel MISFET is shown), and the right region is A part of the SRAM formation region (only a part of each of the driving MISFET and the load MISFET is shown) is shown.

  First, as shown in FIG. 29, an element isolation trench 2, a p-type well 3 and an n-type well 4 are formed on the main surface of the semiconductor substrate 1 by the same method as in the first embodiment, and then the p-type well 3 and After forming the gate oxide film 5 on the surface of the active region of the n-type well 4, a gate electrode conductive film 8 made of a polycide film or a polymetal film is formed on the gate oxide film 5.

  Next, as shown in FIG. 30, by patterning the gate electrode conductive film 8 by etching using the photoresist film 60 as a mask, the gate electrode 8B of the n-channel type MISFET Qn of the logic LSI and the MISFET Qd for driving the SRAM are formed. A gate electrode 8C and a gate electrode 8D of the load MISFET Qp are formed. At this time, the gate electrode conductive film 8 in the DRAM forming region is not patterned and is covered with the photoresist film 60.

Next, as shown in FIG. 31, an n ^- type semiconductor region is formed in the p-type well 3 on both sides of the gate electrode 8B of the n-channel MISFET Qn by implanting an n-type impurity (for example, phosphorus) into the p-type well 3. 12 is formed, and a p ^- type semiconductor region 13 is formed in the n-type well 4 on both sides of the gate electrode 8D of the load MISFET Qp by ion-implanting a p-type impurity (for example, boron) into the n-type well 4.

Next, as shown in FIG. 32, the silicon nitride film deposited on the semiconductor substrate 1 by the CVD method is processed by anisotropic etching, so that the side wall spacer made of the silicon nitride film is formed on the side walls of the gate electrodes 8B to 8D. 15 is formed. Subsequently, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 3 in the logic LSI formation region, thereby forming the n ⁺ -type semiconductor region 16 in the p-type well 3 on both sides of the gate electrode 8B of the n-channel MISFET Qn. Form. Further, by implanting a p-type impurity (for example, boron) into the n-type well 4 in the SRAM formation region, the p ⁺ -type semiconductor region 17 is formed in the n-type well 4 on both sides of the gate electrode 8D of the load MISFET Qp. The n channel MISFET Qn of the logic LSI and the load MISFET Qp of the SRAM are completed through the steps so far.

Next, as shown in FIG. 33, the surface of the semiconductor substrate 1 is thinly etched with a hydrofluoric acid-based etchant, thereby forming the source and drain (n ⁺ type semiconductor region 16) of the n-channel type MISFET Qn and the load MISFET Qp. After exposing the source and drain (p ⁺ type semiconductor region 17), a Co silicide layer 20 is formed on the surface of the source and drain by the same method as in the first embodiment.

  Next, as shown in FIG. 34, after depositing a silicon nitride film 61 having a thickness of about 100 nm on the semiconductor substrate 1 by a CVD method, the silicon nitride film 61 is first patterned by etching using a photoresist film as a mask. Subsequently, after removing the photoresist film, the gate electrode conductive film 8 is patterned by etching using the silicon nitride film 61 as a mask, so that the gate electrode 8A (word line WL) of the memory cell selection MISFET Qs is formed in the DRAM formation region. ).

  Next, as shown in FIG. 35, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 3 in the DRAM formation region, thereby forming the n-type semiconductor region 11 constituting the source and drain of the memory cell selection MISFET Qs. Form. The DRAM memory cell selection MISFET Qs is substantially completed by the steps so far.

  Next, as shown in FIG. 36, a silicon nitride film 63 having a film thickness of about 50 nm is deposited on the semiconductor substrate 1 by the CVD method, and then a silicon oxide film having a film thickness of about 600 nm is deposited on the silicon nitride film 63 by the CVD method. After the film 22 is deposited, the surface of the silicon oxide film 22 is planarized by the CMP method.

  Next, as shown in FIG. 37, after etching the silicon oxide film 22 above the source and drain (n-type semiconductor region 11) of the memory cell selecting MISFET Qs by the same method as in the first embodiment, The silicon nitride films 63 and 61 are etched to form a contact hole 64 in one upper part of the source and drain (n-type semiconductor region 11) and a contact hole 65 in the other upper part.

  The etching of the silicon oxide film 22 is performed by etching the silicon oxide film 22 with a high selectivity with respect to the silicon nitride films 63 and 61 in order to prevent the silicon nitride films 63 and 61 under the silicon oxide film 22 from being removed. This is done using gas. The etching of the silicon nitride films 63 and 61 uses a gas that etches the silicon nitride films 63 and 61 with a high selectivity with respect to silicon or silicon oxide film in order to minimize the amount of chipping of the semiconductor substrate 1. Do it. In addition, this etching is performed under the condition that the silicon nitride film 63 is anisotropically etched so that the silicon nitride film 63 remains on the side wall of the gate electrode 8A (word line WL). As a result, the contact holes 64 and 65 are formed in self-alignment with the gate electrode 8A (word line WL).

  Next, as shown in FIG. 38, after a plug 66 made of a polycrystalline silicon film is formed in the contact holes 64 and 65 in the same manner as in the first embodiment, the film thickness is formed on the silicon oxide film 22. A silicon oxide film 27 having a thickness of about 200 nm is deposited by the CVD method, and the semiconductor substrate 1 is heat-treated in an inert gas atmosphere, thereby reducing the resistance of the n-type semiconductor region 11 (source, drain) of the MISFET Qs for memory cell selection. .

Next, as shown in FIG. 39, the silicon oxide film 27 is etched using the photoresist film as a mask, thereby forming a through hole 30 above the contact hole 64. Subsequently, the silicon oxide film 27 and the silicon oxide film 22 are etched using the photoresist film as a mask, and then the silicon nitride films 63 and 61 are etched, so that the contact hole 31 is formed in the upper portion of the wiring extraction region of the word line WL. The contact holes 32 and 33 are formed above the gate electrode 8B and the n ⁺ type semiconductor region 16 of the n-channel type MISFET Qn and straddle the gate electrode 8C of the drive MISFET Qd and the p ⁺ type semiconductor region 17 of the load MISFET Qp. A contact hole 34 is formed in the region.

  In the etching of the silicon oxide film 27 and the silicon oxide film 22, the silicon oxide films 27 and 22 are highly selected with respect to the silicon nitride films 63 and 61 in order to prevent the lower silicon nitride films 63 and 61 from being removed. This is done using a gas that etches at a ratio. In addition, the etching of the silicon nitride films 63 and 61 is performed by changing the silicon nitride films 63 and 61 into silicon or silicon oxide films in order to minimize the amount of scraping of the silicon oxide film 6 embedded in the element isolation trench 2 and the semiconductor substrate 1. Etching is performed using a gas that etches with a high selectivity. As a result, the contact hole 33 is formed in self-alignment with the element isolation trench 2. Subsequent steps are almost the same as those in the first embodiment.

As described above, in the manufacturing method of the present embodiment, the silicon nitride film 61 for forming the contact holes 64 and 65 in a self-aligned manner with respect to the gate electrode 8A (word line WL) (gate-SAC) in the DRAM formation region. 63 and the silicon nitride films 61 and 63 for forming the contact hole 33 in a self-aligned manner with respect to the element isolation trench 2 in the logic LSI formation region (L-SAC). As a result, the silicon nitride films 61 and 63 having substantially the same thickness exist above the gate electrode 8B of the n-channel type MISFET Qn and the n ⁺ type semiconductor region 16 constituting the logic LSI. The upper contact hole 32 and the upper contact hole 33 of the n ⁺ type semiconductor region 16 can be formed simultaneously.

Further, since the silicon nitride films 61 and 63 are also present above the gate electrode 8C of the driving MISFET Qd constituting the SRAM memory cell, when the contact holes 32 and 33 are formed, the gate electrode 8C of the driving MISFET Qd is formed. In addition, a contact hole 34 can be simultaneously formed in a region straddling the p ⁺ type semiconductor region 17 of the load MISFET Qp.

  Further, in the manufacturing method of the present embodiment, since the relatively thick silicon nitride films 61 and 63 exist on the upper part and the side wall of the gate electrode 8B of the n-channel type MISFET Qn constituting the logic LSI, the contact hole 33 is formed in the element. It is formed not only for the isolation trench 2 but also for the gate electrode 8B by self-alignment.

(Embodiment 3)
A method of manufacturing a system LSI according to the present embodiment will be described in the order of steps with reference to FIGS. 40 to 47 (cross-sectional views of a semiconductor substrate). In these figures, the left region is a part of the DRAM formation region (only the memory cell is shown), the central region is a part of the logic LSI formation region (only the n-channel MISFET is shown), and the right region is A part of the SRAM formation region (only a part of each of the driving MISFET and the load MISFET is shown) is shown.

  First, as shown in FIG. 40, an element isolation trench 2, a p-type well 3 and an n-type well 4 are formed in the main surface of the semiconductor substrate 1 by the same method as in the first and second embodiments, and then a p-type well. After the gate oxide film 5 is formed on the surface of the active region of the 3 and n-type wells 4, a polycrystalline silicon film 7 doped with an n-type impurity (for example, arsenic) is deposited on the gate oxide film 5 by the CVD method. When the n-channel MISFET and the p-channel MISFET have a dual gate structure, after depositing the polycrystalline silicon film 7 not containing impurities, the n-type MISFET and the p-channel MISFET are formed on the polycrystalline silicon film 7 in the n-channel MISFET formation region. An impurity (for example, arsenic) is doped, and the polycrystalline silicon film 7 in the p-channel type MISFET formation region is doped with a p-type impurity (for example, boron).

  Next, as shown in FIG. 41, by patterning the polycrystalline silicon film 7 by etching using the photoresist film 70 as a mask, the gate electrode 7B of the n channel MISFET Qn of the logic LSI and the gate of the MISFET Qd for driving the SRAM are formed. The electrode 7C and the gate electrode 7D of the load MISFET Qp are formed. At this time, the polycrystalline silicon film 7 in the DRAM formation region is not patterned and is covered with the photoresist film 70.

Next, as shown in FIG. 42, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 3, so that an n ⁻ -type semiconductor region is formed in the p-type well 3 on both sides of the gate electrode 7B of the n-channel MISFET Qn. 12 is formed, and a p ^- type semiconductor region 13 is formed in the n-type well 4 on both sides of the gate electrode 7D of the load MISFET Qp by ion-implanting a p-type impurity (for example, boron) into the n-type well 4.

Subsequently, the silicon nitride film deposited by the CVD method on the semiconductor substrate 1 is processed by anisotropic etching to form sidewall spacers 15 made of silicon nitride films on the side walls of the gate electrodes 7B to 7D, and then the logic LSI. By ion-implanting n-type impurities (for example, phosphorus) into the p-type well 3 in the formation region, n ⁺ -type semiconductor regions 16 are formed in the p-type well 3 on both sides of the gate electrode 7B of the n-channel MISFET Qn. Further, by implanting a p-type impurity (for example, boron) into the n-type well 4 in the SRAM formation region, the p ⁺ -type semiconductor region 17 is formed in the n-type well 4 on both sides of the gate electrode 7D of the load MISFET Qp.

Next, as shown in FIG. 43, the surface of the semiconductor substrate 1 is thinly etched with a hydrofluoric acid-based etching solution, and the source of the n-channel type MISFET Qn, the drain (n ⁺ type semiconductor region 16) and the source of the load MISFET Qp, After exposing the drain (p ⁺ -type semiconductor region 17), a Co film 20a is deposited on the semiconductor substrate 1 by sputtering.

Next, as shown in FIG. 44, the semiconductor substrate 1 is heat-treated. As a result, the Co silicide layer 20 is formed on the surface of the source and drain (n ⁺ type semiconductor region 16) of the n-channel type MISFET Qn and the source and drain (p ⁺ type semiconductor region 17) of the load MISFET Qp. At the same time, each surface of the polycrystalline silicon film (7) constituting the gate electrode 7B of the n-channel type MISFET Qn of the logic LSI, the gate electrode 7C of the SRAM driving MISFET Qd and the gate electrode 7D of the load MISFET Qp, and the DRAM A Co silicide layer 20 is formed on the surface of the polycrystalline silicon film 7 remaining in the formation region. Through the above steps, the n-channel MISFET Qn having the polycide structure gate electrode 7B made of the polycrystalline silicon film 7 and the Co silicide layer 20 and the polycide structure gate made of the polycrystalline silicon film 7 and the Co silicide layer 20 are formed. The load MISFET Qp having the electrode 7D is substantially completed.

  Next, as shown in FIG. 45, after depositing a silicon nitride film 61 on the semiconductor substrate 1 by the CVD method, first, the silicon nitride film 61 is patterned by etching using the photoresist film as a mask, and then the photoresist. After the film is removed, the Co silicide layer 20 and the polycrystalline silicon film 7 in the DRAM formation region are patterned by etching using the silicon nitride film 61 as a mask, whereby the gate electrode 7A (word line WL) of the memory cell selecting MISFET Qs. Form.

  Subsequently, an n-type impurity (for example, phosphorus) is ion-implanted into the p-type well 3 in the DRAM formation region, thereby forming the n-type semiconductor region 11 constituting the source and drain of the memory cell selection MISFET Qs. Through the steps up to here, a MISFET Qs for DRAM memory cell selection having a polycide structure gate electrode 7A composed of the polycrystalline silicon film 7 and the Co silicide layer 20 is substantially completed.

  Next, as shown in FIG. 46, a silicon nitride film 63 is deposited on the semiconductor substrate 1 by a CVD method, and then a silicon oxide film 22 is deposited on the silicon nitride film 63 by a CVD method. The surface of 22 is flattened by the CMP method.

Next, as shown in FIG. 47, contact holes 64 and 65 are formed above the source and drain (n-type semiconductor region 11) of the memory cell selection MISFET Qs by the same method as in the second embodiment, and then A plug 66 made of a polycrystalline silicon film is formed inside the silicon oxide film 27, the silicon oxide film 27 and the silicon oxide film 22 are etched using the photoresist film as a mask, and the silicon nitride films 63 and 61 are further etched. A contact hole 31 is formed above the wiring extraction region of the line WL, a gate electrode 8B of the n-channel type MISFET Qn and contact holes 32 and 33 are formed above the n ⁺ type semiconductor region 16, and a gate electrode 8C of the driving MISFET Qd. and co in the region spanning the load MISFETQp the ^{p +} -type semiconductor region 17 Forming a contact hole 34. Subsequent steps are almost the same as those in the second embodiment.

According to the present embodiment, the same effects as those of the second embodiment can be obtained, the formation of the polycide structure gate electrodes 7A to 7D, and the source and drain (n ⁺ type semiconductor region 16, p ⁺ type semiconductor region). 17) Since the surface silicidation is simultaneously performed, the process can be simplified.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention can be used for manufacturing a semiconductor integrated circuit device in which a DRAM and a logic LSI are mixedly mounted.

1 is an equivalent circuit diagram of a DRAM that constitutes a part of a system LSI according to a first embodiment of the present invention. 1 is an equivalent circuit diagram of an SRAM that constitutes a part of a system LSI that is Embodiment 1 of the present invention; FIG. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 1 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 2 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 3 of this invention. It is principal part sectional drawing of the semiconductor substrate which shows the manufacturing method of the system LSI which is Embodiment 3 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation groove 3 P-type well 4 N-type well 5 Gate oxide film 6 Silicon oxide film 7 Polycrystalline silicon film 7A-7D Gate electrode 8 Conductive film 8A-8D for gate electrodes Gate electrode 9 Silicon nitride film 10 Photo Resist film 11 n-type semiconductor region 12 n ⁻ type semiconductor region 13 p ⁻ type semiconductor region 15 Side wall spacer 16 n ⁺ type semiconductor region 17 p ⁺ type semiconductor region 19 Silicon oxide film 20a Co film 20 Co silicide layer 21 Silicon nitride film 22 Silicon oxide film 23 Photoresist film 24, 25 Contact hole 26 Plug 28 Silicon oxide film 30 Through hole 31-34 Contact hole 36 Plug 37-40 Wiring 41 Silicon oxide film 42 Through hole 43 Plug 44 Silicon nitride film 45 Silicon oxide film 46 Groove 47 Lower part Electrode 47a Polycrystalline silicon film 48 Spin-on glass film 49 Photoresist film 50 Tantalum oxide film 51 Upper electrode 52 Silicon oxide film 53 Through hole 54 Plug 55-57 Wiring 60 Photoresist film 61 Silicon nitride film 63 Silicon nitride film 64, 65 Contact Hole 66 Plug 70 Photoresist film BL Bit line C Information storage capacitor MC Memory cell Qn n-channel MISFET
MISFET for Qp load
Qs MISFET for memory cell selection
SA sense amplifier WD word driver WL word line

Claims (1)

A semiconductor integrated circuit having a first memory cell region in which DRAM memory cells in which a first MISFET and a capacitor are connected in series are arranged in a matrix, and a second circuit region in which a plurality of second MISFETs constituting a logic LSI are formed. A circuit device manufacturing method comprising:
(A) forming a gate electrode of the first MISFET in which a first insulating layer is selectively formed in the first memory cell region, and forming a gate electrode of the second MISFET in the second circuit region;
(B) forming a side wall spacer on each side wall of the gate electrode of the first MISFET and the gate electrode of the second MISFET;
(C) After the step (b), a second insulating layer is formed on the main surface of the semiconductor substrate, and then a third insulating layer is formed on the second insulating layer, and then the third insulating layer is formed. Polishing and flattening,
(D) By forming a first opening in the third insulating layer and the second insulating layer covering the space region between the gate electrodes of the first MISFET in a self-aligned manner with respect to the gate electrode of the first MISFET. Exposing the surface of the source or drain of the first MISFET;
(E) forming a second opening in the third insulating layer and the second insulating layer covering an upper portion of the gate electrode of the second MISFET, thereby exposing a surface of the gate electrode of the second MISFET; Exposing a surface of the source or drain of the second MISFET by forming a third opening in the third insulating layer and the second insulating layer covering an upper portion of the source or drain of the second MISFET;
Including
In the step (a), after the first insulating layer is selectively formed on the first conductor layer in the first memory cell region, the first conductor layer is patterned to form a gate electrode of the first MISFET and A gate electrode of the second MISFET is formed;
In the step of forming the first opening, the second insulating layer is anisotropically etched after etching the third insulating layer under a condition that an etching rate of the third insulating layer with respect to the second insulating layer is increased. Etching forms a side wall spacer on the side wall of the gate electrode of the first MISFET,
In the step of forming the second and third openings, the third insulating layer is removed by etching under a condition that an etching rate of the third insulating layer with respect to the second insulating layer is increased. A method of manufacturing a semiconductor integrated circuit device.

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