JPH10254817A - Dma transfer control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a DMA transfer control system executing fast data transfer by transferring data from any starting address at a high speed and executing read and write in parallel. SOLUTION: This control system is connected with a DMA controller 10, address buses 2A, 2B, data buses 3A and 3B. These address buses 2A, 2B, data buses 3A and 3B are connected with at least memories 4A and 4B. Then the controller 10 is provided with a switching means 11 transferring data by automatically switching to optimum transferring method such as block transfer, word transfer, fraction transfer corresponding to the situation of the transfer data at any time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA transfer control system, and more particularly to a DMA transfer control system for transmitting and receiving data between devices independently of a processor only by a start process from a processor in an apparatus using a microprocessor. .

2. Description of the Related Art Recently, in a control device using a communication device and a processor, data capacity has been increased, and accordingly, high-speed data transfer has become an essential issue. However, in the conventional DMA (direct memory access: data transfer without the intervention of a processor) transfer technique, a transfer method that is not very efficient in a transfer including a fraction or a transfer over two buses is performed. And the transfer speed is slow.

[0003]

2. Description of the Related Art FIG. 16 is a block diagram showing a configuration example of a conventional system. In the figure, 1 is MPU, 2A, 2B
Is an address bus, and 3A and 3B are data buses. One of these two buses is called an A bus, and the other is a B bus.

A DMA 6 is connected between the A bus and the B bus.
DMA controller (DMAC) for performing transfer control, G
1 and G2 are bidirectional buffers of an address bus whose direction is controlled by the DMA controller 4, and G3 and G4 are D
It is a bidirectional buffer of the data bus whose direction is controlled by the MA controller 4.

[0005] 4A is a memory provided on the A bus side, 5A
Is an input / output device provided on the A bus side, which is connected to the address bus 2A and the data bus 3A. 4B is B
The memories 5B provided on the bus side are input / output devices provided on the B bus side, all of which are connected to the address bus 2B and the data bus 3B.

FIG. 17 is an explanatory diagram of data transfer in a conventional system. The same components as those in FIG. 16 are denoted by the same reference numerals. In the figure, it is assumed that data having a configuration as shown in the figure is stored in the memory 4B. It is assumed that the data bus width is 4 bytes. If the minimum rectangle indicates 1-byte data, and 4 bytes constitute 1 word, the first to are fractional data less than 1 word.

In the conventional system, these fractional data are stored one by one by the DMAC 6 in the counterpart memory 4A.
Is DMA-transferred, and then the first one-word data is DMA-transferred. In this method, transfer is performed in byte units except for word transfer.

The conventional transfer method will be described in more detail. FIG. 18 is a diagram illustrating a configuration example of transfer data. ○ 1
(Represented in this manner; the same applies hereinafter) to data of ○ 12. １，1, ２，2, ３3 are fraction data, ４4 to １１11 are word data, and １２12 is 1-byte fraction data.

FIG. 19 shows the first data transfer of the conventional system.
FIG. 3 is a diagram showing an example in which data is transferred in byte units except for word transfer (Japanese Patent Application Laid-Open No. 64-76356).
The bus arbitration mode is set for the transfer of one data to the transfer of the next data. That is, the fraction data of ○ 1 to ○ 3
Is transferred one byte at a time, the subsequent word data is transferred in units of words from ４4 to １１11, and finally, 1-byte fraction data １２12 is transferred.

FIG. 20 shows the second data transfer of the conventional system.
FIG. 3 is a diagram showing an example (Japanese Patent Laid-Open No. 6-266612). In this example, fractional 1-word data is fetched, temporarily converted to 4-byte data, and transferred. Then, the data of １〜1 to ３3 are transferred collectively, then the data of one word width is transferred to ４4 to １１11, and the last fraction data １２12 takes one fraction word data. Then, the data is temporarily converted to 4-byte data and transferred.

FIG. 21 shows a third example of the data transfer of the conventional system.
FIG. 4 is a diagram showing an example of the
A cannot be called A (JP-A-2-024756). In this example, in the fraction transfer, only the minimum fraction data is transferred by the MPU, and the others are transferred by the DMA. When transferring fraction data, it is necessary to issue a fraction notification to the MPU from the DMAC.

When receiving the fraction notification, the MPU transfers the fraction data to the transfer destination. When the transfer of the fraction data is completed, the MPU issues a transfer completion notification to the DMAC. FIG. 22 is an explanatory diagram of a data transfer method of a conventional system spanning two buses, and shows a fourth example (Japanese Patent Laid-Open No. 1-2175).
No. 32). This example shows how to implement high-speed transfer.
This uses a single address mode of a bus direct connection type. The same components as those in FIG. 16 are denoted by the same reference numerals.

In this example, the data buses of a transfer source and a transfer destination are directly connected to each other to realize high-speed transfer. FIG.
FIG. 3 is an explanatory view of another data transfer method of the conventional system spanning two buses, showing a fifth example (Japanese Patent Laid-Open No.
No. 107666). The same components as those in FIG. 16 are denoted by the same reference numerals. This example eliminates the conventional disadvantage by having an independent pair of address buses and data buses, and enables high-speed data-to-memory direct transfer between memories.

[0014]

Among the above-mentioned conventional data transfer systems, the first example shown in FIG. 19 performs transfer in units of bytes except for word transfer, so that it takes time to transfer fractional data. Problem.

The second example shown in FIG. 20 has a problem that it takes a long time since data of a 4-byte width must be fetched once and the data of the corresponding byte must be converted, so that high-speed transfer cannot be performed. .

In the third example shown in FIG.
Since the PU is interposed, there is a problem that a time loss occurs, a processing load also increases for the MPU, and efficiency is poor.

In the case of the fourth example shown in FIG. 22, since only one pair of address information can be output, there is a problem that only transfer between the memory 4 and the input / output device 5 can be supported. In the case of the fifth example shown in FIG. 23, since the data is directly connected, the data cannot be rearranged, and there is a problem that transfer between devices having different transfer start addresses cannot be performed.

The present invention has been made in view of such a problem. First, data can be transferred at high speed from any start address, and second, by performing writing and reading in parallel, high-speed data can be obtained. It is an object of the present invention to provide a DMA transfer control system capable of performing a transfer.

[0019]

[Means for Solving the Problems]

(1) FIG. 1 is a principle block diagram of the present invention. The same components as those in FIG. 16 are denoted by the same reference numerals. In the system shown in the figure, a DMA controller 10 is connected to an address bus 2 and a data bus 3, and the address bus 2 and the data bus 3 are connected to at least a memory 4 connected to a DMA.
A transfer control system is configured.

2A and 3A are address buses and data buses on one side (A side), and 2B and 3B are the other side (B side).
Side) address bus and data bus. 11 is DMA
The switching means is provided in the controller 10 and automatically switches to an optimal transfer method as needed, such as block transfer, word transfer, and fractional transfer, and executes transfer according to the status of transfer data.

According to the structure of the present invention, the switching means 1
1 automatically switches to the optimal transfer method as needed, such as block transfer, word transfer, and fractional transfer according to the state of transfer data, and executes transfer at any time, thereby enabling high-speed data transfer from any start address. .

(2) In this case, two pairs of the address bus 2 and the data bus 3 are provided, and the DMA controller 10 performs transfer of the two buses independently.

According to the structure of the present invention, two pairs of address buses and data buses are provided, and by performing independent transfer control of each bus, writing and reading can be performed simultaneously in parallel. High-speed transfer becomes possible.

(3) The DMA controller 10
Is provided with a write counter that counts the number of data written and a read counter that counts the number of read data in order to perform a write process at the same time as reading data into the internal buffer. The transfer of the two buses is performed in parallel.

According to the configuration of the present invention, parallel processing of two buses becomes possible, and data transfer from an arbitrary transfer start address can be performed while realizing continuous high-speed data transfer at both the transfer source and the transfer destination without loss. Can be realized.

(4) Further, the DMA controller 10
And a rearranging means for rearranging the read data is provided, and the data is transferred to the writing side in a data arrangement different from the data arrangement on the read side.

According to the configuration of the present invention, data can be transferred to the writing side in a data sequence different from the data read by using the rearranging means.

[0028]

Embodiments of the present invention will be described below in detail with reference to the drawings. (A) Switching between fractional byte transfer and word / block transfer FIG. 2 is an explanatory diagram of data transfer according to the present invention. 1 are denoted by the same reference numerals. Here, it is assumed that the data stored in the transfer source memory 4B is transferred to the transfer destination memory 4A by the switching means 11 in the DMAC 10 as shown in FIG.

If one word consists of four bytes,
○ Data up to 3 is a fraction. In the present invention, instead of a byte unit, only all fractional bytes are valid,
Word transfer to which a signal indicating the effective area is added, and
○ 3 are transferred collectively. This enables high-speed transfer to a conventional system in which fractions are transferred one byte at a time.

In this case, the switching means 11
The transfer amount is calculated by hardware from the total transfer data amount, transfer source address, transfer destination address, remaining transfer byte number, and the like, and a block transferable area, a word transferable area, and one word are determined according to a transfer situation that changes as needed. Each of the fractional transfers of less than 3 bytes, which is less than 3 bytes, is identified and automatically switched to the optimal transfer mode. Here, the block transfer refers to continuously performing transfer processing using a plurality of word data as one block.

According to this embodiment, the switching means 11 automatically switches to block transfer, word transfer, and fractional transfer, and automatically switches to an optimal transfer method as needed according to the status of transfer data. , Data can be transferred at high speed from any start address.

FIG. 3 is a flowchart showing the switching control operation between fractional byte transfer and block transfer. The switching means 11 sets the total transfer data amount set at the time of transfer,
The transfer amount is calculated in hardware from the transfer source address, the transfer destination address, the remaining transfer byte number, and the like, and the optimum transfer mode is switched according to the transfer situation that changes as needed.

That is, first, the lower two bits (A30, A31) of the transfer start address value of the transfer destination are referred to, and "A30, A30,
Check if A31 = 0,0 "(S
1). The transfer data is represented by 4 bytes (32 bits) per word.

If A30, A31 = 0, 0, the data starts with a word, and if fractional data, A30, A31
There will be 1 in any of 31. A30, A31 =
It will be described in more detail that word data is obtained in the case of 0, 0 and fractional data in other cases. FIG.
Indicates a 32-bit (4-byte) memory map. As is apparent from the figure, when the transfer starts with a word, the end of the value of the start address is 0, 4, 8, C
(Hexadecimal), and the others start in the middle of the word, and this is a fraction.

Looking at the last value of this address in binary (bits A0 to A31), the result is as follows. And if it starts with a word, the lower 2 bits A3
0 and A31 are always 0 and 0. On the other hand, in the case of other fractions, the result is as follows.

[0036] Thus, there is always 1 in either A30 or A31. Therefore, when A30, A31 = 0, 0, it can be identified as a transfer at the beginning of a word, and when A30, A31 ≠ 0, 0, it can be identified as a transfer from a fraction.

When it is determined that the lower two bits are other than "0, 0", the switching means 11 generates a byte control signal (BC) for identifying the effective fraction byte position by a combination of the two bits 0/1 (see FIG. 2). S2).

There are four types of byte control signals BC corresponding to the lower two bits. The byte control signals are as follows. Lower 2 bits of transfer start address = 0,0 0000 (BC0) = 0,1 1000 (BC1) = 1,0 1100 (BC2) = 1,1 1110 (BC3) These control signals BC Is 4 bytes (1 word)
Is a signal indicating which byte data is valid.

When the byte control signal is generated,
A fractional data transfer is executed (S3). That is, the switching means 11 rearranges the data by the byte control signal so that the head of the data read from the transfer source is the head of the effective fraction data, sends out the byte control signal simultaneously with the write data, and Write data to the effective fraction byte area at once.

Next, the switching means 11 subtracts the address value by 4 (hexadecimal) from the initial set address every time the transfer is completed (S4). Thereafter, the switching means 11 outputs the lower 4 bits of the address A28, A29, A30, A31 =
It is checked whether it is 0,0,0,0 (S5).
If it is not all 0, the data is word data, and if it is all 0, it is other data (block data).

Next, the reason why word data is used when the lower 4 bits are not all 0s and block data when the lower 4 bits are all 0s will be described. As shown in FIG. 5, one block is composed of 16 bytes. In block transfer, this one block is transferred as one unit. Therefore, the start of the block transfer is 00000000000000000000000, which is the head of each block.
It is possible when the address is 20,00000000,.... This is represented by binary information as follows.

A26, A27, A28, A29, A30, A31 0000 000 = 0000 0000 000 0004 = 0000 0000 0000 0008 = 0000 0000 0000 000 C 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 From this, when the address is blockable, A28 to A
It can be seen that 31 is always in an all 0 state.

When the address values are not all 0, the switching means 11 switches to the data transfer mode (word transfer mode) in units of 4 bytes, and executes data word transfer (S6). This word transfer mode is executed up to an area where block transfer can be performed. When the transfer of one word is completed, the address value is subtracted by 4 (hexadecimal), and A28
The address values of .about.A31 are checked (S5). Word transfer continues until the address values of the lower 4 bits are all 0s.

When the lower 4 bits of the address are all 0, it is determined whether or not block transfer is possible based on the number of remaining bytes (S7). This determination is made as to whether the remaining number of bytes includes 16 bytes in units of one block. Therefore, the switching means 11 performs the following calculation.

Total transfer byte number- (block transfer start address-transfer start address) = remaining transfer number after block transfer Next, the switching unit 11 checks the remaining transfer byte number after the block transfer start address. S8).
If the number of remaining transfer bytes is larger than an integral multiple of the block unit, block transfer is executed (S9).
When the transfer of one block is completed, the number of remaining bytes is obtained (S7), and it is checked whether the number of remaining bytes is an integral multiple of the block unit (S8). Hereinafter, block transfer is continued until the number of remaining bytes does not become an integral multiple of the block unit.

When the number of remaining bytes does not become an integral multiple of the block unit, the switching means 11 checks the number of remaining bytes (S10). If the number of remaining bytes is larger than 4 bytes, word transfer is performed (S11). If the number of remaining bytes is 3 bytes or less, after generating the byte control signal BC (S12), the data of the fraction is transferred (S13). This completes the transfer of all data. If the number of remaining bytes is 0 in step S10, the transfer ends.

FIG. 6 is a diagram showing allocation of transfer data according to the present invention. The minimum rectangle in the figure is data in units of 1 byte. The first data is three-byte fraction data of ○ 1 to ○ 3, the next ○ 4 to ○ 6 are three 1-word data, the ○ 7 to ○ 10 are 16-byte block transfer data, the next ○ 11 is one word data, and the last ○ 12 is one byte of fractional data.

The following shows how the data transfer time according to the present invention is shortened compared with the conventional system. FIG. 7 is an explanatory diagram of the mode switching transfer according to the present invention.
Is a conventional example, and (b) is according to the present invention. The conventional example of (a) is the same as that shown in FIG.

In the case of the conventional example, the fraction data ○ 1 to ３3 are transferred one byte at a time, including the bus arbitration.
○ 11 is word transfer, and the remaining fraction 、 12 is fraction data transfer. On the other hand, according to the present invention, the fractions ○ 1 to ○ 3 including the bus arbitration are transferred collectively, and the following ○ 4 to ○ 6
Is word transfer, ○ 7 to １０10 are block transfer, １１11 is word transfer, and the last fraction １２12 is fraction transfer. As a result, the amount of time required for the transfer between the conventional example and the present invention is reduced by ΔT ₁ as shown in FIG.

FIG. 8 is another explanatory diagram of the mode switching transfer according to the present invention. (A) is based on the conventional example, (b)
Is according to the invention. The conventional example of (a) is the same as that shown in FIG. In the case of the conventional example, with respect to the fraction data of ○ 1 to ○ 3 which include the fractional data including the bus arbitration, a word of the fraction is read and the data rewriting operation is performed, and the batch transfer of ○ 1 to ○ 3 is performed. Perform Next ○ 4
Word transfer is performed up to ○ 11. Regarding the last fractional data １２12, one word of the fraction is read, the data is rewritten, and the data is transferred. The data transfer of the present invention shown in (b) is the same as in FIG. As a result,
The amount of time required for transfer between the conventional example and the present invention is ΔT ₂ as shown in the figure.

FIG. 9 is another explanatory diagram of the mode switching transfer according to the present invention. (A) is based on the conventional example, (b)
Is according to the invention. The conventional example of (a) is the same as that shown in FIG. In the case of the conventional example, for the fractions of ○ 1 to ○ 3 which are fraction data including the bus arbitration, a fraction notification is issued to the MPU by the DMAC,
It is a fraction transfer from the MPU.

When the MPU finishes the fraction transfer, the MPU
Send a transfer completion notice to C. DMA receiving transfer completion notification
C is a word transfer including bus arbitration for the remaining ○ 4 to １１11. For the last fraction of ○ 12, DMAC
Is notified to the MPU, and the MPU transfers the fraction data. As a result, the amount of time required for the transfer between the conventional example and the present invention is reduced by ΔT ₃ as shown in FIG.

(B) Independent transfer between two buses In the above embodiment, fractional byte transfer and word,
Block transfer has been described. Here, a case of independent transfer between two buses will be described. FIG. 10 is an explanatory diagram of the independent transfer between buses. (A) shows a conventional example, and (b) shows the present invention. In the conventional system, a two-way buffer G is provided to operate the transfer source bus and the transfer destination data independently.

According to the present invention, an address bus and a data bus are provided for each of the two buses, and while the transfer status of each bus is monitored inside the DMAC, the two buses are independently operated to write data at the transfer destination. During the processing, the data reading operation from the next transfer source can be performed in parallel, and the speed of the data transfer processing can be increased.

Further, since parallel processing is performed at the transfer source and the transfer destination, high-speed transfer can be performed at the same level as in the single address mode of the direct connection type to the bus. , It is possible to transfer data to an arbitrary transfer destination address different from the transfer source. Further, it is possible to support memory-memory transfer.

Conventionally, when a transfer is performed over two buses, a transfer method is adopted in which the transfer is performed by switching over both the address bus and the data bus. FIG. 11 is an explanatory diagram of a conventional data transfer method spanning two buses. A total of 64 buses, 32 address buses and 32 data buses, are provided. In the figure, the first hatching indicates the bus occupation time, and the second hatching indicates the bus arbitration time.

Data of device 4C (A bus data)
Is transferred to the device 4D (data on the B bus).
The MAC 6 first reads the data of the device 4C via the A bus, switches the bus, and writes the data to the device 4D via the B bus. Next, DMAC
Reads the data of the device 4C via the A bus, switches the bus, and writes the data to the device 4D via the B bus. The above operation is performed for the number of data.

In the conventional system, the data is read from the transfer source device, and the data is transferred to the transfer destination device by switching the bus. Therefore, one cycle of data transfer requires two cycles (one cycle of reading and one cycle of writing), and furthermore, a bus arbitration cycle is entered to acquire the bus right. If the bus right cannot be acquired immediately, Since the user has to wait until the bus right is acquired, a very long total transfer time is required as a whole as shown in the figure.

FIG. 12 is an explanatory diagram of the data transfer method according to the present invention over two buses. In the present invention, two pairs of an address bus and a data bus are provided, and data is simultaneously written to a buffer in the DMAC 10 while being read. As is clear from the figure, 1
After the first bus arbitration process, the data is continuously read. On the other hand, in the B bus, after the first bus arbitration process, the data is written slightly behind the A bus.

By such parallel processing, the next data can be read from the transfer source while data is being written to the transfer destination, and continuous data transfer can be performed without loss at both the transfer source and the transfer destination. Thus, a transfer speed equivalent to the single address mode in which the bus is directly connected can be realized. Also, unlike the direct bus connection type, there is no need to wait until both bus rights can be acquired for both buses, and the loss time until the start of transfer can be eliminated. Therefore, the total transfer time is smaller than that of the conventional system shown in FIG.
It is reduced by Δt.

FIG. 13 is a circuit diagram showing one embodiment of the DMA controller 10 according to the present invention. In the figure, 12 is a read counter for counting the number of read data, and 13 is a write counter for counting every time data is written. 14 is a read counter 1
2 and the output of the write counter 13,
This is a comparator that controls data reading start, stop, and restart processing according to the comparison result.

Reference numeral 15 denotes a buffer for receiving the read data, reference numeral 17 denotes a data buffer for holding the read buffer, and reference numeral 16 denotes a buffer for receiving the data read from the data buffer 17. The data buffer 17
Writing and reading are controlled by the comparator 14. The operation of the circuit thus configured will be described as follows.

Each time the read data is input via the buffer 15, the read counter 12 is updated by one. Then, the data is written to the data buffer 17.
The data held in the data buffer 17 is read, but at this time, the write counter 13 is updated by one.

The comparator 14 compares the output of the read counter 12 with the output of the write counter 13. And
It monitors the full state or the empty state of the data buffer 17 and controls the start, stop and restart processing of data reading. That is, if there is data in the data buffer 17, the comparator 14 executes reading, and if there is free space, executes the writing.

According to this embodiment, parallel processing of two buses is possible, and data transfer from an arbitrary transfer start address is realized while realizing continuous high-speed data transfer at both the transfer source and the transfer destination without loss. Can be realized.

FIG. 14 is an explanatory diagram of data rearrangement transfer according to the present invention. In the DMAC 10, reference numeral 18 denotes a rearranging means for rearranging the order of the read data and outputting the rearranged data. When two pairs of address buses and data buses are provided, the address buses are individually provided, so that transfer source / destination address information can be output to each of the two address buses independently. This enables direct data transfer between devices such as memories that require addresses.

Further, since the rearrangement means 18 enables rearrangement of data inside the DMAC, data can be transferred even if the data structure of the transfer source and the transfer destination is different. In other words, data can be transferred to the writing side in a data arrangement different from the data read using the rearrangement means 18.

FIG. 15 is a circuit diagram showing an embodiment of the sorting means 18 according to the present invention. In the figure, 20
Is a read route control unit for switching read data, 2
Reference numeral 1 denotes a write path control unit that switches write data. Reference numeral 22 denotes an 8-bit flip-flop that latches 32-bit data in the depth direction. The flip-flop 22 needs a capacity (depth) enough to hold all the read data.

Reference numeral 23 denotes a read counter provided in byte units, and reference numeral 24 denotes a write counter provided in byte units. In this embodiment, since the data width is 32 bits (4 bytes), four data widths are provided. The source counter start address value is input to the read counter 23 as an initial value, and the destination start address value is input to the write counter 24 as an initial value. The arrangement of the read data and the arrangement of the write data are shown in FIG.
Shall be the same as shown in FIG.

The output of each read counter 23 is the write enable (W) of the corresponding flip-flop 22.
E), and the output of each write counter 24 is connected to the out enable (OE) of the corresponding flip-flop 22. The operation of the circuit thus configured will be described as follows.

The read data is (A, B, C),
(D, E, F, G) are input to the reading method control unit 20 in this order. The read route control unit 20 receives the transfer source start address and switches the route of the input 4-byte data. Then, the read route control unit 20 outputs the data whose route has been switched, and writes the data into the flip-flop 22 at the address designated by the read counter 23. By repeating the write operation, all read data is written to the flip-flop 22.

On the other hand, the output of the write counter 24 is also input to the flip-flop 22, and the flip-flop 22 specified by the write counter 24 is also input.
Is read out and enters the write route control unit 21.
The transfer destination start address is input to the write route control unit 21, and the route is switched according to this address. As a result, first, only the data A is read, and then the data (B, C, D, E) is read.

As described above, according to this embodiment,
The data can be transferred to the writing side in a data sequence different from the data read using the rearranging means.

[0074]

As described in detail above, according to the present invention, (1) a DMA controller is connected to an address bus and a data bus, and at least a memory is connected to the address bus and the data bus. In the transfer control system, the DMA controller performs a block transfer, a word transfer, and a fraction transfer according to a state of transfer data.
By providing switching means for automatically switching to an optimum transfer method at any time and executing transfer, the switch means can perform block transfer, word transfer, and word transfer in accordance with the status of transfer data.
By automatically performing the fraction transfer and the transfer method that is automatically switched to the optimum transfer method at any time, data can be transferred at a high speed from any start address.

(2) In this case, two pairs of the address bus 2 and the data bus are provided, and the DMA controller performs the transfer of the two buses independently, whereby
By having a pair of address bus and data bus, and performing independent transfer control of each bus, writing and reading can be performed simultaneously in parallel, and high-speed data transfer becomes possible.

(3) Further, the DMA controller comprises:
A write counter for counting the number of data writes and a read counter for counting the number of read data are provided for reading data into the internal buffer and simultaneously performing a write process. By performing bus transfer in parallel, two buses can be processed in parallel, realizing data transfer from any transfer start address while achieving continuous high-speed data transfer at both the transfer source and transfer destination without loss. can do.

(4) Further, a rearranging means for rearranging read data is provided in the DMA controller,
By transferring data to the writing side in a data arrangement different from the data arrangement on the reading side, it is possible to transfer data to the writing side in a data arrangement different from the data read using the rearranging means.

As described above, according to the present invention, first, data can be transferred at high speed from any start address, and second, DMA can be transferred at high speed by performing writing and reading in parallel. A transfer control system can be provided.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is an explanatory diagram of data transfer according to the present invention.

FIG. 3 is a flowchart illustrating a switching control operation of fractional byte transfer and block transfer.

FIG. 4 is a diagram showing a map of a 32-bit (4-byte) memory.

FIG. 5 is a diagram showing another map of a 32-bit (4 byte) memory.

FIG. 6 is a diagram showing allocation of transfer data according to the present invention.

FIG. 7 is an explanatory diagram of mode switching transfer according to the present invention.

FIG. 8 is another explanatory diagram of the mode switching transfer according to the present invention.

FIG. 9 is another explanatory diagram of the mode switching transfer according to the present invention.

FIG. 10 is an explanatory diagram of an independent transfer between buses.

FIG. 11 is an explanatory diagram of a conventional data transfer method spanning two buses.

FIG. 12 is an explanatory diagram of a data transfer method according to the present invention that spans between two buses.

FIG. 13 is a circuit diagram showing one embodiment of a DMA controller according to the present invention.

FIG. 14 is an explanatory diagram of data rearrangement transfer according to the present invention.

FIG. 15 is a circuit diagram showing an embodiment of the rearranging means according to the present invention.

FIG. 16 is a block diagram showing a configuration example of a conventional system.

FIG. 17 is an explanatory diagram of data transfer in a conventional system.

FIG. 18 is a diagram illustrating a configuration example of transfer data.

FIG. 19 is a diagram showing a first example of data transfer in a conventional system.

FIG. 20 is a diagram showing a second example of data transfer of the conventional system.

FIG. 21 is a diagram showing a third example of data transfer of the conventional system.

FIG. 22 is a diagram illustrating a fourth example of data transfer of the conventional system.

FIG. 23 is a diagram showing a fifth example of data transfer of the conventional system.

[Explanation of symbols]

 1 MPU 2A Address bus 2B Address bus 3A Data bus 3B Data bus 4A Memory 4B Memory 5A I / O device 5B I / O device 10 DMA controller 11 Switching means

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Shibagaki tax 2-2-1 Momichihama, Sawara-ku, Fukuoka, Fukuoka Prefecture Inside Fujitsu Kyushu Communication Systems Co., Ltd. (72) Inventor Kazuyuki Nakamura 2 Momodohama, Sawara-ku, Fukuoka Chome 2-1 Fujitsu Kyushu Communication System Co., Ltd.

Claims (4)

[Claims] 1. A DMA transfer control system in which a DMA controller is connected to an address bus and a data bus, and at least a memory is connected to the address bus and the data bus. A DMA transfer control system comprising a switching means for automatically performing a block transfer, a word transfer, and a fractional transfer, and automatically performing an appropriate transfer method as needed. 2. The DMA transfer control system according to claim 1, wherein the address bus and the data bus are provided in two pairs, and the DMA controller performs transfer of the two buses independently. 3. The DMA controller is provided with a write counter for counting the number of data written and a read counter for counting the number of read data in order to perform write processing while reading data into an internal buffer of the DMA controller. 3. The DMA transfer control system according to claim 2, wherein the transfer of the two buses is processed in parallel by a comparison between the read and the read counter. 4. The DMA controller according to claim 2, further comprising a rearranging means for rearranging the read data, wherein the data is transferred to the write side in a data arrangement different from the data arrangement on the read side. DMA described
Transfer control system.