JPS62212745A - Data processor having buffer memory - Google Patents

Abstract

PURPOSE:To increase the storing speed of data by using an instruction arithmetic processing part to deliver data onto a data bus at a part where data are stored and then using a buffer memory to deliver data to the other part of the data bus. CONSTITUTION:In a store-through system, the data delivered to data buses 4-1 and 4-3 from an instruction arithmetic processing part 1 are stored in main memory store registers 13-1-13-4 within a main memory interface part 2. While the data delivered to data buses 4-2 and 4-4 by the bytes 3-2 and 3-4 are also stored in the registers 13-1-13-4. These data are sent to a main memory and a main memory control part 5 via a main memory bus 6 and stored there. Then the data are delivered to those data buses from the part 1 and a buffer memory 3 and then merged on these data buses. Thus data are stored in a part of the access unit of the memory 3. In such a way, the data storing speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device having buffer storage.

[Conventional technology]

When implementing a store operation for only a portion of the m accesses of the buffer memory, it may be necessary to merge the data to be stored and the read data from the buffer memory for the reasons described below.

The first reason is that, as shown in Japanese Patent Publication No. 54-11220, data to be stored and read data from buffer storage are merged, and the merged data is sent to the main memory. This is because the device wants to make a store request to the storage unit for all parts within an access unit. This eliminates the need for the main memory section to once read data from the main memory and then write the merged data of the read data and the data sent by the processing device to the main memory. Therefore, the throughput (amount of data that can be accessed within a unit time) of the main memory can be improved.

The second reason is that when Hamming code bits are added to buffer storage to increase the reliability of the processing unit,
This is to generate a Hamming code using read data from the buffer storage and data to be stored.

Conventionally, when merging data to be stored and read data from buffer storage as shown above,
Generally, the merging operation is accomplished by first reading data from a buffer storage, then merging the read data with the data to be stored, and then performing a store operation on the buffer storage and main storage.

[Problem that the invention seeks to solve]

The above method is disadvantageous in that it requires extra time to read the data from the buffer storage, ultimately increasing the average instruction processing time of the processing unit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device that can perform a store operation at high speed.

[Means for solving problems]

In the present invention, when storing only a portion of the access unit of buffer storage, the instruction processing unit outputs data on the data bus for the portion to be stored, and outputs data to the remaining portion of the data bus. stores by outputting data from the buffer memory.

[Effect]

In the present invention, store data to the buffer memory is merged on the data bus, so that the store operation for a portion of the access unit of the buffer memory is accelerated.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In the illustrated example, the access unit for buffer storage and the data bus width are 4 bytes.

As shown in the time chart of FIG. 1, when storing, for example, in the portion corresponding to byte O and byte 2 of the buffer memory (2-1.2-3 in FIG. 1), the instruction processing unit 1 Of the instruction arithmetic processing section data output control lines 9-1 to 9-4 which are the output of the control section 12, the line 9-1.9-3 corresponding to byte 0.2 becomes '1'. The store data set in the buffer store registers 7-1 and 7-3 in the instruction arithmetic processing unit 1, that is, the part corresponding to byte 0.2, is
Driver 8-1.8- by the above control line 9-1.9-3
Byte 0.3 is output via data bus 4-1.4-3. Buffer storage output control lines 10-1 to 10-4 are inverted signals of the lines 9-1 to 9-4. In the example of FIG. 2, lines 10-2, 10-4 become 11', and read data from bytes 3-2, 3-4 of buffer storage 3 is output to data buses 4-2 and 4-4.

As shown in the time chart of FIG. 2, data output from the instruction processing unit 1 and bytes 3-2, 3-4 of the buffer storage to the data bus is performed simultaneously. Of the buffer storage store control lines 11-1 to 11-4, bytes 0.
2 corresponds to [11-1. Stored in

In the so-called store-through method, in which a store operation is performed in the buffer memory 3 and also in the main memory at all times, the following operations are further performed. For data bus 4-1.4-3, the instruction arithmetic processing unit 1 outputs data, and for data bus 4-2.4-4, byte 3-2.3-4 of buffer storage 3 outputs data to the data bus. The data is taken into the main memory store data registers 13-1 to 13-4 in the main memory interface section 2, and sent to the main memory and main memory control section 5 via the main memory bus 6, where a store operation is performed on the main memory. .

As shown in the time chart of FIG. 2, in the present invention, data is output from the instruction arithmetic processing unit 1 to the data bus, and data is output from the buffer storage 3 to the data bus. In order to merge data, when performing a store operation for a part of the access unit of buffer memory, the store operation can be performed faster than a method in which data is read from buffer memory and then stored again in buffer memory. .

[Effect of invention]

According to the present invention, when an instruction is given to store a part of the buffer memory in an access unit, reading data from the buffer memory and outputting data from the instruction processing unit to the data bus are performed simultaneously rather than sequentially. Since data is merged on the bus, the store operation can be realized at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a time chart of a store operation to explain FIG. 1. 1... Instruction arithmetic processing unit, 2... Main memory interface unit, 3... Buffer storage, 3-1 to 3-4...
Buffer storage bytes 0 to 3.4-1 to 4-4...Data bus bytes O to 3, 5...Main memory and main memory control unit, 6...Main memory bus, 7-1 to 7- 4...Buffer store register byte O~3.8-1~8-4...Driver byte O~3.9-1~9-4...Instruction arithmetic processing section data output control line byte O~3. 10-1 to 10-4
...Buffer storage data output control line. 11-1 to 11-4...Buffer storage store control line bytes 0 to 3, 12...Control unit, 13-1 to 13-4.
・Main memory store register pi 1-0~3゜1z 2nd port

Claims (1)

[Claims] 1. It is equipped with an instruction processing unit, a buffer memory, and a data bus that connects these two, and when the instruction processing unit performs a store operation on a part of the access unit of the buffer memory, when the instruction processing unit is instructed to store, A data processing device characterized in that the instruction arithmetic processing unit outputs store data on a data bus for a portion, and that the buffer storage outputs store data on a data bus for a portion for which storage is not instructed.