JPH0377459U - - Google Patents
Info
- Publication number
- JPH0377459U JPH0377459U JP1990125696U JP12569690U JPH0377459U JP H0377459 U JPH0377459 U JP H0377459U JP 1990125696 U JP1990125696 U JP 1990125696U JP 12569690 U JP12569690 U JP 12569690U JP H0377459 U JPH0377459 U JP H0377459U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- package substrate
- flat part
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000004020 conductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims 4
- 239000000463 material Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Multi-Conductor Connections (AREA)
- Connections Arranged To Contact A Plurality Of Conductors (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第１図は本考案の半導体用パツケージ基板の斜
視図、第２図及び第３図のａ〜ｆは、導体ピンが
嵌入固着されたプリント配線板の平面図、第４図
及び第６図は導体ピンの平面図、第５図及び第７
図は導体ピンが嵌入固着されたプリント配線板の
縦断面図、第８図はスタンドオフピンの縦断面図
、第９図は本考案の半導体用パツケージ基板から
なるパツケージをマザーボードに実装した状態の
縦断面図を示す。
１……導体ピン、２……プリント配線板、３…
…スルーホール、９……半導体素子、１４……は
んだ、１５……凸状扁平部、１６……凹状扁平部
。
FIG. 1 is a perspective view of a semiconductor package board of the present invention, FIGS. 2 and 3 a to f are plan views of a printed wiring board into which conductor pins are inserted and fixed, and FIGS. 4 and 6 are Top view of conductor pin, Figures 5 and 7
The figure is a vertical cross-sectional view of a printed wiring board with conductor pins inserted and fixed, Figure 8 is a vertical cross-sectional view of standoff pins, and Figure 9 is a diagram of a package made of the semiconductor package substrate of the present invention mounted on a motherboard. A vertical cross-sectional view is shown. 1... Conductor pin, 2... Printed wiring board, 3...
...Through hole, 9...Semiconductor element, 14...Solder, 15...Convex flat part, 16...Concave flat part.
Claims (1)
金属線の直径よりも幅の広い扁平部を持つ導体ピ
ンとよりなると共に、該導体ピンの扁平部が上記
プリント配線板に設けられた該扁平部の幅よりも
小さい直径のスルーホールに嵌入固着されている
半導体用パツケージ基板であつて、 かつ上記導体ピンにおける扁平部の扁平面の延
長線は、隣接する他の導体ピンにおける扁平部の
扁平面の延長線と、互いに略直交するように配置
してあることを特徴とする半導体用パツケージ基
板。 ２ 前記導体ピンは、扁平部の下部近辺に金属線
の直径より大きい鍔が形成されており、該鍔がプ
リント配線板の表面に係止されていることを特徴
とする実用新案登録請求の範囲第１項記載の半導
体用パツケージ基板。 ３ 前記鍔の下部に別の鍔が形成されていること
を特徴とする実用新案登録請求の範囲第１項記載
の半導体用パツケージ基板。 ４ 前記別の鍔の形状は、当該半導体用パツケー
ジ基板を実装するプリント配線板の方向から見て
楕円形であることを特徴とする実用新案登録請求
の範囲第３項記載の半導体用パツケージ基板。 ５ 導体ピンの両端が曲面を形成していることを
特徴とする実用新案登録請求の範囲第１項記載の
半導体用パツケージ基板。 ６ 導体ピン表面は、プリント配線板の表面に形
成された回路表面の金属層とは異なる別の金属層
で被覆されていることを特徴とする実用新案登録
請求の範囲第１項記載の半導体用パツケージ基板
。 ７ 半導体用パツケージ基板の形状は、ピングリ
ツトアレイ状であることを特徴とする実用新案登
録請求の範囲第１項、第２項、第３項、第４項、
第５項或いは第６項記載の半導体用パツケージ基
板。[Scope of claims for utility model registration] 1. A printed wiring board made of organic resin material,
It consists of a conductor pin having a flat part wider than the diameter of the metal wire, and the flat part of the conductor pin is fitted and fixed into a through hole provided in the printed wiring board and having a diameter smaller than the width of the flat part. a semiconductor package substrate, and the extension line of the flat surface of the flat part of the conductor pin is arranged so as to be substantially orthogonal to the extension line of the flat surface of the flat part of the other adjacent conductor pin. A semiconductor package substrate characterized by: 2. The scope of the utility model registration claim, characterized in that the conductor pin has a flange larger in diameter than the metal wire formed near the bottom of the flat part, and the flange is latched to the surface of the printed wiring board. The semiconductor package substrate according to item 1. 3. The semiconductor package substrate according to claim 1, wherein another flange is formed below the flange. 4. The semiconductor package board according to claim 3, wherein the shape of the other flange is elliptical when viewed from the direction of the printed wiring board on which the semiconductor package board is mounted. 5. The semiconductor package substrate according to claim 1, wherein both ends of the conductor pins form curved surfaces. 6. The semiconductor device according to claim 1 of the utility model registration, characterized in that the surface of the conductor pin is covered with a metal layer different from the metal layer on the surface of the circuit formed on the surface of the printed wiring board. package board. 7 Utility model registration claims 1, 2, 3 and 4, characterized in that the semiconductor package substrate has a pin grid array shape;
A semiconductor package substrate according to item 5 or 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990125696U JPH0419806Y2 (en) | 1990-11-27 | 1990-11-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1990125696U JPH0419806Y2 (en) | 1990-11-27 | 1990-11-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0377459U true JPH0377459U (en) | 1991-08-05 |
| JPH0419806Y2 JPH0419806Y2 (en) | 1992-05-06 |
Family
ID=31673560
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1990125696U Expired JPH0419806Y2 (en) | 1990-11-27 | 1990-11-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0419806Y2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009289447A (en) * | 2008-05-27 | 2009-12-10 | Hitachi Ltd | Wiring board and electronic device equipped therewith |
| WO2019182080A1 (en) * | 2018-03-22 | 2019-09-26 | 株式会社アドヴィックス | Press-fit terminal connection device |
-
1990
- 1990-11-27 JP JP1990125696U patent/JPH0419806Y2/ja not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009289447A (en) * | 2008-05-27 | 2009-12-10 | Hitachi Ltd | Wiring board and electronic device equipped therewith |
| WO2019182080A1 (en) * | 2018-03-22 | 2019-09-26 | 株式会社アドヴィックス | Press-fit terminal connection device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0419806Y2 (en) | 1992-05-06 |
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