JPH03214243A - Microcomputer containing watchdog timer - Google Patents

Abstract

PURPOSE:To surely reset a CPU to its normal action state despite such a runaway state where the correct execution is impossible for an instructed action by inputting the abnormality detection signal of a watchdog timer as a reset signal to the CPU and at the same time storing the abnormality signal as an interruption request. CONSTITUTION:When a CPU 3 is a runaway state, an R/S flip-flop 5 is set with the abnormality detection signal of a watchdog timer 4 and stores the occurrence of an overflow of the timer 4. The abnormality signal of the timer 4 is turned into a reset signal of the CPU 3 and resets the CPU 3 in terms of hardware. When the CPU 3 starts a normal operation, an interruption of the timer 4 is immediately produced with a due interruption request stored in the flip-flop 5. Then the flip-flop 5 is cleared. Thus the CPU 3 is surely reset to its normal action with the hardware reset operation.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microcomputer with a built-in watchdog timer, and particularly to a single-chip microcomputer (hereinafter abbreviated as microcomputer) in which a CPU and peripheral hardware are mounted on one silicon chip. ) regarding microcontrollers with built-in watchdog timers.

[Conventional technology]

Conventionally, this type of microcomputer has had a configuration as shown in FIG. That is, during normal operation, the CPU 3 periodically outputs a clear signal to the watchdog timer 4, so the watchdog timer 4 does not generate an abnormality detection signal, but if the CPU 3 goes out of control for some reason, it is cleared. The signal is no longer output, and the watchdog timer 4 overflows and generates an abnormality detection signal, which generates a non-maskable interrupt INTWD to the CPU 3.
Therefore, the configuration was such that the watchdog timer interrupt was activated.

[Problem to be solved by the invention]

In the conventional microcontroller mentioned above, the watchdog timer is C
Since the CPU only generates a non-maskable interrupt to the PU, the CPU executes the instruction correctly. However, if the CPU goes out of control, the non-maskable interrupt can be used to detect the abnormality and return to normal operation.
If U is in a runaway state where it cannot correctly execute command operations, the non-maskable interrupt routine also does not operate normally, so there is a drawback that normal operation cannot be restored.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microcomputer with a built-in watchdog timer that can reliably restore the CPU to normal operation even if the CPU is in an abnormal state where it cannot correctly execute command operations.

[Means to solve problems]

A microcomputer with a built-in watchdog timer according to the present invention includes a CPU, a watchdog timer that generates an abnormality detection signal when a clear signal from the CPU is not applied within a predetermined period, and a watchdog timer that generates an abnormality detection signal as a reset signal for the CPU. means for inputting the abnormality detection signal to the CPU; storage means for storing the abnormality detection signal; means for activating a watchdog timer interrupt of the CPU based on the output of the storage means; and means for clearing the output of the storage means by an acceptance signal generated from the storage means.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. Microcomputer 1 has peripheral hardware 2゜CPU 3. Built-in watchdog timer 4. The R/S flip-flop 5 is set by the abnormality detection signal of the watchdog timer 4, and the watchdog timer interrupt request I
Generates NTWD. R/S flip-flop 5 is RE
It is cleared by the reset signal from the SET terminal and the watchdog timer interrupt acceptance signal INTWD-ACK.

In microcontroller 1 with such a configuration, C
When the PU 3 goes out of control and no longer outputs a clear signal, the watchdog timer 4 overflows and outputs an abnormality detection signal. The R/S flip-flop 5 is set by this abnormality detection signal and stores that the watchdog timer 4 has overflowed.

Furthermore, the abnormality detection signal becomes a reset signal for CPU3.
Reset PU3 hardware-wise. Then, when the CPU 3 starts normal operation after the reset operation is completed, R
The watchdog timer interrupt request stored in the /S flip-flop 5 immediately generates a watchdog timer interrupt, and the watchdog timer interrupt routine is executed. If the watchdog timer interrupt is accepted, the watchdog interrupt is accepted using the signal I NTW.
D-ACK is generated and R/S flip-flop 5 is cleared.

Through the above operations, the CPU 3 will reliably return to normal operation by a hardware reset, and the watchdog timer interrupt will be activated after that, so even if the CPU is in a runaway state where it cannot execute commands correctly, the watchdog timer will be activated. The interrupt routine is guaranteed to operate normally.

The reason why the R/S flip-flop 5 is cleared by a reset signal from the external RESET terminal is that in the case of a system reset from the RESET terminal, generation of a watchdog timer interrupt is prohibited and the initial routine is always executed. This is so that the program can be executed from

FIG. 2 is a block diagram for explaining a second embodiment of the present invention. The difference from the first embodiment is in flag 6. This flag 6 is a flag for selecting whether or not the abnormality detection signal of the watchdog timer 4 is input as a reset signal of the CPU 3.

If the flag 6 is "0°", the CPU 3 will not be reset by the overflow of the watchdog timer 4, similar to a conventional microcomputer.If the flag 6 is 1', the operation will be exactly the same as in the first embodiment. .

By adding the flag 6, the watchdog timer 4 can be used not as a watchdog timer but as a normal interval timer interrupt, resulting in a configuration with a wider range of applications.

The flag 6 is included in the watchdog timer 4 as part of a control register that selects the overflow time of the watchdog timer 4 and instructs it to start. Therefore, it is more effective if the configuration is configured so that writing can be performed only once. FIG. 3 shows an example of a configuration in which flag 6 is part of the control register. Address decoder 10 decodes data on address bus 8 and outputs a decode signal when the address of control register 15 is output on address bus 8.

The R/S flip-flop 12 is set by the AND gate 11 of the decode signal and the write signal WR, and is cleared by the system reset signal. The D flip-flop 13 receives the output of the R/S flip-flop 12 and uses an inverted signal of the write signal WR as a latch clock. Further, the D flip processor 113 is cleared by a system reset signal.

A control register 15 including a flag 6 receives an address decode signal from an address decoder 10, an inverted output of a D flip-flop 13, and an AND gate 1 of a write signal WR.
The control register 15, which is a D flip-flop which inputs the data on the data bus 9, is cleared by the system reset signal like the other flip-flops.

The operation will be explained below. The R/S flip-flop 12 is cleared by the system reset signal from the RESET terminal, and the D flip-flop 13, which outputs 0'', is also cleared by the system reset signal. Since the output is 0, the inverted output of the D flip-flop 13 maintains the state of 1°. The control register 15 is also cleared by the system reset signal and holds the initial value.

When a write command to the control register 15 is executed from such an initial state, the output of the address decoder 10 becomes active and the inverted output of the D flip-flop 13 becomes 1.
``'', the AND gate 14 becomes active in synchronization with the write signal WR, and is input as a latch clock to the control register]5, and writing to the control register 15 is performed.At the same time, the R/S flip-flop 12 also receives the write signal. Set in synchronization with WR.

Since the D flip-flop 13 uses the inverted signal of the write signal WR as a latch clock, it does not change during the period of the write signal WR, and when the write signal WR ends, the new output state of the R/S flip-flop 12 is "1". '' and outputs ``0'' as the inverted output. As a result,
Since one of the inputs of the AND gate 14 is always "0", the AND gate 14 becomes active from then on and the data in the control register 15 is no longer rewritten.

FIG. 4 is a block diagram of a third embodiment of the present invention. In the second embodiment shown in FIG.
The configuration is such that it is added as a reset signal.

That is, this flag 7 is a flag for selecting whether or not the abnormality detection signal of the watchdog timer 4 is input as a reset signal of the peripheral hardware 2. If the flag 7 is "0", the peripheral hardware 2 will not be reset by the overflow of the watchdog timer 4, as in the second embodiment.If the flag 7 is "1", the peripheral hardware 2 will not be reset by the overflow of the watchdog timer 4. The peripheral hardware 2 is reset by the overflow.

If you set flag 7 to 1'' and reset peripheral hardware 2, you can more reliably restore the entire microcontroller 1 to normal operation, but on the other hand, resetting peripheral hardware may turn off all output ports or turn off the crystal oscillation. For several milliseconds after the circuit that counts the oscillation stabilization time operates, the CPU3
Inconveniences such as stopping operation may also occur. Therefore, whether or not the peripheral hardware 2 should be reset by the overflow of the watchdog timer 4 depends on the application device. Therefore, flag 7 is used as in this embodiment.
A configuration that can be selected according to the following is effective.

It is more effective if the flag 7 has the same configuration as that described in the second embodiment and is incorporated into the control register in the watchdog timer 4 so that it can be written only once after the system is reset.

〔Effect of the invention〕

As explained above, the present invention inputs the abnormality detection signal of the watchdog timer as a reset signal to the CPU and also stores it as an interrupt request. This has the effect of allowing the CPU to return to normal operation and then detecting the occurrence of a runaway state by executing a watchdog timer interrupt.

Also, the second. As shown in the third embodiment, by providing a selection flag for inputting the abnormality detection signal of the watchdog timer to the CPU or peripheral hardware, a practical built-in watchdog timer with a wider range of applications can be realized. We can provide microcontrollers.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining a first embodiment of the present invention, FIG. 2 is a block diagram for explaining a second embodiment of the present invention, and FIG. 3 is a control register for a watchdog timer. FIG. 4 is a block diagram for explaining a third embodiment of the present invention, and FIG. 5 is a block diagram for explaining a conventional example. 1...Single-chip microcomputer, 2.
... Peripheral hardware, 3... CPU, 4... Watchdog timer, 5... R/S flip-flop,
6.7...Flag, 8...Address bus, 9...
Data bus, 10...Address decoder, 11,1.
4...AND gate, 12...R/S flip-flop, 13...D flip-flop, 15...control register.

Claims (1)

[Claims] 1. A CPU, a watchdog timer that generates an abnormality detection signal when a clear signal from the CPU is not applied within a predetermined period, and the abnormality detection signal is input to the CPU as a reset signal for the CPU. storage means for storing the abnormality detection signal; means for activating a watchdog timer interrupt of the CPU based on the output of the storage means; A microcomputer with a built-in watchdog timer, further comprising means for clearing the output of the storage means in response to an acceptance signal. 2. The microcomputer with a built-in watchdog timer according to claim 1, wherein the abnormality detection signal of the watchdog timer is inputted as a reset signal for peripheral hardware. 3. The abnormality detection signal of the watchdog timer is
2. The microcomputer with a built-in watchdog timer according to claim 1, further comprising means for selecting whether or not to input the signal as a reset signal for the PU. 4. A microcomputer with a built-in watchdog timer according to claim 3, wherein the selection means is configured to perform a write operation only once after the system is reset by a reset signal from an external reset terminal. microcomputer. 5. The microcomputer with a built-in watchdog timer according to claim 2, further comprising a selection means for inputting the abnormality detection signal of the watchdog timer as a reset signal for the peripheral hardware. 6. The microcomputer with a built-in watchdog timer according to claim 5, wherein the selection means is configured such that the write operation is performed only once after the system is reset by a reset signal from an external reset terminal. microcomputer.