JP2024134199A - Semiconductor integrated circuit device - Google Patents

Abstract

To provide a semiconductor integrated circuit device capable of protecting an internal or external circuit from electromagnetic noise intruding into the semiconductor integrated circuit device.SOLUTION: There is provided a semiconductor integrated circuit device 100, 200, 300 or 400 comprising: a noise detection signal generation circuit 20 configured to generate a detection signal upon detection of noise; and a protection circuit configured to put a target circuit into a state for avoiding influence of noise in response to the detection signal generated by the noise detection signal generation circuit 20.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor integrated circuit device that has a function for reducing malfunctions caused by the intrusion of electromagnetic noise.

To prevent the intrusion of electromagnetic noise, conventional semiconductor integrated circuit devices are fitted with filters such as decoupling capacitors inside and outside the device, or an electromagnetic shield is implemented to allow the electromagnetic noise to flow to ground. This reduces the amount of electromagnetic noise propagating inside the semiconductor integrated circuit device.

However, there is a limit to how much the above methods can reduce the electromagnetic noise that penetrates into a semiconductor integrated circuit device, and it is difficult to completely prevent it. Therefore, if the electromagnetic noise exceeds a certain level, it will propagate into the semiconductor integrated circuit device, causing the circuit to malfunction, potentially resulting in fatal errors such as freezing, runaway, or dangerous control that is normally prohibited.

Patent Document 1 below discloses a noise detection circuit that is provided within a semiconductor integrated circuit device. This noise detection circuit applies a bias voltage to one input of an operational amplifier, and inputs noise superimposed on the bias voltage to the other input. A latch circuit is connected to the output of the operational amplifier, and when noise enters, the latch circuit operates to detect the noise.

JP 2013-258587 A

The invention disclosed in Patent Document 1 is intended to stop the supply of voltage to the core logic when noise is detected in order to return a semiconductor integrated circuit device that has fallen into a latch-up state to a normal operating state, but is not intended to protect the semiconductor integrated circuit device from noise itself.

Therefore, in consideration of the above circumstances, the present invention aims to provide a semiconductor integrated circuit device capable of protecting an internal circuit or an external circuit from electromagnetic noise entering the semiconductor integrated circuit device.

To solve the above problem, the semiconductor integrated circuit device according to the present invention includes a noise detection signal generating circuit that generates a detection signal when noise is detected, and a protection circuit that puts the circuit to be protected into a state that avoids the effects of noise in response to the detection signal generated by the noise detection signal generating circuit.

The present invention has the effect of providing a semiconductor integrated circuit device that can protect an internal circuit or an external circuit from electromagnetic noise that enters the semiconductor integrated circuit device.

FIG. 1A is a diagram illustrating an example of a noise detection circuit according to an embodiment, and FIG. 1B is a diagram illustrating another example of a noise detection circuit according to an embodiment. FIG. 2A is a diagram showing a part of the configuration of the semiconductor integrated circuit device of the first embodiment, and FIG. 2B is a time chart showing the operation of the semiconductor integrated circuit device of FIG. 2A when detecting noise. FIG. 3A is a diagram showing a part of the configuration of a semiconductor integrated circuit device of the second embodiment, and FIG. 3B is a time chart showing the operation of the semiconductor integrated circuit device of FIG. 3A when detecting noise. FIG. 4A is a diagram showing a part of the configuration of a semiconductor integrated circuit device of the third embodiment, and FIG. 4B is a time chart showing the operation of the semiconductor integrated circuit device of FIG. 4A when detecting noise. FIG. 5 is a diagram showing a part of the configuration of a semiconductor integrated circuit device according to the fourth embodiment. FIG. 6 shows an address map matrix for data held in the backtrace memory constituting the semiconductor integrated circuit device of the fourth embodiment. FIG. 7 is a time chart showing the operation of the semiconductor integrated circuit device 400 of the fourth embodiment when detecting noise. FIG. 8 shows an image of address transition in a program memory when the CPU of the semiconductor integrated circuit device of the fourth embodiment processes a program.

The following describes in detail the embodiment of the present invention with reference to the drawings.

The semiconductor integrated circuit devices 100, 200, 300, and 400 of the first to fourth embodiments described below have a noise detection signal generating circuit 20 as shown in FIG. 1(A) and FIG. 1(B). The noise detection signal generating circuit 20 is provided inside the semiconductor integrated circuit devices 100, 200, 300, and 400, and is connected to a noise receiving unit 10A provided outside as shown in FIG. 1(A), and generates a detection signal when noise is detected. The noise receiving unit 10A in FIG. 1(A) is, for example, a conductor or a conductor wound in a loop shape, with capacitors connected to both ends thereof, and outputs changes in electromagnetic waves as changes in current. Alternatively, the noise detection signal generating circuit 20 may be connected to a known electromagnetic wave detector 10B as shown in FIG. 1(B). The electromagnetic wave detector 10B may be a detector that detects noise by comparing the fluctuation of the voltage value of the power supply voltage with a reference voltage using a comparator, or may be another external detector. In this case, the electromagnetic wave detector 10B generates and outputs a detection level signal according to the magnitude of the detected electromagnetic wave. The detection level signal may be a digital signal or an analog signal.

The noise detection signal generating circuit 20, which is common to the first to fourth embodiments described below, outputs a noise detection signal when the output from the noise receiving unit 10A in FIG. 1A or the output from the electromagnetic wave detector 10B in FIG. 1B exceeds a predetermined value. The noise detection signal is, for example, a single pulse wave, but is not limited thereto. The noise detection signal may be a plurality of pulse waves or a signal wave of a predetermined pattern. In the following description, the noise receiving unit 10A in FIG. 1A and the noise detection signal generating circuit 20, or the electromagnetic wave detector 10B in FIG. 1B and the noise detection signal generating circuit 20, are collectively referred to as a noise detection circuit 30. The semiconductor integrated circuit devices 100-400 of the first to fourth embodiments described below are provided with a protection circuit that prevents the circuit to be protected from the effects of noise in response to the detection signal generated by the noise detection circuit 30, and the protection circuit takes various forms described below.
[Embodiment 1]
2A, a semiconductor integrated circuit device 100 according to the first embodiment will be described. The semiconductor integrated circuit device 100 includes an initialization signal generating circuit 110 that generates an initialization signal for initializing the entire semiconductor integrated circuit device 100 in response to a noise detection signal output by the noise detection circuit 30. Upon receiving the noise detection signal, the initialization signal generating circuit 110 generates an initialization signal or a system reset signal for a predetermined period and supplies it to the semiconductor integrated circuit device 100.

Figure 2 (B) is a time chart showing the operation of the semiconductor integrated circuit device 100 of Figure 2 (A) when noise is detected. As shown in Figure 2 (B), when the noise detection circuit 30 detects noise, the noise detection signal is asserted (enabled). The noise detection signal is used as a trigger to cause the initialization signal generation circuit 110 to assert an initialization signal.

When the noise detection circuit 30 detects noise, a noise detection signal is asserted. This signal triggers the reset generation circuit to assert an initialization signal. Note that in FIG. 2(B), the noise detection signal is H active and the initialization signal is L active.

The initialization signal generating circuit 110 is a logic circuit that operates in synchronization with a clock signal. The period during which the initialization signal, which is the output of the initialization signal generating circuit 110, is asserted can be changed by changing the control parameters of the initialization signal generating circuit, and the expected time until the effects of noise converge is set.

According to the above-mentioned embodiment 1, the semiconductor integrated circuit device 100 is initialized by noise detection, so that it is possible to prevent the system of the semiconductor integrated circuit device 100 from being stuck in a state where a fatal error has occurred, such as freezing, running out of control, or the execution of control that is normally prohibited.

[Embodiment 2]
3A, a semiconductor integrated circuit device 200 according to the second embodiment will be described. The semiconductor integrated circuit device 200 includes a clock generating circuit 210, a clock gating control circuit 220, and a clock gate cell 230.

The clock generating circuit 210 generates a clock signal of a predetermined frequency as shown in FIG. 3(B) and supplies it to the clock gating control circuit 220 and the clock gate cell 230.

The clock gating control circuit 220 generates a clock gating signal in synchronization with the clock signal supplied from the clock generating circuit 210 in response to the noise detection signal output by the noise detection circuit 30, and outputs the clock gating signal to the clock gate cell 230. The clock gating signal is a signal for controlling the supply and stop of the system clock within the semiconductor integrated circuit device 200.

The clock gate cell 230 is a standard logic gate cell dedicated to clock gating, which receives the clock signal from the clock generation circuit 210 and the clock gating signal from the clock gating control circuit 220 and outputs the system clock.

Figure 3 (B) is a time chart showing the operation of the semiconductor integrated circuit device 200 of Figure 3 (A) when noise is detected. As shown in Figure 3 (B), when the noise detection circuit 30 detects noise, a noise detection signal is asserted. Note that this noise detection signal is a signal that is generated asynchronously and is not synchronized with the clock signal generated by the clock generation circuit 210.

The noise detection signal triggers the clock gating control circuit 220 to assert a clock gating signal synchronized with the clock signal supplied by the clock generation circuit 210.

When the clock gating signal is asserted, the clock gate cell 230 stops the supply of the system clock to the semiconductor integrated circuit device 200. On the other hand, when the clock gating signal is negated, the supply of the system clock to the semiconductor integrated circuit device 200 is resumed.

The period during which the clock gating signal is asserted by the clock gating control circuit 220 is the time expected until the effects of noise converge, and is, for example, a period of several clocks or a longer period. The period during which the clock gating signal is asserted can be adjusted by appropriately setting the control parameters of the clock gating control circuit 220.

According to the second embodiment, when noise is detected, the supply of the system clock to the circuits to be protected by the semiconductor integrated circuit device 200 or to the entire device can be temporarily stopped. This reduces the risk of the control circuit (logic) inside the semiconductor integrated circuit device 200 falling into an abnormal operating state. Furthermore, in the semiconductor integrated circuit device 200 of the second embodiment, if the supply of the system clock is resumed, processing can be continued without resetting the system. Note that, although the second embodiment describes a case where the supply of the system clock is temporarily stopped when noise is detected, the present invention is not limited to this, and the clock supply to some of the circuits to be protected by the semiconductor integrated circuit device 200 may also be temporarily stopped.

[Embodiment 3]
4A, a semiconductor integrated circuit device 300 according to the third embodiment will be described. The semiconductor integrated circuit device 300 includes an input/output terminal 310, an I/O circuit 320, an internal circuit 330, a mode switching control circuit 340, and an I/O control signal generation circuit 350.

The input/output terminal 310 outputs signals output from the I/O circuit 320 and inputs signals input from an external device to the I/O circuit 320.

The I/O circuit 320 is connected to the internal circuit 330 and the mode switching control circuit 340. In the normal mode, the I/O circuit 320 outputs a signal from the internal circuit 330 to the input/output terminal 310, or outputs an input signal from an external device input to the input/output terminal 310 to the internal circuit 330.

On the other hand, in the safety function mode, the I/O circuit 320 fixes the input/output terminals 310 to one of a low output state, a high output state, and an H-Z (high impedance) output state, depending on the I/O control signal output from the I/O control signal generation circuit 350. In other words, the input/output terminals 310 are set to a safe input/output state. Alternatively, in the safety function mode, the I/O circuit 320 may leave some of the input/output terminals 310 in the same state as in the normal mode.

The mode switching control circuit 340 is a logic circuit that operates in synchronization with the system clock of the semiconductor integrated circuit device 300, and outputs a mode switching signal in response to the noise detection signal output by the noise detection circuit 30. The mode switching signal is asserted, for example, for a predetermined period, and during the asserted period, the I/O control signal generation circuit 350 generates and outputs an I/O control signal for fixing the state of the input/output terminal 310.

The I/O control signal generation circuit 350 outputs an I/O control signal instructing which state each of the input/output terminals 310 should be fixed to in the safety function mode in response to the mode switching signal output by the mode switching control circuit 340. For example, if the input/output terminals 310 have eight terminals, the first terminal, the second terminal, ..., and the eighth terminal, the I/O control signal generation circuit 350 outputs a signal instructing that the first terminal should be fixed to a low output, the second terminal to a high output, ..., and the eighth terminal to an H-Z (high impedance) output. Note that information regarding which state the input/output terminals 310 should be fixed to in the safety function mode may be stored in a register or the like included in the I/O control signal generation circuit 350. In that case, when the mode switching control circuit 340 is asserted, the I/O control signal generation circuit 350 reads the information from the register and outputs it as an I/O control signal.

Figure 4 (B) is a time chart showing the operation of the semiconductor integrated circuit device 300 of Figure 4 (A) when noise is detected. As shown in Figure 4 (B), when the noise detection circuit 30 detects noise, a noise detection signal is asserted. The noise detection signal triggers the mode switching control circuit 340 to assert a mode switching signal for a predetermined period of time.

When the mode switching signal is asserted by the mode switching control circuit 340, the I/O control signal generation circuit 350 outputs an I/O control signal instructing which state each of the input/output terminals 310 should be fixed to in the safety function mode. Depending on the I/O control signal output from the I/O control signal generation circuit 350, the I/O circuit 320 fixes the input/output terminals 310 to either a low output state, a high output state, or an H-Z (high impedance) output state, or sets them to the same state as in normal mode. In this way, in the semiconductor integrated circuit device 300, when the mode switching signal is asserted, it becomes possible to cause the I/O circuit 320 and the input/output terminals 310 to function in the safety function mode.

The period during which the mode switching control circuit 340 is asserted can be set by changing the control parameters, and the expected time until the effects of noise converge can be set. In addition, the state of the input/output terminals 310 in the safety function mode is determined taking into consideration the safety of external devices and elements connected to each input/output terminal 310.

According to the third embodiment, when it is considered that the internal circuit 330 may temporarily become abnormal due to the influence of noise, it is possible to prevent the external device and elements connected to the input/output terminal 310 from being controlled to a dangerous state. In particular, it is possible to prevent unintended control of elements that handle high power, such as IGBTs (Insulated Gate Bipolar Transistors), as external elements.

[Embodiment 4]
A semiconductor integrated circuit device 400 according to the fourth embodiment will be described with reference to Fig. 5. The semiconductor integrated circuit device 400 is, for example, a microcomputer, and includes a central processing circuit 410 (hereinafter referred to as CPU 410), a program memory (ROM) 420, a data memory (RAM) 430, a peripheral circuit 440, an interrupt controller 450, and an emergency stop/recovery and restart controller 460. The CPU 410, the data memory 430, the peripheral circuit 440, the interrupt controller 450, and the emergency stop/recovery and restart controller 460 are each connected to an address bus and a data bus, enabling data to be exchanged between each component and the CPU 410.

The CPU 410 sequentially reads and executes the instructions stored in the program memory 420, and exchanges data with components specified by the CPU 410 via the address bus and the data bus.

The program memory 420 stores in a non-volatile manner the programs for operating the semiconductor integrated circuit device 400. The data memory 430 temporarily stores various data that are generated when the CPU 410 executes the instructions stored in the program memory 420.

The peripheral circuit 440 includes circuits such as a timer circuit and an A/D conversion circuit, in addition to SFRs (Specific Function Registers), that enhance the functionality of the semiconductor integrated circuit device 400 depending on the application of the microcontroller. The operation of these circuits is controlled by the settings of the SFRs.

When the interrupt controller 450 receives an interrupt signal from the peripheral circuit 440, it outputs an interrupt request signal to the CPU 410, and causes the CPU 410 to execute the process corresponding to the interrupt request signal with priority.

The emergency stop/recovery and restart controller 460 includes a noise detection circuit 30, a backtrace memory 470, and an internal control circuit 480, and is the main circuit that controls the emergency stop/recovery and restart process performed by the semiconductor integrated circuit device 400 when noise is detected.

The backtrace memory 470 acquires the circuit states, such as the internal signals and register values of each circuit of the semiconductor integrated circuit device 400, and stores them as data. Figure 6 shows an address map matrix for the data held by the backtrace memory 470.

Data is written to the backtrace memory 470 by monitoring the state of each circuit for each system clock or synchronous cycle of the semiconductor integrated circuit device 400, and stacking the data row by row at the top of the internal address of the backtrace memory 470. In other words, the internal signals and register values of the circuits of the CPU 410, peripheral circuit 440, and interrupt controller 450 are sequentially stored as the top row data of the internal address of the backtrace memory 470 for each system clock or synchronous cycle. When the stored data reaches or exceeds the upper limit of the memory size, the oldest data is discarded.

In addition, data is read from the backtrace memory 470 by referencing the data in the column specified by the CPU-IF address for the row indicated by the internal address specified by the internal control circuit 480.

The internal control circuit 480 transmits and receives various signals between the CPU 410 and the interrupt controller 450, and mediates control related to the backtrace memory 470 and the noise detection circuit 30. The internal control circuit 480 includes a Specific Function Register (SFR). Specifically, when the internal control circuit 480 receives a noise detection signal, it generates an emergency stop interrupt request signal after the time set in the SFR has elapsed, and outputs the signal to the CPU 410. The emergency stop interrupt request signal is the interrupt request with the highest priority level within the semiconductor integrated circuit device 400, and is accepted by the CPU 410 as a non-maskable interrupt request.

Furthermore, the internal control circuit 480 generates a recovery/resume interrupt request signal at the same time as the emergency stop request signal, and outputs the signal to the CPU 410. The recovery/resume interrupt request signal has the second highest priority level within the semiconductor integrated circuit device 400 after the emergency stop interrupt request signal, and is accepted by the CPU 410 as a non-maskable interrupt request.

When the internal control circuit 480 receives a noise detection signal, it generates an interrupt request mask signal and outputs it to the interrupt controller 450. When the interrupt controller 450 receives the interrupt request mask signal from the internal control circuit 480, it disables interrupt requests from the peripheral circuit 440 until the CPU 410 completes the emergency stop process and the recovery/restart process.

When the internal control circuit 480 receives a noise detection signal, it generates an update standby signal and outputs it to the backtrace memory 470. When the backtrace memory 470 receives the update standby signal, it stops writing the status monitor signal.

The internal control circuit 480 also generates an initialization signal in response to an instruction for recovery/restart processing that is performed after the CPU 410 completes the emergency stop processing, and outputs the signal to the backtrace memory 470. Upon receiving the initialization signal, the backtrace memory 470 copies the contents of the internal address specified by the SFR of the internal control circuit 480 to all other internal addresses.

Figure 7 is a time chart showing the operation of the semiconductor integrated circuit device 400 of Figure 5 when noise is detected. First, as a premise, under normal circumstances, the CPU 410 executes the main routine of the program recorded in the program memory 420 (normal processing). In parallel with this, internal signals of each circuit and status monitor signals indicating register values are written to the backtrace memory 470 for each synchronous cycle of the system clock or the semiconductor integrated circuit device 400.

When the noise detection circuit 30 detects noise, a noise detection signal is asserted. Next, the internal control circuit 480 uses this noise detection signal as a trigger to simultaneously assert an emergency stop interrupt request signal and a recovery/resume interrupt request signal after the time set in the SFR of the internal control circuit 480 has elapsed, and outputs them to the CPU 410. The internal control circuit 480 also uses the noise detection signal as a trigger to output an update wait signal to the backtrace memory 470, and in response, the backtrace memory 470 stops writing the status monitor signal. Furthermore, the internal control circuit 480 outputs an interrupt request mask signal to the interrupt controller 450, disabling interrupt requests from the peripheral circuit 440.

When the CPU 410 receives an emergency stop interrupt request signal, it immediately starts emergency stop processing. The emergency stop processing includes processing to determine where the emergency stop interrupt request has originated, for example, when multiple noise detection circuits 30 are provided or multiple emergency stop/recovery and restart controllers 460 are provided. This is because, when a non-maskable interrupt request is supplied from multiple request sources, it is necessary to determine the interrupt request source. Alternatively, the emergency stop processing includes processing to stop and initialize I/O circuits and peripheral circuits to set them to a safe state. Note that if the next emergency stop interrupt request signal is received while the emergency stop processing is being executed, the CPU 410 immediately accepts it and executes the emergency stop processing again from the beginning.

When the emergency stop processing is completed, the CPU 410 executes recovery and restart processing. The recovery and restart processing includes processing for setting the I/O circuit and peripheral circuits to normal states, processing for reading data from the backtrace memory 470 before the emergency stop processing, and processing for initializing the backtrace memory 470.

The CPU 410 restores data by reading the data of the first row of the internal address of the backtrace memory 470, or the row stored in the internal address specified by the SFR of the internal control circuit 480.

The backtrace memory 470 is initialized by copying the contents of the first row of the internal addresses of the backtrace memory 470, or the contents of the row of the internal address specified by the SFR of the internal control circuit 480, to all other internal addresses.

When the recovery and restart processing of the CPU 410 is completed, the CPU 410 resumes normal processing. In addition, the internal control circuit 480 resumes the write processing to the backtrace memory 470 after the period set in the SFR has elapsed. Here, the resumption of the write processing is set to occur after the recovery and restart processing of the CPU 410 is completed.

If an emergency stop interrupt request is asserted while the recovery/resume process is in progress, the emergency stop process will be executed immediately, and the recovery/resume process will be executed from the beginning after the emergency stop process is completed.

With reference to FIG. 8, the transitions when the CPU 410 of the information processing device of embodiment 4 processes a program recorded in the program memory 420 will be described. In the program memory 420, a normal processing program is recorded at the first address of the program memory 420, "0000h", ... "x-N" ... "x" .... In addition, an emergency stop processing program is recorded from address "S", and a recovery/correct processing program is recorded from address "T" onwards. Under normal circumstances, the CPU 410 reads and executes instructions in order from the first address "0000h" of the program memory 420.

When an emergency stop interrupt request is received while executing an instruction at address "x", the CPU 410 branches to processing the first address "S" of the emergency stop processing in the program memory 420, and reads and executes instructions in order starting from address "S". When the CPU 410 completes the emergency stop processing, it receives a recovery/resume interrupt request, branches to processing the first address "T" of the recovery/resume processing in the program memory 420, and reads and executes instructions in order starting from address "T".

When the CPU 410 completes the recovery and restart processing, it branches to the processing of address "x-N" that was executed n cycles prior to the time the emergency stop interrupt request was received, and reads and executes instructions in order starting from address "x-N". Note that "N" is determined by the internal address (row) of the backtrace memory 470 in which the data to be restored is stored, as set by the SFR of the internal control circuit 480. Specifically, for example, if the data restored by the CPU 410 is the data stored in the internal address "row 5" of the backtrace memory 470, the CPU 410 will resume processing from the instruction at address "x-5".

According to the fourth embodiment, when the circuit becomes unstable due to the effects of noise, processing can be temporarily stopped and resumed when the noise has subsided. In addition, the contents of the emergency stop processing and the recovery/restart processing can be set by a program (software), making it possible to flexibly control the semiconductor integrated circuit device 400 according to the application.

The configurations described in the above embodiments 1 to 4 for initializing the semiconductor integrated circuit device when noise is detected, temporarily stopping the supply of the system clock, setting the input/output terminals to a safety function mode, and performing emergency stop/recovery/restart processing may be arbitrarily combined. In that case, for example, a portion of the semiconductor integrated circuit device may be initialized and the supply of the system clock to other portions may be temporarily stopped.

10A Noise receiving unit 10B Electromagnetic wave detector 20 Noise detection signal generating circuit 30 Noise detection circuit 100 Semiconductor integrated circuit device 110 Initialization signal generating circuit 200 Semiconductor integrated circuit device 210 Clock generating circuit 220 Clock gating control circuit 230 Clock gate cell 300 Semiconductor integrated circuit device 310 Input/output terminal 320 I/O circuit 330 Internal circuit 340 Mode switching control circuit 350 Control signal generating circuit 400 Semiconductor integrated circuit device 420 Program memory 430 Data memory 440 Peripheral circuit 450 Interrupt controller 460 Recovery/restart controller 470 Backtrace memory 480 Internal control circuit

Claims (10)

a noise detection signal generating circuit that generates a detection signal when noise is detected;
a protection circuit that puts a circuit to be protected into a state that avoids the effects of noise in response to the detection signal generated by the noise detection signal generation circuit. The semiconductor integrated circuit device according to claim 1, wherein the protection circuit generates a signal for initializing the circuit to be protected in the semiconductor integrated circuit device in response to the detection signal generated by the noise detection signal generation circuit, and supplies the signal to the circuit to be protected. The semiconductor integrated circuit device according to claim 2, wherein the protection circuit is an initialization signal generating circuit that initializes the entire semiconductor integrated circuit device in response to the detection signal generated by the noise detection signal generating circuit. The semiconductor integrated circuit device according to claim 1, wherein the protection circuit temporarily stops clock supply to the circuit to be protected within the semiconductor integrated circuit device in response to the detection signal generated by the noise detection signal generation circuit. The semiconductor integrated circuit device according to claim 4, wherein the protection circuit is a clock gating control circuit that temporarily stops the supply of a system clock to the semiconductor integrated circuit device in response to the detection signal generated by the noise detection signal generation circuit. The semiconductor integrated circuit device according to claim 1, wherein the protection circuit sets the input/output terminals to a safe input/output state in response to the detection signal generated by the noise detection signal generation circuit. The semiconductor integrated circuit device according to claim 6, wherein the protection circuit outputs an input/output control signal for fixing the input/output terminal to one of a low output state, a high output state, and a high impedance state for a predetermined period in response to the detection signal generated by the noise detection signal generation circuit. The semiconductor integrated circuit device includes a central processing circuit,
the protection circuit generates an emergency stop interrupt request signal and a recovery/restart interrupt request signal in response to the detection signal generated by the noise detection signal generation circuit, and stores a circuit state at the time of receiving the detection signal as data in a backtrace memory;
8. The semiconductor integrated circuit device according to claim 1, wherein the central processing circuit performs emergency stop processing in response to the emergency stop interrupt request signal, and after completing the emergency stop processing, performs recovery/resume processing in response to the recovery/resume interrupt request signal to read data before the emergency stop processing from the backtrace memory. The semiconductor integrated circuit device according to any one of claims 2, 3, 6, and 7, wherein the protection circuit temporarily stops clock supply to the circuit to be protected within the semiconductor integrated circuit device in response to the detection signal generated by the noise detection signal generation circuit. The semiconductor integrated circuit device according to any one of claims 2 to 5, wherein the protection circuit sets the input/output terminal to a safe input/output state in response to the detection signal generated by the noise detection signal generation circuit.