JPH11161519A - Reset device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To omit a reset switch and to enable resetting by making use of a watchdog function by controlling a watchdog timer into a time-up state when a reset request signal is extracted from data inputted to a CPU. SOLUTION: The CPU 1 decides whether or not a signal for resetting the CPU 1 is included in data of a command each time the CPU receives the data. When the command requests the resetting of the CPU 1, the CPU 1 is so controlled as to perform an endless loop process wherein an arithmetic process never ends. When the CPU 1 performs the endless loop process, the watchdog timer 3 is not reset within a set specific time, so it enters the time-up state and the CPU 1 is reset with its time-up output. Thus, when the CPU 1 can be reset, the CPU 1 can be reset remotely.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset device for a computer having a watchdog function.

[0002]

2. Description of the Related Art Conventionally, a computer having a watchdog function is a computer (hereinafter referred to as a "CPU").
When the predetermined arithmetic processing in is not completed within the predetermined time set in the watchdog timer, the CPU is reset assuming that an abnormal state has occurred.

Further, when a new processing mode is set, the CPU is reset in order to clear the processing program of the previous processing mode.
The reset process is also performed when U is started, that is, when the CPU is turned on.

[0004] In addition to the above, resetting the CPU
When the CPU housing is opened during the operation and the processing operation cannot be continued as it is, the system reset switch is activated and the operation is performed. It is configured to be resettable. A reset switch indicated by a dashed line in FIG. 1 used in the description of an embodiment of the present invention described below is a reset switch operated by an operator.

[0005]

However, since the above-mentioned conventional CPU reset device is configured to be reset by a reset switch, there is a possibility that the reset switch is erroneously operated.

For example, if the reset switch is erroneously operated during the arithmetic processing of the CPU, the arithmetic processing is interrupted abnormally, and there is a drawback that it takes a long time to recover, and the reset switch requires components. not only,
There is a disadvantage that the wiring for the reset switch is required and the cost is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a reset device which can omit a conventional reset switch and can be reset using a watchdog function. To provide.

[0008]

According to the present invention, there is provided a reset device for a CPU having a function of being reset by a time-up signal of a watchdog timer. Extraction means for extracting a reset request signal from the data input to the CPU, and control means for controlling the watchdog timer to time-up when the reset request signal is extracted. .

According to another aspect of the present invention, there is provided a reset device for a CPU having a function of being reset by a time-up signal of a watchdog timer. At the end or when a predetermined operation processing mode is selected, etc.
PU means for extracting a state requiring resetting, and control means for controlling so that the watchdog timer times out when a state requiring resetting is extracted. I have.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of a reset device according to an embodiment.
Like the PU, the system is configured to be able to perform predetermined normal arithmetic processing (normal processing) using a predetermined system program and working data stored in a memory (not shown).

The mode setting switch 2 is used to clear the previous arithmetic processing mode when the arithmetic processing of the CPU 1 is switched to another predetermined arithmetic processing mode. It is configured similarly.

The watchdog timer 3 is a well-known CPU
And is started when the CPU 1 starts a predetermined calculation process, and the predetermined calculation process is completed within the time set in the watchdog timer 3. Is not reset and a time-up signal is not output, but if the predetermined arithmetic processing is not completed within the time set in the watchdog timer 3, the time-up signal is output.
It is configured to output a reset signal to U1.

The system reset switch 4 is connected to the CPU 1
As if the case cover (not shown) was opened,
When the CPU 1 cannot continue the processing operation as it is and needs to protect the CPU 1 automatically, it is automatically operated.
When N is set, the CPU 1 is reset and the watchdog timer 3 is also reset.

The conventional system reset switch 4
In FIG. 1, a reset switch operated by an operator is provided in parallel as shown by a chain line in FIG. 1, but this reset switch is omitted in the present invention.

The reset control operation of the present invention will be described with reference to the flowchart of FIG. CPU 1 has I /
It is assumed that a predetermined processing operation is executed by a predetermined command (instruction) via the O unit 5.

Each time the CPU 1 receives command data (Step 100, hereinafter, the step is referred to as "S"), it determines whether or not the data includes a signal for resetting the CPU 1. (S102).

When the command does not relate to the reset of the CPU 1 (No at S102), the CPU 1 continues to execute a predetermined normal process based on the received command (S104, S106, S100...). However, when the command requests that the CPU 1 be reset (Yes at S102), the CPU 1 is controlled so as to execute an infinite loop processing without terminating the arithmetic processing (S107). As this infinite loop processing, "LA
A well-known infinite loop program such as “BEL: NOP → JP LABEL” can be used.

When the CPU 1 executes the infinite loop processing,
Since the watchdog timer 3 is not reset within the set predetermined time, the time is up, and the CPU 1 is reset by the time-up output.

As described above, if the CPU 1 can be reset by including the reset request signal of the CPU 1 in the command, not only the reset switch operated by the operator can be omitted, but also the CPU 1 can be reset remotely. Become.

FIG. 3 shows another example of the reset control of the CPU 1. When the command includes the reset request signal of the CPU 1 (Yes at S202), the reset control is executed.
A flag for stopping the reset of the watchdog timer provided in the memory (not shown) of U1 is set (S1).
206), the time of the watchdog timer 3 is increased. That is, when the timer reset stop flag is set, the watchdog timer 3 times out, and the CPU 1 is reset (Yes at S208).

FIG. 4 shows a case where the CPU 1 is in a test processing mode such as a memory check or a hardware check (S3).
00), when the test is completed (Yes at S302), the reset processing of FIG. 2 or FIG. 3 can be performed.

FIG. 5 shows a configuration in which the processing can be reset when the processing mode of the CPU 1 is set to a predetermined processing mode. That is, when the setting of the predetermined processing mode is read from the setting switch signal (S4).
02 affirmative), the reset processing of FIG. 2 or FIG.
PU1 is configured to be reset.

As shown in FIG. 4 or FIG. 5, the watchdog timer 3 can be timed up when the CPU 1 needs to be reset, such as when the test mode ends or when a predetermined operation processing mode is selected. Then, the CPU 1 can be automatically reset.

[0024]

According to the present invention, there is provided a reset device for extracting a reset request signal from data input to a CPU, and for increasing the time of a watchdog timer when the reset request signal is extracted. Since the control means controls the CPU, not only the reset switch operated by the operator can be omitted, but also the CPU can be remotely reset.

The reset device according to the present invention comprises: an extracting means for extracting a state in which the CPU needs to be reset, such as when the test mode of the CPU is completed or a predetermined operation processing mode is selected; Is extracted, the control means controls the watchdog timer to time up, so that the CPU can be automatically reset.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a reset device according to an embodiment of the present invention.

FIG. 2 is an example of a reset control operation.

FIG. 3 is an example of a reset control operation.

FIG. 4 is an example of a reset control operation.

FIG. 5 is an example of a reset control operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Computer (CPU) 2 Mode setting switch 3 Watchdog timer 4 System reset switch 5 I / O unit

Claims (2)

[Claims] 1. A reset device for a computer having a function of being reset by a time-up signal of a watchdog timer, comprising: an extracting unit for extracting a reset request signal from data input to the computer; and a reset request signal. Control means for controlling the watchdog timer to time-up when is extracted, the reset device comprising: 2. A reset device for a computer having a function of being reset by a time-up signal of a watchdog timer, wherein the computer is reset when a test mode of the computer is terminated or a predetermined operation processing mode is selected. A resetting means for extracting a state requiring a reset, and a control means for controlling a time-out of the watchdog timer when a state requiring a reset is extracted. .