[go: up one dir, main page]
More Web Proxy on the site http://driver.im/

JPH024139B2 - - Google Patents

Info

Publication number
JPH024139B2
JPH024139B2 JP57175011A JP17501182A JPH024139B2 JP H024139 B2 JPH024139 B2 JP H024139B2 JP 57175011 A JP57175011 A JP 57175011A JP 17501182 A JP17501182 A JP 17501182A JP H024139 B2 JPH024139 B2 JP H024139B2
Authority
JP
Japan
Prior art keywords
layer
electrode
gate electrode
ohmic
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57175011A
Other languages
Japanese (ja)
Other versions
JPS5965484A (en
Inventor
Shuji Asai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP17501182A priority Critical patent/JPS5965484A/en
Publication of JPS5965484A publication Critical patent/JPS5965484A/en
Publication of JPH024139B2 publication Critical patent/JPH024139B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法、特にシヨツト
キバリアゲート型電界効果トランジスタの製造方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a shotgun barrier gate field effect transistor.

GaAs半導体はSiに比べて5〜6倍と大きな電
子移動度を有し、この高速性に大きな特徴がある
ために、最近超高速の集積回路(以下ICと称す)
に応用する研究開発が活発に行なわれている。こ
のGaAsICの能動素子としては、基本的に第1図
に示すようなシヨツトキーバリアゲート型電界効
果トランジスタ(以下MESFETと称す)が提案
されている。
GaAs semiconductors have an electron mobility that is 5 to 6 times higher than that of Si, and because of this high-speed characteristic, they have recently been used as ultra-high-speed integrated circuits (hereinafter referred to as ICs).
Research and development is actively being carried out to apply this technology to As the active element of this GaAsIC, a Schottky barrier gate field effect transistor (hereinafter referred to as MESFET) as shown in FIG. 1 has basically been proposed.

これは、プレーナ構造と呼ばれ、第1図に示す
よう半絶縁性GaAs基板4上にエエピタキシヤル
成長やイオン注入により厚さ約0.2μmのn形動作
層5を形成し、ホトレジスト膜を用いたリフトオ
フ法などによりゲート電極1を形成し、マスクの
位置合せを行ない同様にリフトオフ法などにより
ソースおよびドレインのオーミツク性電極2,3
を形成した比較的簡単な構造のものである。
This is called a planar structure, and as shown in Fig. 1, an n-type active layer 5 with a thickness of about 0.2 μm is formed on a semi-insulating GaAs substrate 4 by air epitaxial growth or ion implantation, and a photoresist film is used. The gate electrode 1 is formed by a lift-off method, etc., and the mask is aligned, and the source and drain ohmic electrodes 2, 3 are formed by a similar lift-off method.
It has a relatively simple structure.

しかしこのようなプレーナ構造の製造方法で
は、オーミツク性電極を形成するために目合せが
必要であり、目合せ精度は最良の機器においても
±0.5μm位であり、実用機では±1.0μm位であ
る。このような目合せ装置を用いて製造する
MESFETではオーミツク性電極とゲート電極と
の電極間隔を1.0μm以下にすることは実際上困難
である。
However, in the manufacturing method of such a planar structure, alignment is necessary to form an ohmic electrode, and the alignment accuracy is about ±0.5 μm even with the best equipment, and about ±1.0 μm with practical equipment. be. Manufactured using such alignment equipment
In MESFET, it is practically difficult to reduce the electrode spacing between the ohmic electrode and the gate electrode to 1.0 μm or less.

一方ゲート電極間のGaAs動作層表面では、表
面での結晶性の乱れや気体の吸着などにより、第
2図に示すように表面空乏層6が発生し実効的な
動作層が薄くなり、オーミツク性電極とゲート電
極との電極間隔が長い場合にはゲートソース間の
動作層抵抗(ソース直列抵抗)が増大して、相互
コンダクタンスgmが著しく低下し、良好なFET
特性を得ることが難しい。
On the other hand, on the surface of the GaAs active layer between the gate electrodes, a surface depletion layer 6 is generated as shown in Figure 2 due to disturbance of crystallinity and adsorption of gas on the surface, and the effective active layer becomes thinner, resulting in ohmic When the distance between the electrode and the gate electrode is long, the active layer resistance between the gate and source (source series resistance) increases, and the mutual conductance gm decreases significantly, resulting in a good FET.
Difficult to obtain characteristics.

本発明の目的は上記のような問題点に鑑みてな
されたものであり、表面空乏層の影響を小さくし
て良好なFET特性を得るために、オーミツク性
電極とゲート電極との電極間隔を1.0μm以下にす
ることを可能にし、かつ、ゲート電極とソースお
よびドレインのオーミツク性電極を自己整合的に
形成する電界効果トランジスタの製造方法を提供
することにある。
The purpose of the present invention was made in view of the above problems, and in order to reduce the influence of the surface depletion layer and obtain good FET characteristics, the electrode spacing between the ohmic electrode and the gate electrode is set to 1.0. It is an object of the present invention to provide a method for manufacturing a field effect transistor, which enables formation of a gate electrode and ohmic electrodes of a source and a drain in a self-aligned manner.

本発明によれば半導体基板動作層上にゲート電
極を形成する工程と、該ゲート電極近傍を被覆層
で覆う工程と、オーミツク性電極を被着する工程
と、前記オーミツク性電極上にレジスト膜を塗布
しドライエツチング法により前記被覆層上の前記
オーミツク性金属を除去してソースおよびドレイ
ン電極を形成する工程を有することを特徴とする
半導体装置の製造方法が得られる。
According to the present invention, there are a step of forming a gate electrode on an active layer of a semiconductor substrate, a step of covering the vicinity of the gate electrode with a coating layer, a step of depositing an ohmic electrode, and a step of forming a resist film on the ohmic electrode. A method for manufacturing a semiconductor device is obtained, which comprises the step of removing the ohmic metal on the coating layer by coating and dry etching to form source and drain electrodes.

次に本発明の実施例を図面を用いて説明する。
第3図a〜iは本発明半導体装置の製造方法の一
実施例を示す工程図である。
Next, embodiments of the present invention will be described using the drawings.
FIGS. 3a to 3i are process diagrams showing an embodiment of the method for manufacturing a semiconductor device of the present invention.

第3図aのように半絶縁性GaAs基板にイオン
注入法により形成した不純物濃度約2×1017cm
-3、厚さ約0.2μmのn形動作層24の上に、第1
層21としてアルミニウムAlを2.0μmスパツタ蒸
着し、第2層22として二酸化シリコンSiO2
0.3μmスパツチ蒸着し、第3層23としてホトレ
ジスト膜1.0μmを塗布し1.0μm長のゲート電極パ
ターンの開口25を設ける。
As shown in Figure 3a, the impurity concentration is approximately 2×10 17 cm formed by ion implantation on a semi-insulating GaAs substrate.
-3 , on the n-type operating layer 24 with a thickness of about 0.2 μm, the first
Aluminum Al was sputter-deposited to a thickness of 2.0 μm as the layer 21, and silicon dioxide SiO 2 was deposited as the second layer 22.
A 0.3 μm spatch deposition process is performed, and a 1.0 μm photoresist film is applied as the third layer 23 to form an opening 25 for a gate electrode pattern with a length of 1.0 μm.

そして第3図bに示す如くSiO2膜22をバツ
フアド弗酸により0.5μmサイドエツチングして開
口25より広い開口26を設け、更にAl層21
を60℃リン酸により1.5μmサイドエツチングして
開口26より広い開口27を設け、第3図cのよ
うにゲート金属としてアルミニウムAlを0.3μmヒ
ータ蒸着して開口25により決まるゲート電極1
が形成され、アセトンでホトレジスト膜23を溶
してホトレジスト膜23上の余分なゲート金属層
30も同時に除去し、第3図dのようにゲート電
極1の上に一酸化シリコンSiOを0.9μmヒータ蒸
着して第2層の開口26により決まる被覆層28
を形成する。
Then, as shown in FIG. 3b, the SiO 2 film 22 is side-etched by 0.5 μm using buffered hydrofluoric acid to form an opening 26 wider than the opening 25, and the Al layer 21 is then etched.
Side etching is performed by 1.5 μm using phosphoric acid at 60° C. to form an opening 27 wider than the opening 26, and as shown in FIG.
is formed, the photoresist film 23 is dissolved with acetone, the excess gate metal layer 30 on the photoresist film 23 is also removed at the same time, and silicon monoxide SiO is deposited on the gate electrode 1 with a thickness of 0.9 μm as shown in FIG. 3d. A covering layer 28 is deposited and defined by the openings 26 in the second layer.
form.

次に第3図eのようにAl層21を60℃リン酸
で溶して余分な層を除去し、ゲート電極1が被覆
層28で覆われたものを残し、第3図fのように
オーミツク性電極AuGe・Pt2000Åを垂直に蒸着
することによりソースおよびドレイン電極2,3
が形成され、第3図gのようにホトレジスト膜2
9を厚さ1.0μmスピン塗布して乾燥し、第3図h
のようにArイオンミーリングにより、基板を回
転してイオン入射角45゜で被覆膜28上のオーミ
ツク性金属層31がなくなるまでエツチング除去
し、第3図iのように残つたホトレジスト膜29
をはくり液で除去することにより、ソースおよび
ドレイン電極2,3が被覆層28により分離され
て自己整合的に形成されたGaAs MESFETが完
成する。
Next, as shown in Fig. 3e, the Al layer 21 is dissolved in phosphoric acid at 60°C to remove the excess layer, leaving the gate electrode 1 covered with the covering layer 28, and as shown in Fig. 3f. Source and drain electrodes 2 and 3 are formed by vertically depositing ohmic electrodes AuGe/Pt with a thickness of 2000 Å.
is formed, and the photoresist film 2 is formed as shown in FIG.
9 was spin-coated to a thickness of 1.0 μm and dried, as shown in Figure 3h.
By rotating the substrate and etching away the ohmic metal layer 31 on the coating film 28 by Ar ion milling at an ion incidence angle of 45° as shown in FIG. 3, the remaining photoresist film 29 is removed as shown in FIG.
By removing with a stripping liquid, a GaAs MESFET in which the source and drain electrodes 2 and 3 are separated by the covering layer 28 and formed in a self-aligned manner is completed.

SiO2層22をサイドエツチングするバツフア
ド弗酸液としては、50%弗酸水と40%弗化アンモ
ニウム水を1:14で混合したものを10℃で用いる
と、0.5μmサイドエツチングされるまでの時間は
8分であり、ばらつきは±0.1μmと小さく精度よ
く行なわれる。また、被覆層の横幅を小さくする
ためにヒータ蒸着の一酸化シリコンSiOを用いた
が、二酸化シリコンSiO2、窒化シリコン、窒化
チタンなどであつてもよく、これらを電子ビーム
蒸着、スパツタ蒸着してもよい。
As the buffered hydrofluoric acid solution for side-etching the SiO 2 layer 22, when a mixture of 50% hydrofluoric acid water and 40% ammonium fluoride water at a ratio of 1:14 is used at 10°C, it is possible to side-etch the SiO 2 layer 22 by 0.5 μm. The time is 8 minutes, and the variation is as small as ±0.1 μm, making it highly accurate. Furthermore, in order to reduce the width of the coating layer, heater-deposited silicon monoxide SiO was used, but silicon dioxide SiO 2 , silicon nitride, titanium nitride, etc. may also be used, and these can be deposited by electron beam evaporation or sputter evaporation. Good too.

この実施例によると、ゲート電極とソースおよ
びドレイン電極との間隔は被覆層の横幅により決
定する。本実施例では、被覆層の横幅は第2層2
2のサイドエツチング量により決まり、1μm以
下に設定することは容易である。第2層22とし
て用いた二酸化シリコンSiO2はエツチング液の
組成と液温などの条件を決めるとサイドエツチン
グ量をエツチング時間で制御することが可能であ
る。
According to this embodiment, the distance between the gate electrode and the source and drain electrodes is determined by the width of the covering layer. In this example, the width of the covering layer is the second layer 2.
It is determined by the amount of side etching in step 2, and can easily be set to 1 μm or less. The amount of side etching of the silicon dioxide SiO 2 used as the second layer 22 can be controlled by the etching time by determining conditions such as the composition and temperature of the etching solution.

そして、このようにして形成したゲート幅20μ
m、ゲート長1.0μm、電極間隔0.5μmの
MESFETの相互コンダクタンスgmは3.2mSであ
り、従来のようにホトレジスト膜の目合せで電極
間隔1.2μmで形成したもののgmは1.8mSであり、
本発明による電極間隔が短かいMESFETのgm
は、従来のものに較べて2倍近い値となつてい
る。
The gate width formed in this way is 20μ.
m, gate length 1.0μm, electrode spacing 0.5μm.
The mutual conductance gm of the MESFET is 3.2 mS, and the gm of the conventional photoresist film formed with an electrode spacing of 1.2 μm is 1.8 mS.
gm of MESFET with short electrode spacing according to the present invention
is almost double the value of the conventional one.

本発明によると、表面空乏層の影響を小さくし
てオーミツク性電極とゲート電極との電極間隔を
1.0μm以下にすることを可能にした電界効果トラ
ンジスタが得られる。
According to the present invention, the electrode spacing between the ohmic electrode and the gate electrode can be reduced by reducing the influence of the surface depletion layer.
A field effect transistor that can be made smaller than 1.0 μm can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の最も基本的なプレーナ構造のシ
ヨツトキーゲート型MESFETの断面図、第2図
はこのプレーナ構造MESFETの動作層表面に表
面空乏層が発生している状態を示す図、第3図a
〜iは本発明の製造方法の一実施例を説明するた
めの工程図である。図において、 1…ゲート電極、2…ソース電極、3…ドレイ
ン電極、4…半絶縁性基板、5,24…半導体動
作層、6…表面空乏層、21…第1層、22…第
2層、23…第3層、25,26,27…各層の
開口、28…被覆層である。
Figure 1 is a cross-sectional view of the most basic conventional Schottky gate MESFET with a planar structure. Figure 3a
-i are process diagrams for explaining one embodiment of the manufacturing method of the present invention. In the figure, 1... gate electrode, 2... source electrode, 3... drain electrode, 4... semi-insulating substrate, 5, 24... semiconductor operating layer, 6... surface depletion layer, 21... first layer, 22... second layer , 23...third layer, 25, 26, 27...openings in each layer, 28...covering layer.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板動作層上にゲート電極を形成する
工程と、該ゲート電極近傍を被覆層で覆う工程
と、オーミツク性金属を被着する工程と、前記オ
ーミツク性金属上にレジスト膜を塗布しドライエ
ツチング法により前記被覆層上の前記オーミツク
性金属を除去してソースおよびドレイン電極を形
成する工程を有することを特徴とする半導体装置
の製造方法。
1. A step of forming a gate electrode on the active layer of the semiconductor substrate, a step of covering the vicinity of the gate electrode with a coating layer, a step of depositing an ohmic metal, and a step of applying a resist film on the ohmic metal and dry etching. 1. A method of manufacturing a semiconductor device, comprising the step of removing the ohmic metal on the coating layer by a method to form source and drain electrodes.
JP17501182A 1982-10-05 1982-10-05 Manufactue of semiconductor device Granted JPS5965484A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17501182A JPS5965484A (en) 1982-10-05 1982-10-05 Manufactue of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17501182A JPS5965484A (en) 1982-10-05 1982-10-05 Manufactue of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5965484A JPS5965484A (en) 1984-04-13
JPH024139B2 true JPH024139B2 (en) 1990-01-26

Family

ID=15988651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17501182A Granted JPS5965484A (en) 1982-10-05 1982-10-05 Manufactue of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5965484A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56100482A (en) * 1980-01-14 1981-08-12 Matsushita Electric Ind Co Ltd Manufacture of fet

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56100482A (en) * 1980-01-14 1981-08-12 Matsushita Electric Ind Co Ltd Manufacture of fet

Also Published As

Publication number Publication date
JPS5965484A (en) 1984-04-13

Similar Documents

Publication Publication Date Title
JPH0354464B2 (en)
JPH07107905B2 (en) Method for manufacturing semiconductor device
JPS6246073B2 (en)
JPS6351550B2 (en)
US5376812A (en) Semiconductor device
JPH024139B2 (en)
JPH065682B2 (en) Method for manufacturing semiconductor device
JPS5965485A (en) Manufacture of semiconductor device
JPS5975673A (en) Manufacture of semiconductor device
JP2503667B2 (en) Method for manufacturing semiconductor device
JPS61216487A (en) Manufacture of semiconductor device
JPS5833714B2 (en) Method for manufacturing gallium arsenide Schottky barrier gate field effect transistor
JPS6323366A (en) Manufacture of field-effect transistor
JPS6037173A (en) Manufacture of field effect transistor
JP2803112B2 (en) Method for manufacturing semiconductor device
JPS59172776A (en) Manufacture of semiconductor device
JPS6086871A (en) Manufacture of field effect transistor
JPH0797634B2 (en) Field effect transistor and manufacturing method thereof
JPS60198869A (en) Manufacture of semiconductor device
JPH01161873A (en) Manufacture of semiconductor device
JPS6037175A (en) Manufacture of field effect transistor
JPH0574814A (en) Manufacture of schottky-gate type field-effect transistor
JPH09293735A (en) Manufacture of field effect transistor
JPH047101B2 (en)
JPS60132376A (en) Manufacture of schottky barrier gate field effect transistor