JPS6246073B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a so-called Schottky gate field effect transistor using a Schottky barrier in the gate.

[Technical background of the invention and its problems]

In a field effect transistor (FET) using a Schottky barrier at the gate, the gate length and the source series resistance existing between the source and gate are major factors that determine its characteristics. In other words, there is a relationship between the gate length (lg) and the FET signal propagation delay time (tpd): tpd∝lg ² , so the shorter lg, the smaller tpd becomes, enabling high-speed operation. . Regarding source series resistance (Rs), if the FET's intrinsic transconductance is gmo and the actual transconductance is gm, then there is a relationship as follows: gm = gmo/(1 + gmoRs), and the larger Rs is, the smaller gm is. . Furthermore, there is a relationship between lg and gmo: gmo∝1/lg.

In other words, in order to increase the operating speed of the FET, the gate length lg should be shortened and the source series resistance should be reduced.
It is necessary to reduce Rs.

However, there is a limit to reducing the gate length with conventional photoetching technology, which is 1 μm.
It is considered difficult to obtain a gate length below.

Therefore, as shown in FIG. 1, the conventional method used is to form a gate electrode 3 with a heat-resistant metal, and use this as a mask to implant ions on both sides of the gate to form high concentration layers 4 and 5. There is a way to reduce Rs. In the figure, 1 is, for example, semi-insulating
GaAs base, 2 is an n-type GaAs layer. However, in this method, the gate electrode 3 and the high concentration layers 4 and 5 overlap due to impurity re-diffusion in the high concentration layers 4 and 5 during annealing, which increases the gate capacitance and lowers the drain breakdown voltage to about 4V. .

As another example, as shown in FIG. 2, when etching the gate electrode 3, over-etching is applied to shorten the gate length, and the photoresist 6, which is an etching mask, is used as it is as a mask for ion implantation. There is a method of forming the high concentration layers 4 and 5. However, with this method, when a conventional wet etching method or isotropic plasma etching method is used to etch the gate electrode, the amount of overetching varies depending on the thickness distribution of the metal film, resulting in an increase in the gate length. It is difficult to control precisely. Furthermore, during ion implantation, the substrate is often tilted at an angle of 5 to 10 degrees to avoid the effects of surface channeling.
There is also a possibility that either the source region or the drain region becomes closer to the gate electrode than necessary.

[Purpose of the invention]

The present invention has been made in view of the above points,
The present invention provides a method for manufacturing a Schottky gate type FET that can shorten the gate length to submicrons without using advanced lithography technology, has a low source series resistance, and has a high drain breakdown voltage.

[Summary of the invention]

In summary, the present invention is to obtain a gate length slightly smaller than the mask dimension with good controllability by etching a gate electrode metal film by sequentially combining anisotropic and isotropic dry etching techniques in this order. Next, an insulating film is formed using a deposition method with excellent step coverage while leaving the mask, and then anisotropic dry etching is performed.
The method is characterized in that the insulating film is left only on the side surfaces of the gate electrode, that is, under the eaves of the mask, and in this state, low-resistance source and drain regions are formed by ion implantation.

〔Effect of the invention〕

According to the present invention, the gate length can be shortened to submicrons with good controllability by combining dry etching techniques. In addition, as a result of performing ion implantation with an insulating film attached to the side surface of the gate electrode, it is possible to separate the gate electrode and the source and drain regions by a minute distance with good controllability, resulting in small gate capacitance and high-speed operation. Therefore, a short key gate type FET with high drain breakdown voltage can be obtained.

[Embodiments of the invention]

Below, regarding an example using GaAs for the substrate,
This will be explained in detail with reference to FIG. For example, a substrate is used in which an n-type GaAs layer 12 that becomes an active layer is grown on a semi-insulating GaAs substrate 11 doped with chromium (Cr), and a tungsten (W) film is formed on the surface of this substrate as a heat-resistant metal film that becomes a gate electrode. A gold (Au) film 14 with a width of 1 μm and a thickness of about 2000 Å is formed on the portion that will become the gate electrode as an etching-resistant mask.
Diagram a). At this time, if a lift-off method is used for patterning the Au film 14, a fine pattern can be formed with high precision.

Next, using this Au film 14 as a mask, the W film 13
is completely etched using a parallel plate reactive ion etching (RIE) device (Figure 3b). Etching gas was CF ₄ , flow rate was 20c.c./min.
The etching gas pressure is 0.05 Torr, and the high frequency power is
It is 200W. The etching rate of the W film 13 under these conditions is 300 Å/min, and the etching progresses with complete anisotropy. Note that the selectivity with respect to the Au film 14 and the GaAs layer 12 is sufficiently obtained as ~8 and ~10, respectively. Following this RIE, the W film 13 is etched using a normal cylindrical plasma etching device. A mixed gas of CF ₄ and O ₂ was used as the etching gas, and the flow rates were 15 c.c./min and 5 c.c./min, respectively.
cc/min, etching gas pressure is 0.1 Torr, and high frequency power is 100W. In the cylindrical plasma etching apparatus, the W film 13 is etched isotropically at an etching rate of 100 Å/min. After etching for 20 minutes under these conditions, the Au film 14
Since the GaAs layer 12 is not etched completely, the side wall of the W film 14 recedes, and the eaves (Δx) of the Au film 14 are formed by 0.2 μm (FIG. 3c).

In this way, we first process the side walls of the W film vertically using RIE, which is anisotropic dry etching, and then perform side etching using plasma etching, which is isotropic dry etching.
The side etching amount (Δx) can be controlled very precisely. Furthermore, since the entire process is a dry etching process, the uniformity within the wafer surface and between wafers is also very good. For example, when we measured the gate length over the entire surface of a 2-inch φ wafer in this state, we found that the film thickness distribution of the W film was ±
Even though it was about 700Å, the gate length was
It was 0.6 μm±0.05 μm. Furthermore, the eaves Δx of the Au film has almost no variation within the plane, ±0.05
The distribution of μm can be considered to be a variation at the time when the pattern of the Au film is formed.

After forming the gate electrode as above, reduce the pressure
Si ₃ N ₄ film 15 ~6000Å by CVD (LPCVD) method
accumulate. Since this method has very good step coverage, it is possible to completely cover the irregularities on the substrate (FIG. 3d). After this, RIE the entire surface with _CF4 gas.
Do this. As a result, Au
The Si ₃ N ₄ film 15 remains only under the eaves of the film 14 (FIG. 3e).

In this state, ²⁸ Si ⁺ ions are
After ion implantation at 200KeV and a dose of 3×10 ¹³ cm ^-3 and annealing at 800 to 850°C for 15 minutes to form low resistance source and drain regions 16 and 17, AuGe
Ohmic electrodes 18 and 19 made of an alloy were formed (FIG. 3f).

As a result, although the gate mask size is 1 μm, the actual gate length is as short as 0.6 μm, and the distance between the source, drain, and gate is 0.2 μm.
Because the FET is small, the source series resistance and gate capacitance are sufficiently small, high-speed operation is possible, and a high-performance FET with a drain breakdown voltage of 10 V or more was obtained. Moreover, the FET characteristics had very good uniformity with little variation within the wafer surface and between wafers.

As a comparative example, an Al ₂ O ₃ film was used in place of the Au film in the above example, and in the state shown in Fig. 3c, ions were implanted, passivation was performed with SiO ₂ by atmospheric pressure CVD, and heat treatment was performed to form an FET. was formed. Comparing this with the above embodiment, in the above embodiment, the resistance of the gate electrode itself was about 30% lower, and the variation in the source series resistance was about 1/2 smaller. In the case of the comparative example, the variation in series resistance is thought to be due to the substrate being tilted at 7 degrees during ion implantation, but in the above example in which a Si ₃ N ₄ film was formed on the side wall of the gate electrode, this Si ₃ N Since the _4- layer film serves as a mask for ion implantation, variations are reduced even when the substrate is tilted. Further, for the same reason, the drain breakdown voltage was 6 to 12 V in the comparative example, whereas the variation in the drain breakdown voltage was 10 to 12 V in the above example, with small variations.

In addition, the comparative examples had a very high rate of defective products due to imperfection of the passivation of the eaves during heat treatment, but the samples of the above examples had almost no defective products.

The present invention is not limited to the above embodiments. For example, the metal film for the gate electrode is not limited to W, but any metal that is heat resistant and can be dry etched may be used, such as Mo or
WN, WSi, etc. can be used. Further, the etching-resistant mask is not limited to Au, but may be made of Pt or the like as long as it does not react with the underlying gate metal at a high temperature of 800° C. and can be used as a dry etching mask. Also Si ₃ N ₄
Instead of the film, a SiO ₂ film can be used by a similar deposition method. Other etching gases and film deposition methods are not limited to those of the above embodiments as long as they can achieve the intended purpose.

Furthermore, although the above embodiments have been described for the case where the substrate is GaAs, the present invention can also be applied to Si or other compound semiconductors by simply changing the electrode metal or donor impurity.

[Brief explanation of the drawing]

1 and 2 are sectional views of a Schottky gate type FET according to a conventional method, and FIGS. 3 a to 3 f are sectional views showing the manufacturing process of a Schottky gate type FET according to an embodiment of the present invention. . 11...Semi-insulating GaAs substrate, 12...n type
GaAs layer, 13... W film (gate electrode), 14...
Au film (etching resistant mask), 15...LPCVD
-Si ₃ N ₄ film, 16... source region, 17... drain region, 18, 19... ohmic electrode.

Claims (1)

[Scope of Claims] 1. A step of forming a gate metal film that forms a Schottky barrier on the entire surface of a semiconductor substrate, a step of forming an etching-resistant mask on this metal film, and a step of etching the metal by an anisotropic dry etching method. selectively removing the film by etching, and then receding the sidewalls of the remaining metal film by isotropic dry etching to form the eaves of the etching-resistant mask; and with the etching-resistant mask remaining. a step of depositing an insulating film over the entire surface by a deposition method with good step coverage; a step of etching the deposited insulating film by an anisotropic dry etching method to leave it only under the eaves of the etching-resistant mask; A Schottky gate comprising the steps of forming low-resistance source and drain regions by ion implantation using a film and the metal film as a mask, and forming ohmic electrodes on these source and drain regions. Method of manufacturing type field effect transistor. 2 The semiconductor substrate is a semi-insulating GaAs base with an n-type
A GaAs layer is grown, the gate metal film is a W film, and the etching-resistant mask is a
The insulating film is made of Si ₃ N ₄ by low pressure CVD.
The anisotropic dry etching method uses CF ₄
Manufacturing a Schottky gate type field effect transistor according to claim 1, wherein the isotropic dry etching method is a reactive ion etching method using a gas, and the isotropic dry etching method is a plasma etching method using a CF ₄ +O ₂ gas. Method.