JPH02177062A - Digital information signal recorder - Google Patents

Abstract

PURPOSE:To accurately process reproducing data by providing a preamble section in front of a data section recorded with a digital information signal. CONSTITUTION:The preamble section is provided in front of the data section, and this section is recorded with a repeating pattern with min. inversion intervals after modulation and also recorded with a block synchronizing pattern with regular intervals. Consequently, by supplying the repeating pattern with min. inversion intervals to a PLL on the recording side, the PLL is locked, and at the time of entering the data section, a clock signal synchronized with the reproducing data is generated by the PLL. Then, even when a block synchronizing signal inserted into the preamble section is detected, and this is synchronized with a counter for generating a timing pulse, and then the block synchronizing signal is not detected in the beginning of the data section, a required timing pulse can be formed by the inserted signal, thus processing accurately the reproducing data.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a rotary head type VT that records PCM audio signals and video signals on a magnetic tape using a rotary head.
The present invention relates to a digital information signal recording device applicable to R, and particularly to the data structure of the recording signal.

[Summary of the invention]

In this invention, in a digital information signal recording device in which a digital information signal is discontinuously recorded on a recording medium, a preamble section is provided before a data section in which the digital information signal is recorded, and the preamble section includes: By recording the repeating pattern of the minimum inversion interval after modulation and the block synchronization pattern of regular intervals, the block synchronization signal can be detected satisfactorily when entering the preamble period.

[Conventional technology]

As one of the rotary head type VTRs, 1801 magnetic tapes are mounted on the circumferential surface of a drum on which a pair of heads are provided facing each other.
It is known to record a video signal within a wrapping angle of 180°, and to record a time-axis compressed PCM audio signal in an overlap section. In such a VTR, PCM audio signals are recorded discontinuously on tape, and the reproduced PCM audio signals are also intermittent. Furthermore, in the case of a rotary head type digital audio recorder, there is a period when the tape and the head do not come into contact with each other, so the reproduced data becomes intermittent.

When a PCM audio signal is recorded, it is encoded with an error correction code, and the parity (check data) of the PCM audio signal and the error correction code are converted into block data. The block configuration is such that a block synchronization signal is added to the beginning, a block address signal is added after that, and data (PCM audio signal, parity) is located further after.

On the playback side, a clock synchronized with the playback PCM audio signal is generated by a PLL, and the playback PCM audio signal is taken into the playback circuit. As mentioned above, when the playback data is intermittent, in order to facilitate PLL pull-in,
A preamble section is provided before a data section in which blocks are consecutive. In this preamble section, a repeating pattern of the minimum inversion interval after modulation is usually recorded.

[Problem to be solved by the invention]

The preamble section allows the PLL to be pulled in without any problems. However, since the preamble section does not include the block synchronization signal, there is a disadvantage that the block synchronization signal cannot be interpolated in the block immediately after the preamble section.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a digital information signal recording device that can interpolate a block synchronization signal in a data interval and can sufficiently synchronize a PLL with reproduced data.

[Means to solve the problem]

In this invention, in a digital information signal recording device in which a digital information signal is recorded discontinuously on a recording medium, a preamble section is provided before a data section in which the digital information signal is recorded, and the preamble section includes:
A repeating pattern with a minimum inversion interval after modulation and a block synchronization pattern with a regular interval are recorded.

One arrangement of the preamble section is such that a repeating pattern with a minimum inversion interval after modulation is recorded at the beginning of the preamble section, and a block synchronization pattern is recorded at regular block intervals after the repeating pattern.

Another arrangement of the preamble section is one in which a block synchronization pattern is recorded in the preamble section at regular block intervals as a whole, and a repeating pattern with the minimum inversion interval after modulation is recorded after the block synchronization pattern. It is.

Additionally, additional data such as a block address is inserted into the preamble section together with the block synchronization pattern, and the additional data is subjected to error detection or encoding with an error correction code.

[Effect]

A preamble section is provided before the data section,
In this preamble section, a repeating pattern of the minimum inversion interval after modulation is recorded, as well as a block synchronization pattern of regular intervals. Therefore, by supplying the repeating pattern with the minimum inversion interval to the PLL on the reproduction side, the PLL is pulled in, and when entering the data period, the PLL generates a clock signal synchronized with the reproduction data. Further, a block synchronization signal inserted in the preamble section is detected, and a counter that generates a timing pulse is synchronized with the detected block synchronization signal. Therefore, even if the block synchronization signal cannot be detected at the beginning of the data section, the interpolated signal can form the necessary timing pulse, and the reproduced data can be processed correctly.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings. This description is given in the following order.

a. VTR recording/reproducing circuit; PCM recording processing circuit; C0 recording data configuration; d; reproducing side processing e; modification a; VTR recording/reproducing circuit; rotary head type to which the present invention can be applied first; V
Figures 4 and 5 show examples of TR recording/reproducing circuits.
This will be explained with reference to the figures. This VTR records a video signal and a PCM audio signal on a magnetic tape in one scan.

In FIG. 4, 21A and 21B indicate a pair of rotating rads, the heads 21A and 21B being mounted on a rotating drum (not shown) with opposing spacing of 180 degrees. The drum is driven by a motor 22 at a frame frequency (NT
In the case of the SC method, it is rotated by 29°97] (z). A magnetic tape 23 is run diagonally at a constant speed over a range of 180 degrees or more on the circumferential surface of the drum. in this case,
The rotational phases of the heads 21A and 21B are controlled during recording so as to be synchronized with the recorded video signal, and during playback are servo-controlled to scan the tracks correctly.

Therefore, as shown in FIG. 5A, in every other field period Ta, the head 21A scans the video section of the track, and also scans the PCM section before the video section in the overlap period before the period Ta. . Further, in every other field period Tb, the head 21B scans the video section of the track, and also scans the PCM section before the video section in the overlap period before the period Tb.

When recording a video signal, the color video signal SC and the monaural audio signal Sm are supplied to the video recording processing circuit 24, and the FM luminance signal, the low-frequency converted carrier color signal, the FM audio signal, and the tracking @ pilot signal are sent to the video recording processing circuit 24. The frequency multiplexed signal Sf of 1 is continuously taken out as shown in FIG.
5.

A pulse Pg with a frame period indicating the rotational phase of the motor 22
is generated from the pulse generator 26, and this pulse Pg is supplied to the signal forming circuit 28 via the shaping amplifier 27. From this signal forming circuit 28, as shown in FIG.
A pulse signal SW is formed which is inverted every time a and 'rb.

This pulse signal SW is supplied as a control signal to the switch circuit 25, and the switch circuit 25 is alternately switched to the illustrated state every period Ta and Tb. Therefore, the signal Sf is alternately taken out from the switch circuit 25 every period Ta and Tb, as shown in the fifth diagram.

The frequency multiplexed signal Sf passes through recording amplifiers 29A and 29B, and is further supplied to recording side terminals R of switch circuits 30A and 30B.
It is supplied to the rotary heads 21A, 21B through. Therefore, the magnetic tape 23 receives the signal Sf every period Ta5Tb.
are recorded sequentially as video sections.

Further, stereo audio signals R, , R are supplied to the PCM recording processing circuit 31 . Signal SW is pulse forming circuit 3
As shown in FIG.
A pulse Ps that becomes "1" is formed during the period when the section is scanned. This pulse Ps is supplied to the PCM recording processing circuit 31, and as shown in FIG. At the same time, it is converted into a PCM signal. Furthermore, (8 → 1
0) It is modulated and extracted as a PCM signal Ss.

During the field period Ta, this signal Ss is transmitted from [switch circuit 25→amplifier 29B→terminal R of switch circuit 30B]
The zero period Tb is supplied to the head 21B via the signal path of
is supplied to the head 21A via the signal path [switch circuit 25→amplifier 29A→terminal R of switch circuit 30A]. Therefore, the track has a signal S in the video section.
Prior to recording f, signal Ss is recorded in the PCM section.

On the other hand, during reproduction, the signals Ss and Sf are alternately reproduced from the tracks of the magnetic tape 23 by the heads 21A and 21B. The reproduced signals Ss and Sf are supplied to the switch circuit 34 through the reproduction side terminals P of the switch circuits 30A and 30B, and further through the reproduction amplifiers 33A and 33B. The signal SW is supplied as a control signal to the switch circuit 34, from which the signal Sf is continuously taken out and the signal SS is taken out every field period.

The signal Sf from the switch circuit 34 is supplied to the video reproduction processing circuit 35, from which the original color video signal Sc and monaural audio signal Sm are taken out. The signal Ss from the switch circuit 34 is PCM
At the same time, the pulse Ps is supplied as a window signal to the PCM reproduction processing circuit 36, and the original stereo audio signal R is extracted from the signal Ss.

b. PCM recording processing circuit An example of the above-mentioned PCM recording processing circuit 31 will be explained with reference to FIG. In FIG. 6, an analog audio signal is supplied to an input terminal indicated at 41. This analog audio signal is converted into PCM by the A/D converter 42.
converted into an audio signal. Output data of the A/D converter 42 is supplied to an adder 43. The adder 43 contains an address.

Block address signal and ID from ID generation circuit 44
These block address signals and I
A D signal is added to the PCM audio signal.

The output signal of the adder 43 is used as data input to the RAM 45 and RAM 46. Each of the RAMs 45 and 46 has a capacity to store one frame of symbols of a code structure. An address generation circuit 47 and a timing generation circuit 48 are provided in association with the RAMs 45 and 46, and are controlled to write and read data in the RAMs 45 and 46 in symbol units. Two RAM45
and 46 are hooks for reading data from one RAM and encoding the error correction code during a period when data is being written to the other RAM. Furthermore, the RAMs 45 and 46 perform time axis compression processing.

The audio PCM signal read from one of the RAMs 45 and 46 is supplied to a CI code and C2 code encoder 50 to form parity of the C1 code and C2 code, and this parity is written into one of the RAMs 45 and 46. A product code is used as an example of an error correction code. That is, the data arranged vertically in a two-dimensional array of PCM audio signals for one field period is encoded with CI code, and the data arranged horizontally in the two-dimensional array is encoded with C2 code. is encoded.

Reed-Solomon codes can be applied as the C1 code and C2 code. In addition, the parity generation circuit 49
is provided, and simple parity for error detection is formed for two symbols (two bytes) included in the header. When the error correction encoding process is completed, a digital signal consisting of a parity symbol, block address, 10 signals, and data is read out from the RAM 45 or 46 block by block, and is supplied to the parallel to serial converter 51, where it is converted into serial data. converted.

The output data of the parallel-to-serial converter 51 is supplied to an (8->10) i-key circuit 52, which is one of channel encoding. (8→10) modulation is a modulation method that converts 8-bit data into a 10-bit pattern with a small DC component (and easy bit synchronization on the playback side). A block synchronization signal from 54 and a pulse signal having a frequency of y2fch (fch: channel clock frequency after modulation) from terminal 55 are added.The output signal of adder circuit 53 is recorded at output terminal 57 via recording amplifier 56. It is extracted as a PCM signal.

C9 Recording Data Configuration A PCM audio signal recording area is formed on the head entry side of the magnetic tape track, followed by a color video signal recording area. Figure 1A shows the recording area of a PCM audio signal in one track.
The recording area of the audio signal is, in order from the beginning of the track, a margin area, a preamble area, a data area, and
The arrangement is such that the V-P guard is located in the postamble section. For example, in the case of the NTSC system, the length of each area is defined by the number of blocks and the tape winding angle, as shown below.

Margin area: 3° (10,5 blocks) Preamble section = 2° (7 blocks) Data section: at, 43
@(110 blocks) Postamble section: 2" (7 blocks) V-P guard: 2.57" (9 blocks)
Therefore, the total recording area for PCM audio signals is 4.
1.00'' (143.5 blocks).

In the data section, data is recorded in the block configuration shown in FIG. 1B. The length of l block is 44 bytes (the length of one symbol is 1 byte), and a 1-byte block synchronization signal (SYNC) is located at the beginning, followed by 2 bytes W1 . W2 is located, followed by 36 bytes of data, and finally 01 code parity. The block synchronization signal is (8→10
) It has a unique bit pattern that never occurs in the data after modulation. Wl is, for example, an ID signal. The ID signal identifies, for example, the NTSC system and CCIR system, emphasis on/off, sampling frequency, number of audio signal channels, and the like. W2 is
For example, it is a block address signal.

FIG. 1C shows details of the recording area of the PCM audio signal. In the margin area, a repeating pattern of the minimum inversion interval after (8→10) modulation is recorded. This repeating pattern has a frequency of 'Afch (fch: channel clock frequency).

For example, in the case of the NTSC system, the frequency fch is 105
6fh (fh: horizontal frequency), and 840fh in the case of the CCIR method. The seven blocks included in the preamble section each have the same block configuration as the data section. In addition, in the postamble section, “
A pulse signal with a frequency of /2 f ch is recorded. V
- No signal is recorded in P guard.

The first diagram shows the configuration of the signal in the preamble section. Each of the 7 blocks has a length of 44 bytes, with a block synchronization signal 5YNC located at the beginning, an ID signal corresponding to the next Wl, and a block address signal corresponding to W2 next. is located, and simple parity is added to the ID signal and block address signal.

A pulse signal with a frequency of %feb is inserted instead of data. The block address of the preamble section has continuity with the block address of the data section. In this example, since the block address of the data section is 1 byte and starts from 0, the addresses of the 7 blocks of the triangle section are set to increment as (249, 250, . . . , 255).

FIGS. 1E and 1F show other examples of the data structure of the preamble section. As shown in FIG. The latter two blocks have the same block configuration as the data. The block addresses of these two blocks are (254, 255).As shown in FIG. 1F, the data structure of the preamble section is W
The byte corresponding to l is set as zero data, the byte corresponding to W2 is set as a block address, and parity is added to these two bytes. 44 corresponding to data
All bytes are assumed to be zero data.

Wl in the block inserted in the above preamble section
An ID signal indicating that the block is in the preamble section may be inserted as a byte corresponding to the block.

d. Since both a pulse signal with a frequency of '/2 f ch and a block synchronization signal that is the same as the regular block interval are inserted in the processing preamble section on the playback side, the PLL pull-in operation and Block synchronization signals are well detected. FIG. 2 shows a part of the PCM reproduction processing circuit 36.

In Figure 2, the PCM reproduced at the input terminal indicated by 1
An audio signal is provided. This reproduced signal is supplied to a comparator circuit 3 via an equalizer circuit 2, and reproduced data in the form of a pulse waveform is obtained. As shown in FIG. 3A, this reproduced data has the same data structure as the recorded data, and one block has a length of (44×10 bits). The output signal of the comparator circuit 3 is supplied to the PLL 4, and the PLL
A clock signal of frequency fch synchronized with the reproduced data is obtained from L4.

A clock signal from PLL 4 is supplied to shift register 5, intra-block counters 6 and 8, and D flip-flop 7. The intra-block counters 6 and 8 and the block counter 16, which will be described later, have an interpolation circuit (not shown), so even if a clear pulse or load is not manually applied, these counters will be able to match the previous timing. It can run on its own. Shift register 5 is 10
It has a number of stages of bits, and reproduced data is taken into the shift register 5 in units of 10 bits by a clock signal. The 10-bit data taken into this shift register 5 is supplied to a (10→8) conversion circuit 9.

(10 → 8) The conversion circuit 9 converts the 10 channel bits into 8
It converts into data bits and detects the pattern of the block synchronization signal. (10→8) The conversion circuit 9 is composed of a ROM in which a data conversion table is stored. (
10→8) The 8-bit data generated from the conversion circuit 9 is supplied to the (n+od, 2) adder circuit 10.8-bit D flip-flops 11 and 12.

(10→8) The detection signal generated when the block synchronization signal is detected in the conversion circuit 9 is supplied to the D flip-flop 7, and the synchronization detection pulse Psy (Fig. 3B) synchronized with the clock formed by the PLL 4 is generated. It is generated from the D flip-flop 7. Detection pulse Ps generated for each block
y is supplied as a clear pulse to the intra-block counter 6 and the 8-bit D flip-flop 13.

After being cleared by the synchronization detection pulse Psy, the intra-block counter 6 counts clocks and outputs a clock pulse P ch 1 , a window pulse WN, and an address latch pulse Pad. Clock pulse Pchl
As shown in FIG. 3C, this signal has a frequency of 1/10 fah and is synchronized with two pieces of data W1, W2 and parity P included in the header after the block synchronization signal.

The window pulse WN is a pulse generated at the last timing of the header, as shown in the third diagram. The address latch pulse Pad is W2 as shown in FIG. 3G.
This is a pulse that occurs at a timing synchronized with .

A clock pulse Pchl is supplied to the D flip-flop 13 as a clock. The output signal of the adder circuit 10 is D
The output signal of the D flip-flop 13 is supplied to the parity check circuit 14 and fed back to the adder circuit 10. The contents of the D flip-flop 13 change as shown in FIG. Parity check circuit 14
generates an error flag EF which becomes high level when the above-mentioned addition result is zero, that is, when there is no error, and becomes low level when there is an error.

This error flag EF and the window pulse WN from the counter 6 are supplied to an AND gate 15. Therefore,
From AND gate 15, when there is no error in the header,
A synchronization detection pulse CPsy shown in FIG. 3F is generated. This synchronization detection pulse CPsy is supplied to the intra-block counter 8 as a clear pulse, and is also supplied to the block counter 16 as a load pulse. If there is an error in the header, the error flag EF becomes low level and the synchronization detection pulse CPsy is not generated.

The address latch pulse Pad generated by the intra-block counter 6 is supplied to the 8-bit D flip-flop 11, and therefore the 8-bit data W2 (block address) from the (10→8) conversion circuit 9 is supplied to the D flip-flop 11. It is latched as shown in FIG. 3H. W2 latched in D flip-flop 11 is block counter 1
6 and is loaded into the counter 16 by the synchronization detection pulse CPsy. When a correct block synchronization signal cannot be detected and the synchronization detection pulse CPsy is not generated, the intra-block counter 8 and the block counter 16 run free using the interpolated pulse signal.

The clock pulse from PLL4 is sent to counter 8 in the block.
A clock pulse Pch2 having a frequency of 1/10 fch is generated from the counter 8, and an output signal generated when the counter 8 counts one block of clock pulses is supplied to the block counter 16. As described above, the block address is loaded into the block counter 16 by the synchronization detection signal CPsy, and the contents of the block counter 16 are incremented by the output signal of the intra-block counter 8. As mentioned above, since a block address that is continuous with the data section is also inserted in the preamble section, the block address detected in the preamble section and stored in the D flip-flop 11 is stored in the block counter 16. loaded.

Further, the clock pulse Peh2 is shown in FIG. 3, and is supplied to the 8-bit D flip-flop 12 as a clock. The D flip-flop 12 has (10→
8) Since the output signal of the conversion circuit 9 is supplied, the D flip-flop 12 sequentially receives each byte of the data section of one block, as shown in FIG. 3J. D
The output data of the flip 7+o tube 12 is output to the system bus 18. A RAM 19 for data storage is connected to the system bus 18 .

The intra-block address generated by the above-mentioned intra-block counter 8 and the block address generated by the block counter 16 are supplied to the RAM controller 17. RAM
The controller 17 controls writing/reading, addressing, etc. of the RAM 19. Similar to the recording side, the RA
M19 has a double bank configuration. Furthermore, a configuration in which the RAM is shared between the recording side and the reproducing side is also possible.

e. Modifications The present invention can also be applied to a digital audio recorder that records only PCM audio signals on tape using a rotating head.

Furthermore, the present invention can also be applied to recording/playback of digital video signals.

[Effects of the Invention] In this invention, P is added to the preamble section before the data section.
Since the pulse signal of the highest frequency for LL pull-in and the block synchronization signal at the regular block interval are recorded, the PLL pull-in operation can be performed without any problem, and the interpolation of the block synchronization signal can be performed from the beginning of the data interval. It can be carried out. Even if the block synchronization signal cannot be detected at the beginning of the data interval, if the block synchronization signal is detected in the preamble interval, a detection signal interpolated at the correct timing can be obtained in the block period, so playback Data is processed correctly.

Further, in the present invention, since a block address continuous with the data section is inserted into the preamble section, it is possible to interpolate the block address from the beginning of the data section, and the block address can be sufficiently protected.

[Brief explanation of the drawing]

Fig. 1 is a route diagram showing the structure of recorded data in an embodiment of the present invention, Fig. 2 is a block diagram of a part of the processing circuit on the playback side, and Fig. 3 is a timing diagram used to explain the processing circuit on the playback side. 4 is a block diagram of a recording and reproducing circuit of a VTR to which the present invention can be applied, FIG. 5 is a timing chart used to explain the recording and reproducing circuit, and FIG. 6 is a block diagram of an example of a PCM recording processing circuit. Explanation of main symbols in the drawings 1: Reproduction signal input terminal, 4: PLL. 6.8: Intra-block counter, 9: (10→8) conversion circuit, 14: Validity check circuit, 16: Block counter.

Claims (6)

[Claims] (1) In a digital information signal recording device in which a digital information signal is discontinuously recorded on a recording medium, a preamble section is provided before the data section in which the digital information signal is recorded, and the preamble section is provided with a preamble section. A digital information signal recording device characterized in that a repeating pattern with a minimum inversion interval after modulation and a block synchronization pattern with a regular interval are recorded. (2) Claim (1) characterized in that a repeating pattern with a minimum inversion interval after modulation is recorded at the beginning of the preamble section, and a block synchronization pattern is recorded at regular block intervals after the repeating pattern. The digital information signal recording device described above. (3) A digital information signal characterized in that a block synchronization pattern is recorded in the preamble section at regular block intervals as a whole, and after the block synchronization pattern, a repeating pattern with a minimum inversion interval after modulation is recorded, respectively. Recording device. (4) The digital device according to claim (1), wherein additional data is inserted in the preamble section together with a block synchronization pattern, and the additional data is subjected to error detection or encoding with an error correction code. Information signal recording device. (5) A block address signal is inserted in the preamble section together with a block synchronization pattern, and the block address signal is continuous between the preamble section and the data section. 1) The digital information signal recording device as described above. (6) The digital information signal recording device according to claim (1), wherein the repeating pattern of the minimum inversion interval after modulation is half the frequency of the channel clock after modulation.