KR910002346B1 - Switching circuit of mono and multi track - Google Patents

Abstract

The circuit equips a fixed head multi/track circuit (1) and a rotary head monotrack circuit (2) on an error correction digital signal processor (DSP) to record/reproduce the audio or video signal to/from any kind of recording medium. A demultiplexer (A) is a circuit drived by a mode control signal (MC) and 8 bit encoder data of the DSP. A modulation circuits (B1-2) modulate the outputs (X0-1) of the demodulator. A track separation circuit (C) separates into 20 tracks the modulator (B1) output data which is recorded on the recording medium by driving the fixed head multitrack tape (MTT) with a driver (D).

Description

Mono / multitrack switching circuit

1 is a block diagram of the present invention.

2 is a detailed circuit diagram showing an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

DSP: Error Correction Circuit MSC: Mode Switching Circuit

A: Demultiplexer B ₁ , B ₂ : Modulation circuit

C: Track Separation Circuit D: Driver

E ₁ , E ₂ : data and clock reproduction circuit F ₁ , F ₂ : time axis correction circuit

G: demodulation circuit H: multiplexer

I: Frequency conversion circuit J: Synchronization generator

K: Video level L: Synchronous detection and demodulation circuit

M ₁ , M ₂ : Power control MC: Mode control circuit

A: Fixed head multi track part B: Rotating head mono track part

The present invention relates to a mono / multitrack switching circuit, and more particularly, to record and play an audio or video signal by selecting a mono / multitrack using an error correction circuit (Digital Signal Processing DSP). The present invention relates to a mono / multitrack switching circuit.

In digital audio or digital video system, the data transmission rate is very high. Therefore, if the fixed head is used as the recording medium of the audio signal, the multi track is used. If the rotating head is used, the mono track is used. Play it.

Conventionally, the error correction circuit (DSP) cannot be efficiently used because a single recording medium mono or multitrack is connected to one error correction circuit (DSP).

The present invention has been made to solve the problems of the prior art as described above, by using a fixed head multitrack unit and a rotating head monotrack unit in a single error correction circuit to efficiently use the error correction circuit and mono and multitrack It is an object of the present invention to provide a mono / multitrack switching circuit for controlling and recording and reproducing audio or video signals on any recording medium.

In order to achieve the above object, the present invention provides an error correction circuit for error correction and correction of data by comparing input and output data, and a demultiplexer to which encoder data output from the error correction circuit is input and synchronized by a mode control signal. The first and second modulation circuits for modulating and outputting the data output from the output terminal of the demultiplexer, and the track separation circuit and the track separation circuit separated into 20 tracks by inputting the data output from the first modulation furnace into 20 tracks. A driver for driving the fixed-head multitrack and recording the separated data to a recording medium; first, synchronously detecting data by reading the data from the fixed-head multitrack and the rotating head monotrack and separating the signal into audio signal data and clock pulses; The second data and clock regeneration circuit and the data and clock pulses to input the error correction circuit. The demodulation circuit for demodulating the data output from the first time axis correction circuit in the first and second time axis correction circuits for correcting the time axis, and the data output from the demultiplexer are modulated in series through the second modulation circuit so that the frequency of the data is A frequency conversion circuit for converting, a synchronization generating unit J for generating vertical and horizontal synchronization pulses and applying a frequency to the converted data, and a video level for adjusting the input pulses and applying them to the mono track, and second data and clock reproduction. It consists of a synchronous detection and demodulation circuit which is separated into data and clock through circuit, and then synchronously detected and demodulated, and a multiplexer which converts data into decoder data in fixed head multitrack and rotating head monotrack and inputs it into error correction circuit. Provide a mono / multitrack switching circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of the present invention. When the error correction circuit (DSP) records digital audio or video data on a magnetic tape, a large number of errors occur unlike a compact disc. Corrects an error and controls the system by exchanging encoder data and decoder data with the mode switching circuit, and the mode switching circuit MSC is controlled by the mode control signal MC. This circuit is operated by selecting the fixed head multitrack unit and the rotating head monotrack unit.

2 is a detailed circuit diagram showing a preferred embodiment of the present invention, in which error correction (DSP) is a circuit for error correction and correction of data as shown in FIG. 1 and demultiplexer (A) is an error correction circuit (DSP). a circuit which is driven by the 8-bit encoder to enter the data mode, the control circuit signal (MS) that is output from a modulation circuit _{(modulation, B 1, B 2} ) is an output terminal (X _0, X ₁₎ of the demultiplexer (a) The data output from the modulated data is outputted, and the track separation circuit (C) inputs the data output from the modulation circuit (B ₁ ) and divides the data into 20 tracks. A device for recording a recording medium by driving a fixed-head multitrack tape (MTT) with data separated by 20 tracks in C).

The data and clock regeneration circuits (E ₁ , E ₂ ) read data from the fixed head multitrack and the rotating head monotrack to separate the audio signal data and the clock pulse to perform synchronous detection, and the time base corrector (F) ₁ , F ₂ ) inputs data and clock pulse to correct the time base. The demodulation circuit (G) demodulates and outputs the data output from the time base correction circuit (F ₁ ), and the frequency conversion circuit (I) removes the data output from the output terminal (X ₁ ) of the demultiplexer (A). The modulator J modulates the input data by modulating in the two modulation circuits B ₂ and outputs the frequency. The synchronous generator J generates vertical and horizontal synchronous pulses to be synthesized with the frequency-converted data. Is input to the input terminal (V _in ) of the VTR by adjusting the input pulse and converting it into a video input signal form. The synchronous detection and demodulation circuit (L) is a data and clock in the data and clock regeneration circuit (E ₂ ). A circuit for synchronously detecting and demodulating a separated input signal.

In the multiplexer H, data input from the fixed head multitrack unit A and data input from the rotating head monotrack unit B are input to the input terminals X ₀ and X ₁ to convert the decoder data into an error correction circuit ( The first power controller (M ₁ ) is a circuit for outputting to the DSP, and the first power controller (M ₁ ) is a power supply unit for supplying power to the fixed head multitrack unit (A) when the mode control circuit (MC) is "low level". (M ₂ ) is a circuit for supplying power to the rotating head mode track section ( _b ) when the mode control circuit MC is at "high level".

Here, the operations of the first and second power controllers M ₁ and M ₂ are alternately used for the purpose of switching power.

The effect of the present invention configured as described above will be described in detail.

When the mode control circuit MC is " low level ", the fixed head multitrack portion A is driven. That is, since the "low level" is applied through the inversion gate NOT, the fixed head multitrack unit is driven, while the "low level" is applied to the second power controller M ₂ so that the rotating head monotrack is applied. The part (b) is not driven.

The encoder data output to the error correction circuit DSP is input to the first modulation circuit B ₁ via the demultiplexer A, modulates the data, and is separated into 20 tracks in the track separation circuit C. It is applied to the fixed-head multitrack tape (MTT) through the data is stored in the recording medium.

At the time of reproduction, the signal reproduced at 20 tracks is divided into the data and the clock by the first data and the clock regeneration circuit E ₁ , and then applied to the first time side correction circuit F ₁ to restore the time base correction suitable for the error correction circuit. It is input to the input terminal X ₀ of the multiplexer H through the inquiry path G. Since the data input to the multiplexer H is converted into decoder data and input to the error correction circuit DSP, error correction may be performed.

If the mode control circuit MC is "high level", the first power controller M ₁ is supplied with a "low level" through the inversion gate NOT so that the power supply is cut off, so that the fixed head multitrack unit is driven. the output terminal of the not without, the second rotary head mono track portion (B) is powered by a power controller (M ₂₎ are driven encoder data output from the error correction circuit (DSP) is a demultiplexer (a) (X ₁ Is input to the second modulating circuit B ₂ .

The data input to the second modulation circuit B ₂ is modulated into serial data and input to the frequency conversion circuit I to convert frequencies.

When the frequency converter circuit I applies the horizontal and vertical synchronization pulses synchronized by the synchronization generator J to the signal whose frequency is converted, it is stored at the video level K to drive the rotating head monotrack.

Here, the video level K is a video signal format converter, and Vin and Vout are general video input / output terminals.

During reproduction of the rotating head monotrack, the video output signal Vout of the VTR is separated into data and clock by the second data and clock reproduction circuit E ₂ and applied to the synchronous detection and demodulation circuit L. FIG.

When the separated data and clock are applied to the synchronous detection and the second time axis correction circuit F ₂ by the synchronous detection and demodulation circuit L, the error correction circuit performs appropriate time axis correction.

The time-base corrected data is applied to the input terminal X ₁ of the multiplexer H, converted into decoder data, and then input to the error correction circuit DSP.

As described above, according to the present invention, since the error correction circuit portion is very large, a mode switching circuit is provided in the middle without using two error correction circuits, so that the fixed head multitrack and the rotating head multitrack and the rotating head are used. There is an advantage that recording / playback of a mono track is possible.

Claims (1)

Error correction circuit (DSP) for error correction and correction of data by comparing input / output data, demultiplexer (A) and demultiplexer (A) to which encoder data output from the error correction circuit is input and synchronized by the mode control circuit (MC). A track in which the data output from the first and second modulation circuits B ₁ and B ₂ and the first modulation circuit B ₁ for modulating and outputting data output from the output terminal of A) are separated into 20 tracks. A driver (D) for driving the fixed head multitrack to record data separated and separated into 20 tracks by the separation circuit (C) and the track separation circuit (C) on a recording medium, and the multitrack for the fixed head and the rotating head mono First and second data and clock reproducing circuits E ₁ and E ₂ which read data from the track and separate them into audio signal data and clock pulses for synchronous detection, and a time base suitable for an error correction circuit by inputting data and clock pulses. Data output from the demodulation circuit G and the demultiplexer A, in which the first and second time axis correction circuits F ₁ and F _{2 to be} corrected, and the data output from the first time axis correction circuit F ₁ are demodulated. Is modulated in series through the second modulation channel B ₂ to convert the frequency of data, and the synchronization generator J generates vertical and horizontal synchronization pulses and applies them to the frequency-converted data. And a video level (K) for adjusting the input pulse and applying it to the mono track, and a synchronous detection and auxiliary circuit which is separated into data and clock through the second data and clock regeneration circuit (E ₂ ), and then synchronously detected and demodulated. (L) and a multiplexer (H) for converting data input from the fixed head multitrack and the rotating head monotrack into decoder data and inputting the error correction circuit (DSP). Switching circuit.

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