JPS58194117A - Synchronizing system of digital signal recording - Google Patents

Abstract

PURPOSE:To attain accurate detection of synchronism at a PCM signal period, by inserting a synchronizing signal similar to that added to each PCM signal to be recorded in a clock locking signal. CONSTITUTION:In recording a picture signal and an audio signal in a VTR, the audio signal is pulse-code-modulated at each field of the picture signal and recorded with time compression. The clock locking signal is provided for the beginning of a PCM signal group at each field period to take synchronism at the reproduction. Plural synchronizing signals SYNC same as those added to each PCM signal and address signals ADRS-1-ADRS-4 succeeding to each PCM signal are inserted in the locking signal. The synchronism of each frame of the accurate PCM signal is taken based on the correlation between the front and rear locations of the synchronizing signals and the address signals at the reproduction.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the recording, reproduction and transmission of digital signals, and in particular to a digital signal synchronization method characterized by reliably performing synchronous reproduction of digital signals during reproduction or on the receiving side. As an example of the conventional example, when rotating
An example of throat health scan will be explained below.0 A method in which the audio signal is compressed on the time axis for each field period and recorded on a recording track that is an extension of the recording track of the video signal using rotation and throat. has already been proposed.0 FIG. 1 is an explanatory diagram showing recording and ζ-turns on a magnetic tape in a specific example of this method. Note that this specific example is an example of a Hercal scan method in which recording and reproduction are performed using a rotating cylinder to which two magnetic nodules are attached.

Figure 2 is. This is an explanatory diagram showing a state in which a magnetic tape is wound around a rotating cylinder. As shown in the figure, two magnetic heads H1 and H2 are placed at positions directly opposite to each other with respect to the center of the rotating cylinder. Signals are recorded and reproduced every one field period by alternately using the magnetic node H1 and the magnetic node H2. The audio signal is time-base compressed for each field period, and immediately after recording the video signal,
Same as recorded by Rad. Therefore, a recording pattern as shown in FIG. 1 is obtained.

In Fig. 1, A shows the trace recorded by the rotating head, B shows the scanning direction of the rotating head, and C shows the recording band of the video signal.
D indicates the recording band of the audio signal, E in Fig. 2 indicates the rotating cylinder, F indicates the magnetic tape, G indicates the guide post, H indicates the recording section of the video signal, and F indicates the recording section of the audio signal. , ■ indicate the rotation direction of the rotating cylinder, and θ indicates the angle at which the magnetic tape is wound around the rotating cylinder E.

FIG. 3 is a time chart for explaining temporal operations. 3a shows that the input video signal is divided into 1 field periods and each signal is divided into 1. ■2. v3...
. . ., b divides the input audio signal into every field period, and divides each signal into A1 . A2゜A・・・・・・
..., where C is the magnetic head H
1 and b indicate signals recorded and reproduced by the magnetic head H2, and e indicates a reproduced signal.

For example, the audio signal A1 in the first field period is time-base compressed and converted into a signal A', which is recorded at a timing such as C by the magnetic head H1 immediately after the video signal v1 in the first field period. The audio signal A2 of the 0th order second field period is similarly compressed on the time axis and becomes A'
2 and recorded by the magnetic herad H2 immediately after the video signal v2 in the second field period. In this way, the audio signal A3 after the third field period.
A4゜A6... are similarly compressed on the time axis and converted into signals of AI, A'4゜A'6..., which are alternately applied to the magnetic field and by Rad H1 and H2. To,
Recorded at timings c and d.

During playback, each signal is played back at timings such as c and d, similar to when recording, and the signal A'+*"-" from each head is
a... are the signals A; , AS! on the original time axis after the time axis has been expanded, respectively. , A, .

For example, a frequency f8 that is more than twice the highest frequency of the audio signal
The audio signal is sampled using the sampling signal of This is done by using a clock signal with a higher frequency, f, to read it out faster. Conversely, time axis expansion during playback is performed by writing into the memory at high speed using a clock signal of frequency f'8 and reading at a slower speed using a clock signal of frequency f8. The memory capacity of the memory is PCM for one field period.
For example, if the number of samples in one field period is N and the storage address is 1-N, then in the PCM signal in one field period, The PCM signal of the first sample is written to the first address, the PCM signal of the second sample is written to the second address, etc., the PCM signal of the Nth sample is written to the Nth address, and when reading, sequentially from the first address Read out.

Now, during reproduction, when the first sample of the PCM signal (for example, the first sample of the PCM signal of the signal A'1) is reproduced, it is necessary to write this signal to the first address of the memory. By the way, the reproduction timing of the PCM signal of the first sample fluctuates in time due to time axis fluctuations that occur in the magnetic recording and reproduction system of the reproduced signal that has been magnetically recorded and reproduced.

Therefore, the timing of writing to the first address (writing start timing) also needs to be changed in accordance with this variation. In other words, to do this, it is necessary to detect this writing start timing.

In normal recording and playback of PCM signals, in order to perform timing detection as described above, synchronization signals are converted into PCM signals at the time of recording.
This synchronization signal is inserted into the signal, and during playback, this synchronization signal is detected, and the timing of the PCM signal is fixed based on the detection timing of this synchronization signal.

FIG. 4 is an explanatory diagram illustrating the timing of a PCM signal into which a conventional synchronization signal is inserted. Note that this PCM signal is an example of a time-base compressed signal (eg, signal A7) in the embodiment of FIG.

In FIG. 4, the first part of the signal includes a clock pull-in coarse signal A for obtaining the reproduced clock signal necessary for reproduction, followed by the first synchronization signal, and later the PCM signal of the first frame. be.

In each subsequent frame, the synchronization signal and the PCM signal are arranged alternately in time series.

In normal PCM recording and playback, multiple sample PC
M signal, error detection signal and correction signal for detecting and correcting errors occurring in the recording/reproducing system, and synchronization signal.
The frame is configured.

In the example of FIG. 4, the error detecting signal and the error correcting signal are not the object of the present invention, but are well-known signals, and therefore will be omitted for ease of explanation.

When reproducing a normal PCM signal, a reproduced clock signal whose phase is synchronized with the reproduced signal is obtained using the reproduced signal, and this signal is used to perform signal processing during reproduction.

Obtaining this reproduced clock signal is called self-clocking, and normally a PLL (phase locked loop) is used to obtain a reproduced clock signal that is phase-synchronized with the reproduced signal. By the way, in the case of a temporally intermittent signal as in the example shown in FIG. 4, the phases of the reproduced signal and the reproduced clock signal are completely synchronized with respect to the signal start point due to the delay in the temporal response of the PLL. A predetermined time (phase synchronization pull-in time) is used until Therefore, in order to ensure that the reproduced clock signal is completely phase-synchronized in the PCM signal part, the PCM
Immediately before the signal starts, a clock pull-in coarse signal A having a period of the predetermined time is added and recorded. Note that this clock pull-in coarse signal A usually has a predetermined relationship with the bit period and phase of the PCM signal, and uses a signal of a constant frequency.

The synchronization signal port is used to detect the timing of the PCM signal during reproduction, and to generate a control signal for error detection when error detection is performed on a frame-by-frame basis. In particular, in the case of a signal that is intermittent in time as in the example in Fig. 4, it is necessary to detect the start timing of the PCM signal, and for this timing detection, the first synchronization signal in the first frame becomes important. For example, by detecting the first synchronization signal, the PCM signal of the first sample immediately after that starts to be written to the first address of the memory, and thereafter, the memory address is incremented by 1 for each sample, and the memory is sequentially written. After writing to address N is completed, a clock signal of sampling frequency f8 is used to sequentially read from address 1 to address N, which is similar to the PCM signal before time axis compression during recording. A reproduced PCM signal is obtained. This reproduced PCM signal is then D/A converted by a D/A converter to obtain a reproduced audio signal.

By the way, due to errors occurring in the recording/reproducing system, this first
If the second synchronization signal is not detected but is detected from the second synchronization signal, the P immediately after the second synchronization signal
This causes the inconvenience that the CM signal is erroneously written to the first address of the memory, regarding it as the first sample PCM signal. Also, if an error occurs in the clock pull-in signal and it happens to become the same signal as the synchronization signal, the signal immediately after this erroneously detected signal will be erroneously written to the first address. . In other words, if a signal other than the first synchronization signal is mistakenly detected first, all the signals for one field period will be incorrectly written to memory, which is a very long - field period. Since the period is incorrect, the sound quality of the reproduced audio signal is greatly deteriorated.

Therefore, it is necessary to write a predetermined sample of the PCM signal to a predetermined address (hereinafter referred to as addressing).

A method for accurately performing this addressing is to insert an address signal that has information for identifying the number of the synchronization signal immediately after the synchronization signal during recording, and then insert this address signal during playback. There is a method for accurate addressing depending on the information possessed. FIG. 6 is an explanatory diagram of an example in which this address signal is inserted. The difference from the example in FIG. 4 is that the address signal is inserted immediately after the synchronization signal of each frame.

This address signal includes, for example, the information 1'' in the address signal of the first frame.

The address signal of the second frame contains the information “2”,
・・・・・・・・・The address signal of the Nth frame is “
An address signal having information "N" is used.

Then, during playback, the information contained in this address signal (
Addressing is performed accurately using the same numerical information as the frame number. Therefore, as described above, even if the first synchronization signal is not detected at the beginning, if the second synchronization signal is detected, the address signal of the second frame is used to detect the 27th L/- frame and the subsequent frames. frames can be addressed accurately, and the inconvenience of audio signal errors during one field period as described above is greatly reduced.

However, even with this method of using address signals, if the synchronization signal is detected incorrectly, the information possessed by the address signal is obtained based on this synchronization signal, so it is difficult to accurately obtain the information possessed by the address signal. This will result in incorrect addressing. Therefore, it is important to accurately detect the synchronization signal.

Synchronous signal detection errors include non-detection errors and pseudo-detection errors. A non-detection error is an error that occurs when a synchronization signal should be detected but is not detected due to an error in the synchronization signal. A false detection error is an error in which an error occurs in a portion that is not a synchronizing signal and happens to be the same as the synchronizing signal, and a synchronizing signal is detected even though it is not a synchronizing signal. Another pseudo-detection error is not a signal error, but an error that occurs when there is a signal that happens to be the same as the synchronization signal in an address signal, PCM signal, clock pull-in signal, etc. other than the synchronization signal.

One way to improve undetected errors is to use frame correlation. This method takes advantage of the fact that a synchronization signal exists for each frame period, and if there is a non-detection error, the detection signal of the synchronization signal of the previous frame is delayed by one frame period to compensate. .

This method is hereinafter referred to as the interpolation method. Although this interpolation method is an effective method for improving non-detection errors, if there is a false detection error, Since there should be no synchronization signal at the time one frame later than this point, an erroneous detection signal is generated at this point as well, and based on this erroneously generated detection signal, the synchronization signal is further delayed by one frame. An erroneous detection signal is also generated. Then, an erroneous detection signal is sequentially generated for each frame. First, although this interpolation method is effective against non-detection errors, it has the opposite effect of increasing pseudo-detection errors when they occur. Therefore, it is not preferable to use this interpolation method alone, and it is used in combination with the restriction method, which is a method for improving false detection errors.

This restriction method also uses frame correlation, and sets an invalid period and a valid period based on the synchronization signal detection signal at a certain point in time, and even if a synchronization signal is detected during the invalid period, it will not be detected. This is a method in which detection is disabled and only detection during the validity period is enabled. Note that the invalid period is a certain point in time t. Based on the detection signal at time t. , the period is defined as the period (11-Δt) which is a predetermined error period Δt before the next time t1 delayed by one frame period, and the effective period is (
11-Δt) to (11+Δt). This error period Δt takes into consideration the phase synchronization error of the reproduced clock signal, and if self-clocking is performed accurately,
Since the number of regenerated clocks in one frame period is constant, by counting this regenerated clock signal, the timing t1 at which the next detection should be performed can be accurately set, and Δt
may be zero.

However, it is normal for dropouts to occur in normal recording/playback systems, and during this dropout period, the PLL
is in a free run state, and there is a possibility that the phase of the reproduced signal and the reproduced clock signal will shift during this period.

This phase shift is determined by the free run frequency stability of the PLL and the dropout period, and the Δt is set in consideration of these factors. Note that a detailed explanation of this Δt is omitted since it is not the main focus of the present invention. By using this restriction method, false detection errors are greatly improved.

As described above, the detection error of the synchronization signal can be greatly improved by the improvement method using both the interpolation method and the restriction method. However, when detecting a synchronization signal from temporally intermittent signals,
This improvement method alone is still insufficient.

For example, in detecting the first synchronization signal, since it is an intermittent signal, the detection signal of the previous frame cannot be used, and neither the interpolation method nor the restriction method can be used. This is because the synchronization signal immediately before the first synchronization signal is the last synchronization signal of the intermittent signals before the 17' field period.

Therefore, a three-mode method is used, which will be further explained next.

This three-mode method is a method of temporally switching between three modes: standby mode, supplementary mode, and steady mode. In the standby mode, an intermittent signal (in the example shown in Fig. 3, a time axis compressed signal Kinuta, etc.) is used.
This is a mode in which all operations for synchronization detection are stopped during periods other than the (equivalent to) period. Acquisition mode is a mode in which a capture start signal is generated immediately before an intermittent signal to transition from standby mode, and a mode in which the first synchronization signal is captured. mode. In the steady mode, a detection signal is obtained using the above-mentioned interpolation method and restriction method based on the detection signal of the first synchronization signal captured in the acquisition mode, and the mode shifts to the standby mode in response to the detection end signal. As described above, in the three-mode method, the standby mode, capture mode, and steady mode are sequentially transitioned in time and are repeated, thereby effectively performing synchronization signal detection during the intermittent signal period.

Note that in the acquisition mode, the interpolation method and the limit method are prohibited, and only the synchronization signal detection operation is performed at 1, when the first synchronization signal is detected. Therefore, in this acquisition mode, if a false detection is made due to an error in a part other than the synchronization signal, in the subsequent steady mode, the intermittent signal period, Erroneous detection signals will be generated sequentially. This is 1
This causes an error in the reproduced audio signal during the field period, which is inconvenient for the son-in-law. On the other hand, if detection is performed accurately in this acquisition mode, the interpolation method and limit method in the steady mode will work effectively, and even if considerable non-detection errors and false detection errors occur, these improvement methods will reduce the resulting Detection errors are greatly reduced.

Therefore, in acquisition mode, it is important to perform the initial synchronization signal detection accurately. In this acquisition mode, interpolation and limiting methods cannot be used as described above, so other improvement methods must be used. A multiple detection method is an effective method for improving this. This method is
This method generates a detection signal when several conditions are met simultaneously. For example, instead of making the first detection the final detection, the final detection is made even when a detection is made one frame later than the first detection. be. in this way,
If the first detection is a pseudo error, no detection error will occur unless the next detection, which is delayed by one frame, is a pseudo error.

Normal pseudo-errors are random, and the probability of pseudo-errors occurring at the same time in parts separated by one frame period is extremely small compared to a method that performs single detection. The multiple detection method is a very effective method.

Furthermore, there is also a method using the address signal explained in FIG. In this method, final detection is determined when the following conditions are further satisfied in addition to the above conditions. This condition is that the value obtained by adding 1 to the numerical information (for example, 3) possessed by the address signal at a certain point in time (4 in this case) is equal to the numerical information possessed by the next address signal (4 in this case). It is. If the address signal is also used as a condition in this way, detection in capture mode can be carried out quite accurately.

By the way, in this multiple detection method, the probability of detection error decreases as the conditions are increased, but since detection is performed when all the conditions between signals spanning between frames are satisfied, it is more effective than single detection. , the detection is delayed by the maximum time between signals spanning between frames. Further, if even one of the conditions is not satisfied due to an error, no detection is made, so if there are many errors, it is difficult to detect them, and there is a tendency for them to be detected even later.

By the way, the signal that can be considered accurate as a reproduced PCM signal is the signal after this first detection, and since the synchronization signal has not been detected for the signal before that, it cannot be considered as an accurate signal.

Therefore, in order to effectively use the multiple detection method, it is necessary to insert a synchronization signal from an earlier point in time to each frame in which the PCM signal begins, for a frame period corresponding to the detection delay. For example, if detection is delayed by this period, the time point at which the mode shifts to the steady mode is the time point at which the synchronization signal of the frame where the PCM signal starts, and the PCM signal will be accurately reproduced.

In the present invention, a synchronization signal is inserted into the clock pull-in signal for a period equal to or longer than the time delay, and the synchronization signal is captured in the frame structure where the PCM signal starts, and the synchronization signal is synchronized in the steady mode. Detection is PCM
The purpose is to accurately perform the signal period.

FIG. 6a is an explanatory diagram of a clock acquisition signal according to an embodiment of the present invention, and FIG. 6b is an explanatory diagram of a conventional clock acquisition signal. In Figure 6, "SYNC" is a synchronization signal, "ADH8" is an address signal, and "PCM" is a PCM
Show signal.

When using the conventional clock pull-in signal as shown in Figure 6, if independent detection is performed, the PCM of the first frame
It is possible to enter the steady mode from the signal, but in single detection, if there is a false detection error as described above, 1
This results in a signal error during the field period, which is very inconvenient. If a synchronization signal is inserted into the clock acquisition signal before the first frame as in one embodiment of the present invention, these synchronization signals can be used to generate a highly reliable synchronization signal using the multiple detection method described above. The detection time delay, which is a drawback of the multiple detection method, can be kept within this period. Note that since a synchronization signal is inserted into the clock pull-in signal to create a frame structure, an address signal is also added accordingly, but only the address signal may be added from the first frame.

An embodiment of the present invention will be described in detail with reference to the drawings.

As an example, a case of recording and reproducing an audio signal as described in FIGS. 1 to 3 will be described, and a description of a video signal will be omitted since it is not the main focus of the present invention.

FIG. 7 is a block diagram of a recording system circuit according to an embodiment of the present invention. The audio signal input to audio signal input terminal 1 is A
The signal is applied to the /D converter 2, converted into a PCM signal, and applied to the changeover switch 6.

The A/D converter 2 is supplied with a sampling signal from a sampling signal generation circuit 3, and the audio signal is sampled by this sampling signal and converted into a PCM signal for each sample. It is assumed that the frequency of this sampling signal is 30 kHzC', and the number of quantization bits of the PCM signal is 10 bits.

On the other hand, the sampling signal is generated by the write address generation circuit 4.
The write address generation circuit 4 generates a write address signal having numerical information that increases by one each time this sampling signal is applied, and supplies it to the address changeover switches 9 and 1o. The numerical information contained in this write address signal changes from 1 to 600, and becomes 1 after 500. At this time, a clock signal is generated and applied to the flip-flop 5.

In the flip-flop 6, the state of the output signal changes from "L" to "H" every time this clock is applied.

A memory switching signal that changes from "H" to "L" is obtained, and the changeover switches 6, 12, address changeover switches 9, 10 . Given. These changeover switches 6.12 and 9.10 are switched so that when the memory changeover signal is in the H# state, the H side terminal is closed, and when the memory changeover signal is in the L'' state, the L side terminal is closed. As a result, the input PC
The M signal will be applied to the digital memory 7.8 alternately every 500 samples. Since the sampling frequency is 30 kHz, this period of 500 samples corresponds to a period equivalent to eoHz, and each period corresponds to one field period. On the other hand, these digital memo IJ-7, 8
A write address signal is applied to the address signal changeover switches 9 and 1o, and during the field period when the PCM signal is applied to each digital memory 7.8, the write address signal is applied synchronously. Since the signal is applied, as a result, 1 is sequentially written to addresses 1 to SOO for each sample, alternately every field period.

On the other hand, the other terminals of the address changeover switches 9 and 1o are given a read address signal from the read address generation circuit 11, and while one digital memory is writing, the other digital memory is reading and the result is As such, readout is also performed alternately every field period, and is switched by the changeover switch 12 to obtain one readout signal. Note that this read address signal is a signal having numerical information that increases by one each time a clock signal from the clock signal generation circuit 13 is applied. This numerical information also changes from 1 to 500'j, and becomes 1 after 60o. or,
Since this clock signal has a frequency ten times higher than the sampling frequency, the PCM signal written in the digital memory 7.10 is read out at high speed, and as a result, the changeover switch 12 receives the time-base compressed PCM signal. The signal will be obtained as an intermittent signal. Note that the read address generation circuit 11 is supplied with a control signal, and is controlled by this control signal so that the numerical information included in the read address signal increases intermittently over time. For example, from 1 to 10, each clock signal increases by 1, but after reaching 10, it does not increase for 2 clock periods, and from the next clock it increases by 1.
It increases continuously until it reaches 0, and after reaching 20, it repeats intermittent operation with an increase or no increase for 2 clock periods, and when it reaches 500, it stops until the next field period starts reading. Repeat 0 Such a two-clock period stopping operation is performed to insert a synchronization signal and an address signal, which will be described later.

On the other hand, the control signal generating circuit 1jlC is supplied with a lock signal as described above, and as shown in FIG. The control signal causes the changeover switch 1γ to close the a-side contact of the changeover switch 17 for the first clock period, close the a-side contact for the next clock period, and then close the a-side contact for the next clock period. In the 1o clock cycle, the repeating operation of 1 cycle is repeated at 12 clock cycles such as closing the contact on the b side for 66 cycles, and then stops, and when the recording signal start control signal for the next field is given, the same operation is performed. conduct.

On the other hand, the address signal generation circuit 16 is given a control signal from the control signal generation circuit 14.
At the time when the recording signal start control signal is given, it is reset (the numerical information of the output signal is 0), and at the time when the a side contact of the changeover switch 17 is closed, the numerical information of the output signal increases by 1. controlled as follows. The output signal is then given to the a-side terminal of the changeover switch 17.

On the other hand, a signal corresponding to a synchronizing signal is applied from the synchronizing signal generating circuit 16 to the a side of the changeover switch 17. The start time of the read address generation circuit 11 is determined by a control signal from the control signal generation circuit 14 so that the operation is delayed by 60 clock cycles (equivalent to 6 frames) from the time when the recording signal start signal is applied. Also, during this 60 clock cycle period, a read address signal having numerical information of zero is generated. During this period, digital memory address 〇〇 is read out, but information corresponding to the clock acquisition signal is stored at address 0, and the signal corresponding to the clock acquisition signal is read out. become.

As a result, a signal having a temporal arrangement as shown in FIG. 6 is obtained at the output of the changeover switch 17.

Next, this signal is converted by a parallel-to-serial converter 18 into one signal in which each digit signal is serialized in time, and is applied to a modulator 19 where it is modulated into a signal suitable for magnetic recording and reproduction. The recording signal is output to the recording signal output terminal 2o.

Although a detailed explanation will be omitted, this recording signal is appropriately switched together with the video recording signal to become the signals shown in Fig. 3c and d, and is sequentially recorded on the magnetic tape by two magnetic heads. Ru.

During reproduction, the signals reproduced from the two magnetic heads are
The signals are switched appropriately and separated into a video signal and a PCM recording signal, and a reproduced signal similar to that during recording is obtained.

FIG. 8 shows a reproduction system circuit according to an embodiment of the present invention.

The reproduced signal is transmitted via a reproduction input terminal 21 to a demodulator 22,
A self-clocking circuit 23 is provided with the self-clocking circuit 23.

The self-clocking circuit 23 generates a reproduced clock signal using the reproduced signal and supplies it to the write generation circuit 27. The demodulator 22 demodulates the reproduced signal to obtain a demodulated signal, which is input to the synchronization signal detection circuit 24 and the serial/parallel converter 26. The synchronization signal detection circuit 24 detects a synchronization signal, and uses this detection signal as a timing reference signal to convert the serial/parallel converter 2
6. Write address generation circuit 27. It is applied to the address signal detection circuit 25.

On the other hand, the demodulated signal is given to the address signal detection circuit 26, and using the detection signal from the synchronization signal detection circuit 24,
Address information included in the address signal is detected, and this address information is provided to the write address generation circuit 27 to synchronize address generation.

The serial/parallel converter 26 converts the signals into parallel signals and sends them to the reproduction PC.
The M signal is obtained and applied to the changeover switch 28. The changeover switch 28 is provided with a memory changeover control signal from the flip-flop 34 to alternately apply and write data to the digital memo +7 +29.30 every one fill-in period. On the other hand, the write address generation circuit 27 uses the detection signal from the synchronization signal detection circuit 24 and the address information signal from the address detection circuit 25 to generate a write address signal for writing the reproduced PCM signal given to the changeover switch 28 to a predetermined address. The address changeover switches 31.32 generate 1 and give it to the address changeover switches 31.32 in response to memory changeover control signals.
It is alternately switched every field period and applied to the digital memory to be written. The reproduced PCM written in the digital memory as described above
The signals are sequentially read out every field period by a read address signal (given via switches 31 and 32) from the read address generation circuit 35, and are alternately switched by the changeover switch 23, and are changed over time. becomes a continuous reproduced PCM signal, and the D/A converter 37
given to.

In the D/A converter 37, the reproduced PCM signal is D/A converted and becomes a reproduced audio signal, which is sent to the reproduced audio signal output terminal 38.
Note that the sampling signal generation circuit generates a clock signal having the same frequency as the sampling frequency, and supplies it to the read address generation circuit 35 and the D/A converter 37. The read address generation circuit 35 is a circuit similar to the write address generation circuit 4 during recording, and generates one clock signal for each field period and applies it to the flip 70 block 34.

In response to this clock signal, the flip-flop 34 generates a memory switching control signal whose output signal state changes every one field period. The reproduction system circuit will now be described. Next, the synchronizing signal detecting circuit 24, which is the main focus of the present invention, will be explained in detail. FIG. 9 is a block diagram of one embodiment of the synchronizing signal detecting circuit 24. The reproduced PCM signal from the demodulator 22 in FIG.
1 is given. This reproduced PCM signal is shown in Figure 6a.
This is a signal that includes a synchronization signal in the clock pull-in signal.

On the other hand, the capture start signal is applied to the set terminal of the S-R flip-flop via the capture start signal input terminal. Note that this capture start signal is a signal generated at the timing immediately before the clock pull-in signal. A rotational phase detector that detects the rotational phase of the rotating cylinder (general rotary head VTRs have this rotational phase detector to set the rotational phase of the rotating cylinder to a predetermined phase, and this is well known, so we will explain it here. It is generated based on the signal from the

The output of the S-R flip-flop changes from "low level" (hereinafter abbreviated as L) to "high level" (hereinafter abbreviated as H) at the time of the acquisition start signal.
1 outputs a "H" signal when a signal having synchronization signal information comes, and otherwise outputs a "L" Ω signal.Next, this output signal is sent to the one-frame delay circuit 42 and the AND circuit 43. The 01 frame delay circuit 42 provided at 48 obtains a signal obtained by delaying the input signal by one frame period.
The signal is applied to the ND circuit 43. The 1-frame delay circuit 42 and the AND circuit 43 cause both the signals before and after 1 frame to be "
Outputs a "H" signal only when the signal is "H", that is, only when synchronization signal information is detected in the signal before and after one frame.
Strengthen. Then, the time when "H" is output is the detection time of the above-mentioned acquisition mode, and it is necessary to shift from the acquisition mode to the steady mode.

This transition is made by the capture signal at AND circuit 43, via AND circuit 65, resetting SR flip-flop 45 and setting SR flip 70. In other words, since the SR flip-flop is reset, its output becomes II L #, and since that output is given to the AND circuit 65, no capture signal will be output from now on. Note that the capture signal is sent to the synchronization detection signal output terminal 54 via the OR circuit 51.
is output as the first detection signal. Furthermore, this capture signal is given to a limit signal generation circuit 52 and a one frame delay circuit 53. Based on this captured signal, the limit signal generation circuit 52 generates an H signal only during the valid period after the next frame.
” is generated and applied to the AND circuit 49 and the detection judgment circuit 56. On the other hand, the one frame delay circuit 63 delays the captured signal for one frame period, and in the case of a non-detection error in the next frame, On the other hand, the SR flip-flop is set by the acquisition signal, and its output becomes "H" and is given to the AND circuit 48, so that from this point on ( In the steady mode), the detection signal from the synchronization information detection circuit 41 is given to the AND circuit 9 and the detection signal discrimination circuit 66 via the AND circuit 48.Since the AND circuit 49 is given a limit signal, , only the detection signal in the valid period passes through and is applied to the changeover switch.In other words, false detection signals are removed.When a non-detection error occurs, the detection signal judgment circuit determines whether or not there is a detection signal in the valid period. If there is no detection, it will be considered as a non-detection error and the changeover switch 6o will be turned on.
The interpolation signal from the one-frame delay circuit 63 is output. Even if there is a non-detection error, the interpolated detection signal is output to the changeover switch 5o, and the OR circuit 61
is output to the synchronization detection signal output terminal 64 via
The limit signal generation circuit 62.1 is applied to the frame delay circuit 63 and is further used for detecting the next frame.

The steady mode is terminated by detecting the address signal and by resetting the SR flip-flop 47 via the termination signal input terminal.

The above is an explanation of the embodiments of the present invention. By using the present invention, a highly reliable synchronization signal is made possible by using the synchronization signal inserted into the synchronization pull-in signal, and the PCM signal In part, it is a curse to minimize the occurrence of errors due to synchronization pull-in delays.

[Brief explanation of drawings]

Figure 1 is a diagram showing a recording pattern on a magnetic tape showing an example of a time axis compression recording method for audio signals, and Figure 2 is a diagram showing a recording pattern on a magnetic tape showing an example of a time axis compression recording method for audio signals.
FIG. 3 is an explanatory diagram of the same operation. FIGS. 4 and 6 are diagrams schematically showing conventional recording signals. FIG. 6 is an embodiment of the present invention. FIG. 7 is a block diagram showing the basic configuration of the recording system in an embodiment of the present invention. FIG. 8 is a block diagram of the reproduction system. 1 is a block diagram of an embodiment of a synchronization signal detection circuit used in the present invention. 1...Input terminal, 2...A/D converter,
3...Sampling signal generation circuit, 4...
...Write address generation circuit, 5...Flip-flop, 6゜9.10, 12.17...Switch switch, 7゜8...Digital memory,
11... Read address generation circuit, 13...
... Clock generation circuit, 14 ... Control signal generation circuit, 16 ... Address signal generation circuit, 16 ... Synchronization signal generation circuit, 18 ...
...Parallel-to-serial converter, 19...-"Bottom\Modulator. Fig. 1 Fig. 2

Claims (1)

[Claims] A group of digital signals is divided into small groups, a synchronization signal is added to each small group for timing synchronization during playback, and the signals are arranged in chronological order so that the time intervals between the synchronization signals are constant. , Add a clock pull-in signal to obtain a lock signal that is necessary during playback immediately before recording on a recording medium, insert a synchronization signal similar to the synchronization signal into the clock pull-in signal and write it on the recording medium. 1. A synchronization method for digital signal recording, characterized in that timing synchronization is performed by using the temporal correlation of a synchronization signal inserted into the clock pull-in signal during reproduction.