JPH01254877A - Lsi tester - Google Patents

Abstract

PURPOSE:To improve a credibility for measuring data and to reduce the time by making a decision with a comparison for output data as an object and anticipated value data, in case a read-out address in a pattern data storing part is in coincident with the address settled beforehand. CONSTITUTION:The patterns for impressing an input and for an output anticipating value are written beforehand in the pattern data storing part 4. The input impressing pattern written-out from the storing part 4 is inputted to a device 7 to be tested after the wave for is arranged 6 in order. By a decision part 8 for the outputs comparison, the outputs decision is made for the output signal from the device 7 and the pattern of the output anticipating value. An enable signals group for the decision with the comparison is supplied to the decision part 8 by the comparison enable signal generating part 10 which consists of a storing part 11 for the comparison enable data, detection part 12 for the address accord, logical product means 13, storing part 14 for the comparison enable mask data and tri-state gate 15. Then, when the read-out address of the storing part 4 is in coincident with the address settled beforehand, the decision with the comparison is made for the output data as a object and the anticipated value data, and if not in coincident, the decision with the comparison is made for other output data and the anticipated value data.

Description

[Detailed description of the invention]

[Summary] Regarding the improvement of an LSI tester capable of measuring output delay time, the purpose is to improve the reliability of measurement data and shorten measurement time in measuring output delay time of LSI, and to improve the pattern data storage section. In an LSI tester, input data read from the pattern data storage section is given to the device under test, and output data from the device under test is compared with expected value data read from the pattern data storage section. If the read address matches a predetermined address, a comparison is made between the target output data and the expected value data, and if the read address of the pattern data storage section does not match the predetermined address, teeth,
The target output data and expected value data are not compared and determined, but other output data are compared and determined with the expected value data. [Industrial Application Field] The present invention relates to an improvement of an LSI tester capable of measuring output delay time. [Prior Art] FIG. 5 is a block diagram showing the configuration of a conventional tester. In the figure, 1 is a test processor, 2 is a pattern address generation section, 3 is a pattern generation control data storage section, 4 is a pattern data storage section, 5 is a timing generation section, 6 is a waveform shaping section, and 7 is a target Test equipment, 8 is an output comparison/determination section, 10 is a comparison enable signal generation section, 11 is a CP E
(Comparat. r Enable) Data storage section, 12 is an address match detection section, 13 is an AND circuit, 20 is a CPE window.
Each address storage section is shown. When executing a test, test processor l issues measurement instructions. Measurement commands are: (1) Turn on the power of the units in the tester related to measurement (2)
) Start of measurement (3) It means a series of commands to display the measurement result Pa5s/Fail. When executing the measurement command written on the program, the pattern address generator 2
It receives a start signal from the test processor 1, and starts from the start address set in advance in the program in the start address register and stop address register in the pattern address generator 2 to the stop address. are issued to the pattern generation control data storage unit 3 in order. Pattern generation control data storage section 3
The data in the pattern data storage unit 4 and the data in the pattern data storage unit 4 are stored in a one-to-one correspondence in the address direction, and the data in the pattern data storage unit 4 for the pattern address consisting of
The pattern data in is output based on the pattern control data in the pattern generation control data storage section 3 corresponding thereto. Input data 11 to I and expected value data (11 to o7) are stored at each address of the pattern data storage unit 4 (see FIG. 7). Input data read from the pattern data storage unit 4 The data 11 to 1 are waveform-shaped by the waveform shaping section 6,
Waveform shaped input data

[1 to I] are input to the device under test 7. Expected value data 0 to 07 read from the pattern data storage section 4 are output comparison judgment section 8
given to. The timing generator 5 generates input timing to be applied to the waveform shaping unit 6 and output timing to be applied to the output comparison and determination unit 8. Input timing exists for each input data,
Output timing exists for each output data. The position at which the input timing occurs is variable, and the position at which the output timing occurs is also variable. The output comparison/judgment section 8
The output is compared with the corresponding expected value data, and if they match, Pa5s is output, and if they do not match, Fail is output. The comparison enable signal generation section 10 includes a CPE data storage section 11, an address match detection section 12, an AND circuit 13, and the like. CPE data is stored in each address of the CPE data storage section 11. The relationship between CPE addresses and pattern addresses is shown in FIG. The CPE data has an n-bit configuration, and each bit corresponds to each expected value data. for example,
When the j-th output of the device under test 7 and the expected value data Oj are not compared, the j-th bit of the CPE data is set to “0”, and the j-th output of the device under test 7 and When comparing with the expected value data Oj, the j-th bit of the CPE data is set to "1". The address-defeat detection section 12 compares the read pattern address and the address output from the CPE window address storage section 20, and outputs "1" if the two match, and if they do not match, outputs "1". outputs "0". Although only one AND circuit 13 is shown in the figure, an AND circuit 13 exists for each expected value data. For example, the expected value data Oj
When "1" is output from the AND circuit 13 corresponding to . In addition, Fig. 5 shows T 320 manufactured by Atopan Test Co., Ltd.
This shows the configuration of an LSI tester called /23. When measuring output delay time on an LSI tester, the sixth
As shown in the figure, from the start cycle of the test pattern, the input signal and output signal of interest are in the state to be measured (in the example in Figure 6, the input ) is run until the measurement cycle that causes
The difference between the time when switching from aN to Pa5s and the state change time of input I is obtained as a delay time value t6. [Problem I that the invention seeks to solve] In order to obtain the delay time value, the LSI shown in FIG.
The tester's CPE window function is used, but since this mode only allows comparison of the shaded areas as shown in Figure 7, there is no possibility of comparing the device under test during the period from the start cycle to the measurement cycle. Since it is unclear whether the desired state change of the measurement cycle has been reached as a result of normal operation, the reliability of the measurement data has been compromised. The present invention was created in view of this point, and
In measuring the output delay time value of SI, the purpose is to increase the credibility of the measurement data and shorten the measurement time. [Means for Solving the Problems] FIG. 1 is a diagram showing the principle of the present invention. The LSI tester of the present invention includes a pattern data storage section 4 in which m-bit input application patterns and n-bit output expected value patterns are written in advance at each address, and m-bit input application patterns and n-bit output expected value patterns read from the pattern data storage section 4. A waveform shaping unit 6 that shapes a bit input application pattern and supplies the waveform-shaped m-bit input application pattern to the device under test 7 as an input signal, and an output signal from the device under test 7 and an expected output value of n bits. An output comparison/judgment section 8 that performs comparison/judgment with a pattern, a timing generation section 5 that provides input timing to the waveform shaping section 6 and output timing to the output comparison/judgment section 8, and n-bit comparison enable data at each address. a comparison enable data storage section 11 written in advance in the pattern data storage section 4; an address match detection section 12 that detects a match/mismatch between a read address for the pattern data storage section 4 and a predetermined address;
A comparison enable mask data storage section 14 in which n-bit mask data is written in advance, n tri-state gates 15, n AND means 13, and n
A signal line group S is provided for supplying the outputs of the AND means 13 to the output comparison/judgment section 8 as a comparison/judgment enable signal. The input of the i-th (i=1.2,...,n) tristate gate 15 has a comparison enable mask.
The i-th bit of the mask data read from the data storage unit 14 is input, and the tristate gate 1
The output of the address match detection section 12 is applied to the control terminal 5. The i-th bit of the comparison enable data read from the comparison enable data storage section 11 is input to one input terminal of the i-th AND means 13. The other input terminal of
The output of the i-th tristate gate 15 is input. [Embodiment] FIG. 2 is a block diagram of one embodiment of the present invention. In the figure, 14 indicates a CPE mask data storage section for the output OJ, and 15 indicates a tri-state gate circuit. Note that the same reference numerals as in FIG. 5 indicate the same parts. Output 0. In the CPE mask data storage unit 14 of
N-bit data is stored in which only the th bit is rQJ and the other bits are "1". As described above, the address match detection section 12 outputs "1" when the read pattern address and the address output from the CPE window address storage section 20 match, and outputs "1" when the two do not match. Outputs "0". The output of the address match detection section 12 is applied to the control terminal of the tristate gate 15. When "1" is applied to the control terminal, the tristate gate 15 becomes a high impedance state, and the lower input terminal of the AND circuit 13 is "1".
1” is applied. Under the condition that "0" is applied to the control terminal, the tristate gate 15 has an input r
□, it outputs "0", and when the input is "1", it outputs "1". Although only one AND circuit 13 is shown in the figure, there are n AND circuits 13. jth
The j-th bit of the data output from the CPE data storage section 11 is applied to the upper input terminal of the AND circuit 13 at the number slot. The figure shows a tri-state gate 15.
Only one is shown, tri-state gate 1
There are n pieces of 5. The j-th bit of the data output from the CP'E mask data storage section 14 is applied to the input of the j-th tristate gate 15,
The output of the j-th tristate gate 15 is applied to the lower input terminal of the j-th AND circuit 13. The output of the address match detection section 12 is applied to the control terminal of each tristate gate 15. In the present invention, as shown in FIG. 3, in the period from the start cycle to the measurement cycle, the output of interest is 0. The other outputs are compared with expected values using fixed position strobes. Also, as shown in FIG. 4, the entire portion indicated by the dotted line is compared. (Effects of the Invention) As is clear from the above explanation, according to the present invention, (a) the reliability of measurement data is improved; (1)) in any cycle during the measurement cycle; If the output comparison result is Fail, one measurement command is completed at that point, and execution of the next measurement command can be started, so that the measurement time can be shortened by that amount. This can produce a remarkable effect. 4. [Brief explanation of Figure (13)] Figure 1 is a principle diagram of the present invention, Figure 2 is a block diagram of an embodiment of the present invention, Figure 3 is a diagram showing a timing chart of the present invention, Fig. 4 is a diagram showing the output numbers and cycles for output comparison in the present invention in the pattern data storage block, Fig. 5 is a block diagram showing an example of the configuration of a conventional tester, and Fig. 6 is a diagram showing the conventional timing - A diagram showing a chart; FIG. 7 is a diagram showing the output number and cycle for output comparison in the prior art in the pattern data storage unit; FIG. 8 is a diagram showing the relationship between the CPE address and the pattern address. DESCRIPTION OF SYMBOLS 1...Test processor, 2...Pattern address generation section, 3...Pattern generation control data storage section,
4... Pattern data storage unit, 5... Timing generation unit, 6... Waveform shaping unit, 7... Device under test, 8
. . . Output comparison/determination section, 10. Comparison enable signal generation section, 11. CPE data storage section, 12.
CPE mask data storage section of output Oj, 15...tristate gate, 20...CPE window
Address storage.

Claims (1)

[Claims] A pattern data storage section (4) in which an m-bit input application pattern and an n-bit output expected value pattern are written in advance at each address, and read from the pattern data storage section (4). The m-bit input application pattern is waveform-shaped, and the waveform-shaped m
A waveform shaping section (6) that applies a bit input application pattern as an input signal to the device under test (7), and the device under test (7).
An output comparison/judgment section (8) that compares and decides the output signal from the output signal with an n-bit expected output value pattern, and a waveform shaping section (6) that provides input timing to the output comparison/judgment section (8). a timing generating section (5) to provide a timing, a comparison enable data storage section (11) in which n-bit comparison enable data is written in advance at each address, and a read address and predetermined address for the pattern data storage section (4). an address match detection section (12) that detects a match/mismatch with a given address; a comparison enable mask data storage section (14) in which n-bit mask data is written in advance;・Gate (15) and n logical product means (
13) and a signal line group (S
), and the input of the i-th (i=1, 2, ..., n) tri-state gate (15) is the data read from the comparison enable mask data storage section (14). The i-th bit of the mask data is input and the tri-state
The control terminal of the gate (15) is connected to the address match detection section (1
2) is applied to one input terminal of the i-th AND means (13),
The i-th bit of the comparison enable data read from the comparison enable data storage section (11) is input, and the i-th bit is input to the other input terminal of the i-th AND means (13). An LSI tester characterized in that the output of a tristate gate (15) is input.