JPH06265597A - Test equipment for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To correct fluctuation in the timing skew caused by various factors. CONSTITUTION:The delay of a variable delay circuit 16 is controlled based on a timing correction data outputted from a memory circuit 23. Address from the memory circuit 23 is connected with the outputs of a clock type control 20, a period control 21, a timing control 22 for controlling the clock type, period, and timing being used in the generation of driver output timing and strobe acquisition timing, the output of a pattern buffer 14 for storing a test data pattern, and the output of a wave control 19 for designating the output waveform of data. Each address stores a corresponding data pattern, a waveform, a clock type, a period, and a timing correction data representative of an appropriate delay for the timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for guaranteeing a test timing with high accuracy in a test device for a semiconductor integrated circuit such as an LSI.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit tester,
Given a predetermined test data pattern to the semiconductor integrated circuit,
The semiconductor integrated circuit is tested by comparing the output for the given test data pattern of the semiconductor integrated circuit with the expected value.

Therefore, in a semiconductor integrated circuit tester, skew generated due to variations in the propagation time due to the length of the cable and the propagation time of the driver circuit is corrected, and the test data pattern supply timing and comparison are performed. It is necessary to accurately match the timing of.

Therefore, in the technique disclosed in Japanese Patent Publication No. 63-57809, the address signal for clock selection is also input to the address of the memory circuit for storing the timing correction data for each clock type to delay the delay of the variable delay circuit. By controlling the timing with the output signal of the memory circuit, the skew is corrected by the variation of the propagation time of the driver circuit that drives each clock.

[0005]

By the way, such a variation in skew is a pattern given to a semiconductor integrated circuit.
Data, its cycle and phase, the format of the data given to the semiconductor integrated circuit, the type of timing clock used for the format, and other factors.

However, in the technique described in Japanese Patent Publication No. 63-57809, the skew caused by such a factor is
Is not taken into consideration.

Therefore, it is an object of the present invention to provide a semiconductor integrated circuit testing apparatus capable of correcting skew variations due to various factors.

[0008]

[Means for Solving the Problems] To achieve the above object,
The present invention is, for example, a semiconductor integrated circuit test apparatus for comparing an output of a semiconductor integrated circuit under test with an expected value for a given test data pattern, and a test pattern generation for generating a pattern of test data. Means, waveform shaping means for shaping the waveform of the supplied test data, a first variable delay circuit for delaying the waveform shaped test data, a driver for outputting the delayed test data, and a semiconductor integrated circuit under test. A comparator that compares the output of the circuit with an expected value, and a second variable delay circuit that delays the strobe timing that specifies the comparison timing of the comparator,
A first generator that specifies the output timing used by the waveform shaping means for waveform shaping and the timing generator that generates the strobe timing, and the timing generator that specifies the type of clock used for generating the output timing and the strobe timing. And a means for supplying a second control signal designating the output cycle and phase of the test data to the timing generator, and a third control signal designating the type of waveform shaping performed by the waveform shaping means. Means for supplying the waveform shaping means, a sequence of the generated test data, and the first
Control signal, the second control signal, and the third control signal are input as addresses, and the delay amounts of the first variable delay circuit and the second variable delay circuit are designated as data corresponding to the addresses. The data, respectively, in the first
And a memory circuit for outputting to the second variable delay circuit.

[0009]

According to the semiconductor integrated circuit testing device of the present invention, the test data, the type of waveform shaping, the type of clock to be used, the output cycle and the phase of the test data are appropriately passed through the memory circuit. Different delay amounts can be set for each variable circuit. Therefore, variations in skew due to such factors can be accurately corrected in real time.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the semiconductor integrated circuit according to the present invention will be described below.

FIG. 1 shows the configuration of a semiconductor integrated circuit testing apparatus according to this embodiment.

In the figure, a pattern memory 10 is a logic LSI.
Memory, pattern generator 1 for storing test data patterns used for AC / DC / function tests, etc.
Reference numeral 1 is a unit for generating a test data pattern of the memory LSI. The selector circuit 12 selects either the output of the pattern memory 10 or the output of the pattern generator 11.

The timing generator 13 is a unit for generating the driver output timing used by the waveform formatter circuit 15 and the strobe fetch timing used by the comparator 18. The clock type control 20, the cycle control 21, and the timing control 22 are control registers for respectively storing the clock type, the cycle, and the data for controlling the timing used for generating the driver output timing and the strobe fetch timing. Here, the cycle control 21 controls the bit cycle of the test data pattern output in bit serial, the timing control 22 controls the phase of each bit of the test data pattern, and the clock type control controls the waveform formatter. At 15 control the clock species used for the waveform format.

The pattern buffer 14 is a selector circuit 1.
The pattern data selected from 2 is temporarily stored and sent to the waveform formatter circuit 15 in a bit serial manner.

The waveform formatter circuit 15 uses the driver output timing from the timing generator 13 to
The test data pattern is shaped into a waveform suitable for the LSI to be measured, such as NRZ or RZ, and the variable delay circuit 16
Send to. The waveform control 19 is a control register that stores data designating a waveform.

The variable delay circuit 16 is a delay circuit for correcting the phase skew of the driver 17, and the variable delay circuit 24 is a delay circuit for correcting the phase of the strobe fetch timing of the comparator 28. .

The driver 16 sends the waveform-corrected data pattern with the phase skew corrected to the semiconductor integrated circuit such as the LSI to be measured bit-serially, and the comparator 18 is operated.
Compares the data input from the LSI to be measured and the expected value (not shown) at the strobe fetch timing and outputs the result.

Now, in such a configuration, the delay amount of the variable delay circuit 16 is controlled by the timing correction data output from the memory circuit 23. The address of the memory circuit 23 is the pattern buffer 14, clock type control 2
0, waveform control 19, cycle control 21, timing control 22
Is connected to each output, and each address stores the data pattern corresponding to the address, the clock type, the waveform, the period, and the timing correction data indicating the appropriate delay amount with respect to the timing. Here, the pattern buffer 14 is a bit-serial data pattern.
Output to the waveform formatter 15, but the memory circuit 2
For 3, all the bits currently stored are output in parallel as addresses. For example, if the pattern buffer 14 is a 4-bit buffer, all 4 bits currently stored are output in parallel as 4 bits of the address of the memory circuit 23.

Accordingly, the contents of the pattern buffer 14 are
Appropriate timing correction data corresponding to the states of the waveform control 19, the clock type control 20, the cycle control 21, and the timing control 22 are sent to the variable delay circuit 16 in real time,
The output of the driver 17 is always in a state where the skew is adjusted.

On the other hand, the delay amount of the variable delay circuit 24 is controlled by the timing correction data output from the memory circuit 25. The address of the memory circuit 24 is the cycle control 2
1. The timing control circuit 22 is connected to the output of the timing control unit 22 and each address stores the timing correction data indicating the period corresponding to the address and the appropriate delay amount with respect to the timing.

Accordingly, appropriate timing correction data according to the states of the cycle control 21 and the timing control 22 is sent to the variable delay circuit 24 in real time, and the comparator is operated.
The timing of strobe acquisition of the computer 18 is always skewed.
Is adjusted.

FIG. 2 shows the timing of address input of the memory circuit 23 and output of the memory circuit 23.

As shown in the figure, the test is performed according to the purpose.
The test data pattern designated by the pattern buffer 14 is applied to each of the combinations of the waveform, clock type, period, and timing controlled by the waveform control 19, clock type control 20, period control 21, and timing control 22. It is generally performed by giving it to the LSI to be tested in a bit serial manner. Here, the contents of the pattern buffer 14 are shifted and changed for each cycle controlled by the cycle control 21. Therefore, as shown in the figure, the timing correction data output from the memory circuit 23 also changes in each cycle. In the illustrated example, the capacity of the pattern buffer 13 is set to 4 bits, and the timing correction data is stored in the memory circuit 23 for each 4-bit bit string.

By thus changing the timing correction data in real time in accordance with the pattern data that changes in real time, it is possible to accurately correct the skew due to the pattern jitter that depends on the data pattern.

Now, the timing correction data stored in the memory circuit 23 and the memory circuit 25 is obtained by the procedure shown in FIG.

That is, first, the data pattern is patterned.
It is fixed to a predetermined reference data pattern from the generator 11 (step 30), and correction values of all possible combinations of waveform format, test period, timing and clock type are calculated (step 31), Next, all possible patterns are generated from the pattern generator and the phase difference from the reference pattern is measured to obtain a correction value (step 32).
Timing correction data is written in the memory circuits 23 and 25 using the calculated correction value (step 33).

Then, the timing correction data determined by such a calibration is transferred to the external support processor 26 and stored therein after the completion of the calibration (step 34). This is to prevent the timing correction data from being lost even when the power of the test apparatus is turned off.

The timing correction data stored in the external support processor 26 is loaded into the memory circuits 23 and 25 together with the power-on of the test apparatus.

As described above, according to this embodiment, the skew depending on the test period, clock timing, and waveform format, which are factors of the timing skew in the semiconductor integrated circuit test apparatus, is generated. It is possible to satisfactorily correct the variation and the skew variation due to the influence of the pattern jitter depending on the data pattern.

[0030]

As described above, according to the present invention, it is possible to provide a semiconductor integrated circuit testing apparatus capable of correcting skew variations due to various factors.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention.

FIG. 2 is a timing chart showing input / output of a memory circuit according to an embodiment of the present invention.

FIG. 3 is a flowchart showing a procedure for creating timing correction data used in an embodiment of the present invention.

[Explanation of symbols]

 10 ... Pattern memory 12 ... Selector 14 ... Pattern buffer 15 ... Waveform formatter 23 ... Memory circuit 25 ... Memory circuit

Claims (7)

[Claims] 1. A test device for a semiconductor integrated circuit, which compares an output of a semiconductor integrated circuit under test with an expected value for a given test data pattern, and a test pattern generating means for generating a pattern of test data. A waveform shaping means for shaping the waveform of the supplied test data, a variable delay circuit for delaying the waveform shaped test data, a driver for outputting the delayed test data, and an output of the semiconductor integrated circuit under test. A comparator for comparing with an expected value, a timing generator for generating an output timing used by the waveform shaping means for waveform shaping, and a column of the generated test data as an address are input as data corresponding to the address. A memory circuit that outputs data designating a delay amount of the variable delay circuit to the variable delay circuit. Test equipment. 2. A semiconductor integrated circuit testing device according to claim 1, wherein the test data generated by the test pattern generating means is temporarily stored in a predetermined amount before being supplied to the waveform shaping means. A test apparatus comprising: a test data string input to the memory circuit as an address, the test data string being stored in the pattern data buffer. 3. A test device for a semiconductor integrated circuit for comparing an output of a semiconductor integrated circuit under test with an expected value for a given test data pattern, and a test pattern generating means for generating a pattern of test data. A waveform shaping means for shaping the waveform of the supplied test data, a first variable delay circuit for delaying the waveform shaped test data, a driver for outputting the delayed test data, and a semiconductor integrated circuit under test. For delaying the comparator that compares the output of the output with the expected value and the strobe timing that specifies the comparison timing of the comparator.
Variable delay circuit, a timing generator for generating the output timing used for waveform shaping by the waveform shaping means and the strobe timing, and a clock used by the timing generator for generating the output timing and the strobe timing. A means for supplying a first control signal designating a type and a second control signal designating an output cycle and a phase of test data to the timing generator, and a type of waveform shaping performed by the waveform shaping means. A means for supplying a third control signal to the waveform shaping means, a sequence of the generated test data, the first control signal, a second control signal, and a third control signal.
Control signal is input as an address, and as the data corresponding to the address, data designating the delay amounts of the first variable delay circuit and the second variable delay circuit, respectively, is input to the first variable delay circuit. And a memory circuit for outputting to a second variable delay circuit. 4. The semiconductor integrated circuit testing device according to claim 3, wherein the memory circuit addresses the test data sequence, the first control signal, the second control signal, and the third control signal. As the data corresponding to the address, and outputs the data designating the delay amount of the first variable delay circuit to the first variable delay circuit, and the second control signal. A second memory for inputting an address and outputting, as data corresponding to the address, data designating a delay amount of the second variable delay circuit to the second variable delay circuit. Characteristic test equipment. 5. A semiconductor integrated circuit testing apparatus according to claim 3, wherein the test data generated by the test pattern generating means is temporarily stored in a predetermined amount before being supplied to the waveform shaping means. A test apparatus comprising: a test data string input to the memory circuit as an address, the test data string being stored in the pattern data buffer. 6. The semiconductor integrated circuit testing device according to claim 3, wherein the data stored in said memory circuit is based on a pattern of test data output from said test pattern generating means as a predetermined reference. With the test data pattern fixed, the timing correction values for all possible combinations of the clock type, test data output period, phase, and waveform shaping type are measured, and then the pattern is measured. Each timing correction data obtained by generating all possible test data patterns from the generator and measuring the timing correction value for each test data sequence included in each test data pattern. The data is written in the address corresponding to the pattern of the combination of the timing correction data measured and the test data. Test equipment. 7. The semiconductor integrated circuit testing device according to claim 3, wherein the data stored in said memory circuit is data externally loaded into said memory circuit when said testing device is activated. A testing device characterized by being present.