JPH0991194A - Mediation system and mediation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely guarantee data transfer to a device or a DMA channel for which it is required to transfer data within fixed time. SOLUTION: The time from the memory access start to the next memory access start of the specified device 103 for which it is required to transfer the data within the fixed time in the plural devices 101-103 to be the objects of arbitration by an arbiter 108 is timed in a timer circuit 109. When the timer circuit 109 detects that the specified device 103 is not selected for the fixed time required for the data transfer, the priority of the mediation circuit 108 is changed so as to make the priority of the specified device 103 be highest corresponding to the detection. Thus, the memory access request of the specified device 103 is allowed at every fixed interval of time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration system and an arbitration method, and more particularly to a device such as a device which needs to transfer data within a fixed time or an information processing system having a direct memory access (DMA) channel, which requires memory access or the like. The present invention relates to an arbitration system and an arbitration method provided with an arbitration circuit (arbiter) that arbitrates the priority of the.

[0002]

2. Description of the Related Art Conventionally, in a system having a DMA channel that needs to transfer data within a fixed time, as seen in a DMA transfer that transfers image data from a controller board of an electrophotographic printer to a print engine, By designing the arbitration circuit so as to give the DMA channel the next highest priority to the memory access request from the CPU (central processing unit), data transfer within a fixed time is enabled. This arbitration circuit causes a conflict when a plurality of constituent devices simultaneously issue usage requests to the same resource (for example, memory). However, by giving an appropriate priority (priority) to the conflicting request signals, the arbitration circuit Is assigned.

[0003]

However, in the prior art as described above, in the situation where the memory access is frequently performed from the CPU having a higher priority than the DMA channel which needs to transfer the data within a fixed time, There have been cases where the DMA channel cannot transfer data within a fixed time.

On the other hand, in a system in which frequent memory access requests from the CPU do not continue for a long time, first-in first-out (F
IFO) A buffer circuit including a memory is provided, and
Some MA channels are designed to transfer data within a fixed time. However, even if such a buffer circuit is provided, it is not possible to cope with the situation where the memory access from the CPU is frequent for a long time, and it is expensive because of the memory used for the buffer circuit. There was a problem to be solved.

The present invention has been made in view of the above points, and an object thereof is to transfer predetermined data to a device which needs to transfer data within a fixed time or a constituent device such as a DMA channel. An object of the present invention is to provide an arbitration system and an arbitration method that ensure a time interval.

A further object of the present invention is to reduce the cost by eliminating the need for a buffer circuit.

[0007]

In order to achieve the above object, the system of the present invention arbitrates usage requests from a plurality of devices for shared resources by a predetermined priority and selectively permits the use of shared resources. This is an arbitration system that performs timekeeping and measures the time from the start of usage request permission of a specific device that needs to transfer data within a fixed time among multiple devices subject to arbitration to the start of the next usage request permission. The timing means for generating a time-out signal when detecting that the use request permission of the particular device is not selected for a predetermined time, and the priority of the particular device is the highest according to the time-out signal from the time-measuring means, Alternatively, it is provided with an arbitration means for permitting the use request of the specific device at regular time intervals by changing at least the second highest value.

In one form of the system of the present invention, when the arbitration means changes the priority order and then selects a specific device and permits a usage request from the specific device, the priority order is changed to the original order. Restores the initial priority.

As another form of the system of the present invention, when the arbitration means permits a use request from a specific device before the timekeeping means measures a predetermined time, the content of the timekeeping means is returned to the initial state. Restart timekeeping.

In another form of the system of the present invention, when a device other than the specific device has obtained permission to use when the time-out signal of the timing means is generated, the system other than the specific device is activated based on the generation of the time-out signal. It has a means for interrupting the use permission to withdraw the use permission of the device on the way.

As another form, the system of the present invention has a masking means for prohibiting the arbitration means from selecting a usage request of another device while permitting the use request of the device selected by the arbitration means.

As another form, the system of the present invention is a memory system in which the shared resource has a memory such as DRAM, the use request from a plurality of devices is a memory access request to the memory system, and the clock means is the memory system. Transfer period register that is set as the predetermined time by subtracting the time from when a memory access of another device is interrupted until the memory access of a specific device is started from the fixed time required to transfer data from the device to the specific device And a timer circuit that initially sets a value of a predetermined time of the transfer cycle register to start time measurement, and a normal time priority order in which a certain device other than a specific device has the highest priority in the arbitration means. A specific device has a highest priority, or at least a second highest preset It includes a priority encoder circuit.

In another form of the system of the present invention, two or more devices including a specific device among a plurality of devices share one data bus, and the two or more devices and the arbitration means are provided. A DMA controller having a data bus arbitration function is connected between the two, and two or more devices are given a data bus use right and a memory access right from the DMA controller based on an instruction from the arbitration means.

In order to achieve the above object, the method of the present invention is an arbitration system for arbitrating use requests from a plurality of devices for a shared resource according to a predetermined priority order and selectively permitting the use of the shared resource. Of the specified devices that need to transfer data within a certain time among multiple devices subject to the arbitration, the time from the start of the use request permission to the start of the next use request permission is timed Generating a time-out signal when it is detected that the use request permission of is not selected for a predetermined time,
A step of withdrawing permission to use a device other than the specific device in response to the occurrence of the timeout signal, and changing the priority of the specific device to the highest or at least the second highest in response to the timeout signal. The step of returning the priority to the original priority level after permitting the use request of a specific device at every fixed time, and selecting the use request of another device while permitting the use request of one device is continued. And a prohibiting step.

The method of the present invention also has, as one form thereof, a step of returning to the initial state and restarting the clocking when the use request from the specific device is permitted before the clocking of the predetermined time.

According to the present invention, among the plurality of devices to be arbitrated by the arbitration means, the time from the start of access of a specific device that needs to transfer data within a fixed time to the start of the next access is measured by the timer means. Time. When the timing means detects that the particular device has not been selected for a certain period of time required for data transfer, the particular device is given the highest priority or at least the second highest in response to the detection. The priority of the arbitration means is changed as follows. Thereby, the access request of the specific device can be permitted at regular intervals.

Further, according to the present invention, a DMA controller is added between the arbitration means and a plurality of devices so that a specific device and another device share the same data bus.
The specific device can acquire the right to use the data bus and the right to access the memory when the timing means times out.

Further, according to the present invention, the highest priority of the refresh timer is not changed and the specific device is changed to the second priority when the priority is changed, so that the activation of the refresh cycle to the DRAM is completed. Can be guaranteed.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
2 shows a circuit configuration of the embodiment. The system 100 includes a refresh timer 101, a CPU 102, a first device 103, a second device 104, and a multiplexer 10.
5, DRAM (dynamic RAM) controller 10
6. A memory system 107 including a DRAM, an arbitration circuit 108, and a timer circuit 109 are included. Also, the multiplexer 105 and the DRAM controller 1
Bold lines 111, 112, 113, 125 and 12 connecting the memory system 107 and each device via 06.
Reference numeral 8 is a data bus for transmitting data from the memory system 107. The thin line represents a signal line.

The CPU 10 is a device that controls the arithmetic control of the entire system, and a known one-chip microcomputer or the like can be applied to it. The DRAM controller 106 generates a sequence for accessing the memory system 107. The refresh timer 101 is a timer circuit that activates a refresh cycle in the DRAM of the memory system 107.

The arbitration circuit 108 gives a proper priority (priority) to the memory access request signal because a conflict occurs when a plurality of devices make a memory access request to the DRAM at the same time, and the arbitration circuit 108 selects based on the priority. The arbitration process of allocating DRAM to the device is executed. Multiplexer 105
The data of the memory system 107 is distributed to the device selected by the arbitration circuit 108. First device 10
Reference numeral 3 denotes a device that needs to transfer data within a certain period of time, such as a print engine of an electrophotographic printer to which image data is transferred from the memory system 107. The second device 104 is a device having a lower memory access priority than the first device 103, and corresponds to, for example, an external storage device. The timer circuit 109 measures (counts) the time from the data transfer to the first device 103 to the next data transfer, and outputs the time-out signal 109 when measuring a preset fixed time.

The normal priority set in the arbitration circuit 108 is highest in the refresh timer 101, followed by the CPU 102, the first device 103, and the second device 104 in that order. However, as will be described later, the time-out signal 109 from the timer circuit 109 causes the memory access request 118 of the first device 103.
Arbitration circuit 108, the arbitration circuit 108 makes the first device 103 the highest priority, and then the refresh timer 101, the CPU 1
02, the priority of the second device 104 is changed to become lower.

Next, the overall operation of the system 100 having the above configuration will be described along the flow of signals. Each device 1
The memory access request signals 114, 116, 118, and 120 from 01, 102, 103, and 104 are arbitration circuits 108.
Arbitration circuit 108, the arbitration circuit 108 selects the device with the highest priority among the devices that have made a memory access request, transmits the memory access request signal 122 to the DRAM controller 106, and selects the result (selected device) to the multiplexer 105. It is conveyed by signal 124.

Upon receiving the memory access request signal 122, the DRAM controller 106 receives the memory system 107.
An access cycle signal 126 is generated in the DRAM and the data enable signal 123 is returned to the arbitration circuit 108. Upon receiving the data enable signal, the arbitration circuit 108 sends data enable signals 115, 117, 1 to the selected device.
Returns 19, 121. On the other hand, the access cycle signal 12
The DRAM which has received 6 receives the internal data (128) as D
The data is output to the multiplexer 105 through the RAM controller, and the multiplexer 105 outputs this data to the arbitration circuit 1.
08 selected devices 102, 103, 10
4 data buses 111, 121, 113.

The refresh timer 101 which receives the data enable signal 115, or the data enable signals 117, 119 and 121 and the data (111, 112, 1).
13) Other devices 102, 103, 104 that have received
Withdraws the memory access request on signals 114, 116, 118, 120. Since the memory access request is withdrawn by the selected device, the arbitration circuit 10
8 enters the next arbitration. At this time, if the timer circuit 109 indicates the signal 129 indicating that the memory access request signal 118 from the first device 103 has not been selected for a certain period of time, the arbitration circuit 108 causes the first device 10 to operate.
The priority is changed so that the memory access request of No. 3 has the highest priority. As a result, if the first device 103 is selected with the highest priority and memory is allocated, the arbitration circuit 108 returns to the normal priority again and performs arbitration processing.

FIG. 2 shows a detailed configuration example of the arbitration circuit section 110 including the arbitration circuit 108 and the timer circuit 109.
The arbitration circuit unit 110 is used by the priority encoder 20.
1. J-K flip-flop circuits 201 to 205, 21
2, OR gate (logical sum circuit) 206, AND gates (logical product circuit) 207 to 211, 251, timer circuit 2
13 and a transfer period register 24.

When a memory access request arrives, the priority encoder 201 selects the device with the highest priority at that time according to the logic of the truth table of FIG. 3 described later. The input terminals a, b, c, d of the priority encoder 201 have memory access request signals 114, 116, 118, 120 from the corresponding devices, respectively.
Is input to the output terminals z1, z2, z3, and z4 of which signals 226, 227, and 22 indicating the selected device are input.
8 and 229 output. These signals 114 and 226
Is a signal regarding the memory access request from the refresh timer 101, signals 118 and 228 are signals regarding the memory access request from the first device 103, and signals 120 and 229 are the second device 10.
4 is a signal relating to a memory access request from the memory 4 (see FIG. 1).
See). Further, the priority encoder 201 outputs a signal 12 for instructing to change the priority of the memory access request.
A change terminal for accepting 9 and a mask terminal for accepting a signal 260 indicating that no other memory access request is selected are also provided.

JK flip-flop circuits 202 to 20
Reference numeral 5 denotes a circuit for holding each selection output of the priority encoder 201. The signals 230, 234, 235 and 236 from the respective Q output terminals are supplied to the multiplexer 105 as the device selection signal 124, and at the same time, the OR gate. It is sent to the DRAM controller 106 as a memory access request signal 122 through 206. The output signal 122 of the OR gate 206 is also supplied to the priority encoder 201 so that another memory access request is not selected.

The timer circuit 213 counting the data transfer time interval reads the initial value 249 of the data transfer time interval from the transfer cycle register 214 in response to the input of the data enable signal 119, and determines the time until the next data transfer. Start counting. Transfer cycle register 21
Although the contents of 4 may be fixed as in this example, for example, C
It is preferable that the PU 102 be configured so that the transfer cycle can be variably set according to changes in the usage status. The time-out signal 248 from the timer circuit 213 is used to suspend the memory access, so that the DRAM controller 106
To the JK flip-flop 212
And priority change signal 1 via AND gate 211
It is also supplied to the priority encoder 201 as 29.

Next, the flow of the entire operation of the arbitration circuit section 110 of FIG. 2 will be described. Each device 101, 10
Memory access request signal 11 from 2, 103, 104
4, 116, 118, 120, the device having the highest priority at that time among the devices of the incoming signals is selected by the priority encoder 201, and its selection signals 226, 227, 228, 22 are selected.
9 is flip-flop circuits 202, 203, 204, 205 at the next rising edge of the clock signal 250.
When it is caught by, it is DR as a memory access request signal 122 by passing it through an OR gate 206.
It is transmitted to the AM controller 106. Since the memory access request of either device is currently selected,
The signal 122 is simultaneously sent to the priority encoder 20.
The priority encoder 201 is also masked so as not to select the memory request of a device other than the selected device.

D for the memory access request signal 122
Data enable signal 1 from RAM controller 206
When 23 is returned, this data enable signal 1
23 and the flip-flop circuits 202, 203, 204,
AND outputs 251, 208, 209 and 210 take the logical product of the outputs 230, 234, 235 and 236 of the 205 and the result is the data enable signal 11 of each device.
5, 117, 119, 121 are assigned. At this time, when the first device 103 is selected, the data enable signal 119 is also input to the load terminal (L) of the timer circuit 213 at the same time. Timer circuit 213
The transfer period register 21 having the initial value 249 of the data transfer time interval in response to the input of the data enable signal 119.
Reading from 4 starts counting the time (clock signal) until the next data transfer.

When the memory access is completed, a memory access end signal comes from the DRAM controller 206, and this signal causes the flip-flop circuit 20 to operate.
Clear 2, 203, 204 and 205. Since the memory access request signal 122 to the DRAM controller 206 is released by clearing the flip-flop circuits 202, 203, 204, 205, the mask of the priority encoder 201 is released, which causes the priority encoder 201 to move to the next memory. Move to access request arbitration.

If the timer circuit 213 counts up to the predetermined time required for data transfer to the first device 103 during the memory access, the timer circuit 213
Generates a timeout signal 248. The time-out signal 248 is sent to the DRAM controller 106 to interrupt the memory access being performed at that time, and the flip-flop circuit 212 and the AND gate 2
The priority order change signal 129 is also sent to the priority encoder 201 through 01 to change the priority order of the memory access request of the priority encoder 201.

As a result, the memory access that has occurred at this point is interrupted, and the end signal of the memory access comes from the DRAM controller 206, and this signal causes the flip-flops 202, 203, and 20.
Clear 4,205. Flip-flop circuit 20
Since the memory access request signal 122 to the DRAM controller 206 is released by clearing 2, 203, 204, and 205, the mask of the priority encoder 201 is released, which causes the priority encoder 201 to move to the next memory. Move to access request arbitration. At this time, since the first device 103 has the highest priority, the first device 103
Memory access is selected with the highest priority, and data transfer from the memory system 107 to the first device 104 is secured.

Since a certain time is required before the memory access of the first device 103 starts after the time-out signal 248 is generated, the value set in the transfer cycle register 214 needs to be transferred. It is necessary to set a value obtained by subtracting the time from when a memory access of another device is interrupted until the memory access of the first device 103 starts from a certain fixed time.

FIG. 3 shows the priority encoder 20.
It is a truth table showing the logic of 1. In the figure, a, b,
"1 and 0" in the columns of c, d and z1, z2, z3, z4 correspond to the input / output values to the terminals of the same sign of the priority encoder 201 of FIG. 2, and "1" has an input or an output. "0" represents the case where there is no input or output. Further, “0 and 1” in the change column correspond to the value of the priority order change signal 129 in FIG. 2, “0” is the setting for the normal priority, and “1” is the priority of the first device 103. The case of the highest priority change setting is shown.

As can be seen from FIG. 3, in the normal priority when the change column is "0", the refresh timer 101 of a, z1 has the highest priority, and the CPUs 102, c, z3 of b, z2 have the highest priority. The first device 103, the second device 104 of d, and the second device 104 of z4 are lower in this order. On the other hand, when the change column is “1”, the priority of the first device 103 of c and z3 is set to the highest, and then the refresh timers 101 and b of a and z1 and the CPUs 102, d and z4 of z2 are set. The priority is changed so that the second device 104 becomes lower in order.

For example, when the memory access requests of the refresh timer 101 of a, z1 and the CPU 102 of b, z2 and the memory access request of the first device 103 of c, z3 compete with each other, the normal case when the change column is "0" is set. In the priority, the refresh timer 101 or the CPU 102 is selected in preference to the first device 103,
At the change priority when the change column is “1”, the first device 103 is selected in preference to the refresh timer 101 and the CPU 102.

The priority encoder 201 for executing such logic can be easily realized not only by a logic circuit but also by a look-up table, for example.

The timing chart of FIG. 4 shows the operation timing of the arbitration circuit section 110 of FIG. Where s1
s26 indicates a step of timing synchronized with the clock signal 250. Further, reference numerals such as 250 and 114 indicate signals having the same reference numerals in FIG. In the example of this figure, the CPU 102
Memory access and the refresh cycle by the refresh timer 101, the first device 103 continues to be in a state in which data transfer cannot be performed despite issuing the memory access request signal 118 (s1 to s13) (in particular, signals 114, 116 and 118). , 230, 234, 23
5). If this state continues, the timer circuit 213 times out and a timeout signal 248 is generated (s1
4) Suspend the memory access cycle of the CPU 102 (s15) (see especially the signal 234).

The next arbitration (s1) due to the occurrence of the priority order change signal 129 accompanying the generation of the timeout signal 248
By 6), the first device 103 can access the memory, and data transfer within a fixed time is secured (s17).
~ S18) (see especially signal 235). The timer 213 starts counting the next cycle due to the occurrence of the signal 119 accompanying the signal 235, and the memory access of the first device 103 is performed again (s19 to s24) (particularly the signal 23).
4).

(Second Embodiment) FIG. 5 shows a circuit configuration of a second embodiment to which the present invention is applied. In this example, a DMA controller 501 is added to the circuit of the first embodiment of FIG. 1, and the first device 103 and the second device 104 are added.
Are configured to share the same data bus 511.

The DMA controller 501 is the data bus 5
Since the arbitration function 11 has the arbitration function 11, the signal 129 indicating the change of the priority order due to the timeout of the timer circuit 109 is input to the DMA controller 501 at the same time as the arbitration circuit 108. In response to the input of the priority change signal 129, the DMA controller 501 sends a data enable signal 119 which permits the first device 103 the right to use the data bus 511 and the right to access the memory. As a result, the first device 103 can acquire the right to use the data bus 511 and the right to access the memory at the time of timeout, and can secure the data transfer within a fixed time.

The configuration of FIG. 5 has an advantage that the number of data buses can be reduced because a plurality of devices can share the data bus.

(Other Embodiments) In the above-described embodiment of the present invention, the first device 103 is changed to the highest priority by the priority changing process, but the refresh cycle is activated to the DRAM of the memory system 107. In the case of a system in which it is necessary to place the highest priority on guaranteeing the above, the first priority of the refresh timer 101 is not changed, and the first device 103 is changed to the second priority when the priority is changed. It is preferable to configure In this case, the line of the signal 150 of FIG. 1 and the AND gate 251 of FIG. 2 are not necessary in this case, and the contents of the truth table of FIG. 3 can be rewritten.

In the above-described embodiment of the present invention, the case where it is applied to the arbitration circuit of the information processing system having the memory system as the shared resource is illustrated as the most preferable embodiment, but the present invention is not limited to this. The arbitration circuit that arbitrates the competition when a plurality of devices (for example, a plurality of processors, etc.) request a usage request to a shared resource (for example, a device having a single function such as an arithmetic unit) other than the memory system is similar to the above embodiment. Of course, it is applicable.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, according to the present invention, by reading a storage medium in which a program is stored in the system or device into the system or device, the system or device can enjoy the effects of the present invention.

[0049]

As described above, according to the present invention,
Among multiple devices subject to arbitration, it is necessary to transfer data within a certain period of time. When it is detected that the particular device is not selected, the priority of the arbitration means is changed so that the priority of the particular device becomes the highest, or at least the second highest, and the memory access request of the particular device is made at regular intervals. Since the permission is permitted, there is an effect that the data transfer to the device or the DMA channel that needs to transfer the data within a certain time can be surely guaranteed.

Further, according to the present invention, since it is not necessary to use an expensive buffer such as a FIFO memory, there is an advantage that it can be provided at a relatively low cost.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a first embodiment to which the present invention is applied.

FIG. 2 is a block diagram illustrating a detailed configuration example of an arbitration circuit unit in FIG.

3 is a diagram showing a truth table representing the logic of the priority encoder of FIG.

FIG. 4 is a timing chart showing the operation of the circuit of FIG.

FIG. 5 is a block diagram showing a circuit configuration of a second embodiment to which the present invention is applied.

[Explanation of symbols]

101 Refresh Timer 102 CPU 103 First Device (Specific Device) 104 Second Device 105 Multiplexer 106 DRAM Controller 107 DRAM 108 Arbitration Circuit 109 Timer Circuit 111, 112, 113, 125, 128, 511 Data Bus 201 Priority Encoder 202, 203, 204, 205, 212 Flip-flop circuit 206 OR gate 207, 208, 209, 210, 211, 251 A
ND gate 213 timer circuit 214 register 501 DMA controller

Claims (9)

[Claims] 1. An arbitration system that arbitrates usage requests from a plurality of devices for a shared resource according to a predetermined priority order and selectively permits the use of the shared resource. In particular, the time from the start of permission of use request of a specific device that needs to transfer data within a certain period of time is counted from the start of permission of the next use request, and the permission of use request of the specific device is selected for a predetermined time. A time-out means that generates a time-out signal when it detects that there is no time-out, and the priority of the particular device is changed to the highest or at least the second highest in accordance with the time-out signal from the time-measurement means. An arbitration system comprising: an arbitration unit that permits a use request at regular time intervals. 2. The arbitration means, after changing the priority,
2. When the specific device is selected and the usage request from the specific device is permitted, the priority is returned to the original priority of the initial state after that.
Arbitration system described in. 3. The timekeeping means returns the content of the timekeeping means to an initial state and restarts the timekeeping when the use request from the specific device is permitted by the arbitration means before the predetermined time is counted. The arbitration system according to claim 1 or 2, wherein 4. When the device other than the specific device has obtained permission to use when the time-out signal is generated by the timing means, the use permission of the device other than the specific device is permitted based on the generation of the time-out signal. The arbitration system according to any one of claims 1 to 3, further comprising a use permission interrupting means for withdrawing the license on the way. 5. The masking means for prohibiting the arbitration means from selecting the usage request of another device while permitting the usage request permission of the device selected by the arbitration means. The arbitration system according to any one of 4 to 4. 6. The shared resource is a memory system having a memory such as a DRAM, the use request from the plurality of devices is a memory access request to the memory system, and the time counting unit is the memory system A transfer cycle in which a value obtained by subtracting the time until the memory access of another device is interrupted and the memory access of the specific device is started from the fixed time required to transfer data to the specific device is set as the predetermined time. A register and a timer circuit that initially sets the value of the predetermined time of the transfer period register to start the time counting, and the arbitration unit is a normal device having a highest priority of a certain device other than the specific device. Time priority and the priority of the particular device is highest, or at least the second highest. 6. The arbitration system according to claim 1, further comprising a fixed priority encoder circuit. 7. Two or more devices including the specific device among the plurality of devices share one data bus, and have a data bus arbitration function between the two or more devices and the arbitration means. 7. The arbitration according to claim 6, wherein a DMA controller is connected to the two or more devices, and the DMA bus is given the right to use the data bus and the right to access the memory based on an instruction from the arbitration unit. system. 8. An arbitration system that arbitrates usage requests from a plurality of devices for shared resources according to a predetermined priority order and selectively permits the use of the shared resources. In particular, the time from the start of permission of use request of a specific device that needs to transfer data within a certain period of time is counted from the start of permission of the next use request, and the permission of use request of the specific device is selected for a predetermined time. A step of generating a time-out signal when detecting that there is no, a step of withdrawing the use permission of the device other than the specific device in the middle in response to the generation of the time-out signal, and of the specific device according to the time-out signal By changing the priority to the highest, or at least the second The method includes the steps of returning the priority to the original priority level after the permission is granted at regular time intervals, and prohibiting the selection of the usage request of another device while the permission of the usage request of any of the devices is continued. An arbitration method characterized in that 9. The method according to claim 8, further comprising the step of returning to the initial state and restarting the clocking when the use request from the specific device is permitted before the clocking of the predetermined time. Mediation method described.