JP3987750B2 - Memory control device and LSI - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory control device for controlling memory access, and more particularly to a memory control device included in an LSI (large scale integrated circuit), which is connected to a memory connected to the outside of the LSI by a plurality of circuits inside the LSI. The present invention relates to a memory control device that controls access.
[0002]
[Prior art]
In recent years, LSIs including one or more DSPs (Digital Signal Processors) and MPUs (Microprocessing Units) have been developed in order to process video, audio, etc. at high speed against the background of multimediaization of information. It is coming.
[0003]
In addition to MPU, complex and high-performance LSIs equipped with independent circuits such as a graphics processor, an AV (Audio Visual) decoder, and a hard disk controller have been developed.
Each internal circuit in such a composite LSI is an independent circuit capable of performing arithmetic processing for realizing each function using an independent local memory, but each circuit has the same memory. If the LSI is configured so as to perform arithmetic processing or the like for realizing each function by sharing, it is possible to reduce the cost of components.
[0004]
For this purpose, it is necessary to provide a memory control device inside the LSI for arbitrating memory access contention by each circuit to the same memory.
The memory control device arbitrates an access request to a memory from a plurality of circuits such as a DSP and an MPU (hereinafter referred to as “bus master”), that is, a bus request for the memory bus, and only one bus master at a certain time. Allow access. That is, the memory control device grants the right to use the memory bus to only one bus master at a certain time.
[0005]
On the other hand, each bus master issues a bus request to the memory control device when memory access becomes necessary, and when the bus use right is acquired, performs data transfer with the memory using the memory bus.
By the way, some bus masters require data transfer at a constant transfer rate when there is data to be continuously processed in order to realize real-time reproduction of video and audio, for example.
[0006]
Bus masters that require data transfer at a fixed transfer rate are specific to the time interval within which the transfer rate should be maintained, depending on the internal I / O buffer size, data processing method, and other factors I have a request. For example, when viewed through 2 milliseconds (ms), there may be a bus master that only needs to maintain a transfer rate of 500 kilobytes / millisecond (KB / ms). Some bus masters have no margin and must maintain a transfer rate of 500 KB / ms in 1 ms.
[0007]
If the memory can be monopolized, the bus master basically issues a bus request repeatedly with a time interval within a range in which the transfer rate should be maintained. Hereinafter, the time interval within which the transfer rate should be maintained is referred to as a bus request cycle.
When designing an LSI that includes multiple bus masters that require data transfer at a constant transfer rate and a memory controller, arbitration of the memory controller takes into account the transfer rate and bus request cycle required by each bus master. A mechanism must be built.
[0008]
If arbitration is appropriate, each bus master can transfer data at the required transfer rate, but if arbitration is not appropriate, any bus master transfers data at the required transfer rate within the bus request cycle. The problem that it is not possible to do.
As a conventional memory control device, there are a general memory control device that uses a bus usage right preemptive priority method as an arbitration mechanism, and a method that uses a method that arbitrates based on a priority determined for each bus master.
[0009]
[Problems to be solved by the invention]
Hereinafter, problems of such a conventional memory control device will be described.
Assuming that the bus bandwidth of the memory bus is about 800 KB / ms, when there is data to be continuously processed, the bus master A requests that the bus request cycle be 2 ms and 1000 KB of data be transferred during the 2 ms. Assuming that the LSI includes two bus masters, the bus master B and the bus master B requesting that 100 KB of data be transferred during 1 ms when the bus request period is only 1 ms and the bus request cycle is 1 ms. To do. Further, it is assumed that the bus master A first issues a bus request if the preemptive priority method is used, and the bus master A is assumed to have a high priority if it is a method that performs arbitration based on the priority.
[0010]
In this case, when there is a bus request from the bus master A in the conventional memory control device, the memory control device grants the bus use right to the bus master A and permits data transfer. In response to this, when the bus master A transfers 1000 KB of data, the transfer takes 1 ms or more, so the memory control device cannot immediately respond to a bus request from the bus master B every 1 ms.
[0011]
For this reason, for the bus master B, the memory access waiting time becomes longer than 1 ms, and the data transfer amount between the bus master B and the memory is not unified to 100 KB in each cycle of 1 ms unit. It will occur. That is, the transfer rate required by the bus master B cannot be maintained within the bus request cycle.
[0012]
As described above, the conventional memory control device having the arbitration mechanism using the bus use right preemption priority scheme or the arbitration scheme based on the priority can guarantee the transfer rate required by each bus master in the long term. However, there is a problem that the transfer rate cannot be guaranteed in a short period of time.
In order to solve this problem, it is necessary to design the memory control device in advance in consideration of the transfer rate required by each bus master and the time interval within which the transfer rate is to be guaranteed.
[0013]
However, depending on the device in which the LSI is mounted, the contents of processing required for each bus master change, and this changes the transfer rate and bus request cycle required by each bus master. It is difficult to design a memory control device in consideration of specific processing contents in advance.
In addition, LSIs are becoming more sophisticated year by year, and from the standpoint of reducing development costs when new circuits are incorporated in the LSI in the future, the data transfer rate for each circuit will be whatever the circuit included in the LSI. Design and development of a highly versatile memory control device that can be guaranteed is required. This is because if the versatility of the memory control device is high, the design assets can be used for a long time.
[0014]
Accordingly, the present invention has been made in view of such a demand, and is a general-purpose memory control device that arbitrates memory access contention by guaranteeing a required transfer rate to each bus master with a required time accuracy. The purpose is to provide. It is another object of the present invention to provide an LSI including the memory control device and the bus master.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, a memory control device according to the present invention arbitrates a memory access conflict by selectively granting a right to use a memory bus to any of a plurality of bus masters sharing a memory. A memory control device, for each of a plurality of bus masters, a transfer rate at which the bus master transfers data to and from a memory, and a time interval that defines a range to be guaranteed to be transferred at the transfer rate Holding unit for holding transfer rate information indicating unit time calculating unit for determining a unit time as a time equal to or less than the smallest time interval corresponding to each bus master, and for each bus master, the unit according to the corresponding transfer rate V transfer based on the bus bandwidth of the memory bus when the amount of data that can be transferred in time is V Bus usage permission time calculating means for obtaining a bus usage permission time, which is a required time, and a bus corresponding to each bus master in each of a plurality of unit time zones obtained by periodically dividing the passage of time by the unit time. Usage right granting means for granting the right to use the memory bus for the usage permission time.
[0016]
In addition, the memory control device according to the present invention arbitrates contention for access to the memory by selectively granting the right to use the memory bus to a plurality of bus masters that access mutually independent memory areas in one memory. A memory control device for each of a plurality of bus masters, which defines a transfer rate when the bus master transfers data to and from the memory and a time interval that guarantees transfer at the transfer rate Holding means for holding transfer rate information indicating unit time, a unit time calculation means for setting a time equal to or less than the smallest one of the time intervals corresponding to each bus master as a unit time, and for each bus master, depending on the corresponding transfer rate Based on the bus bandwidth of the memory bus when the amount of data that can be transferred in unit time is V A bus use permission time calculating means for obtaining a bus use permission time which is a time required for the transfer of V, and each bus master in each of a plurality of unit time zones obtained by periodically dividing the passage of time by the unit time. And usage right granting means for granting the right to use the memory bus for the corresponding bus usage permission time.
[0017]
With the above configuration, the transfer rate is adjusted so that the conditions regarding the transfer rate of the bus master with the smallest allowance for transfer can be satisfied even if the conditions regarding the transfer rate requested by each bus master are not uniform. As a result, each bus master can perform data transfer while keeping the transfer rate constant with the required time accuracy.
[0018]
In addition, when this memory control device is used, even when it is necessary to change the conditions regarding the transfer rate of each bus master, it is possible to rewrite the stored transfer rate information at a transfer rate according to the request of each bus master. Each bus master can transfer data to and from the memory. From this, it can be said that this memory control device can be utilized even if the bus master subject to access contention control is replaced.
[0019]
In addition, the LSI according to the present invention includes a plurality of circuits sharing a memory, and a memory control that arbitrates a memory access conflict by selectively granting a right to use a memory bus to any one of the plurality of circuits. And each of the circuits is a circuit that requires data to be transferred to and from a memory at a constant transfer rate. Corresponding to each circuit, and holding means for holding transfer rate information indicating a transfer rate at the time of transferring data to and a time interval that defines a range in which the transfer should be guaranteed at the transfer rate Unit time calculation means for determining a time less than the smallest one of the time intervals as a unit time, and each circuit can be transferred to the unit time at a corresponding transfer rate. Bus usage permission time calculating means for obtaining a bus usage permission time which is a time required for V transfer based on the bus bandwidth of the memory bus when the data amount is V, and the time passage is periodically divided into the unit times. In each of the plurality of unit time zones obtained in this manner, each circuit is provided with usage right granting means for granting the right to use the memory bus for the corresponding bus usage permission time.
[0020]
With the above-described configuration, each of the plurality of internal circuits of the LSI can perform data transfer with a necessary transfer rate with a necessary time accuracy with respect to the memory shared with each other.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an LSI including a memory control unit and a plurality of bus masters, which is an embodiment of a memory control device according to the present invention, will be described.
<Embodiment 1>
<Configuration>
FIG. 1 is a configuration diagram of an LSI 100 including a memory control unit according to the first embodiment of the present invention. FIG. 1 shows a unified memory 200 in addition to the LSI 100.
[0022]
The LSI 100 is an LSI mounted on information home appliances and other devices, and includes a memory control unit 110, a bus master A 121, a bus master B 122, a bus master C 123, and a clock generator 190, and is connected to the unified memory 200. Although not shown in FIG. 1, the LSI 100 is also connected to other external devices.
[0023]
Here, the clock generator 190 is a circuit that supplies a clock signal to the memory control unit 110, the bus masters A to C, and the unified memory 200.
The bus masters A121, B122, and C123 are, for example, an MPU that uses the unified memory 200 as a main memory, a DSP that stores image data or the like in the unified memory 200, and accesses the unified memory 200 and transfers data independently of each other. I do. That is, each of the bus masters A to C issues a bus request to the memory control unit 110 through the REQ signal line when data transfer is necessary, and obtains a bus use right from the memory control unit 110 through the GNT signal line. While the right to use is obtained, data is transferred in synchronization with the arbitration unit 114 of the memory control unit 110 at a timing based on the clock signal from the clock generator 190.
[0024]
In FIG. 1, bus requests from each bus master are represented by REQ-A, REQ-B, and REQ-C, respectively, and the granting of the bus use right to each bus master is represented by GNT-A, GNT-B, and GNT-C, respectively. Represents.
The data transfer is performed by designating a memory address, writing data to the unified memory, or reading data from the unified memory, whereby the address and data are transmitted on the memory bus. The data transferred by each bus master to / from the unified memory 200 is video data to be output to the display device generated by the bus master based on data input from an external device, for example.
[0025]
Each bus master performs data transfer processing independently. For example, to prevent the video output to the display device from being interrupted, data is transferred to and from the unified memory at a constant transfer rate. Is something that must be done. However, the bus master does not always transfer data to and from the unified memory continuously. For example, the bus master continuously transfers data to the unified memory during the period in which data to be sent is generated and stored because the data is continuously input from the external device. The bus master does not transfer data to the unified memory during a period in which data to be transmitted is not accumulated, for example, because of no input.
[0026]
The memory control unit 110 arbitrates access to the unified memory 200 of each bus master based on transfer rate information transmitted from an external device, and includes a transfer rate information storage unit 111, a timing information generation unit 112, A timing information storage unit 113 and an arbitration unit 114 are included.
Here, the transfer rate information storage unit 111 is a memory area for storing transfer rate information transmitted from an external device. The transfer rate information will be described in detail later.
[0027]
The timing information generation unit 112 has a function of generating timing information with reference to the transfer rate information stored in the transfer rate information storage unit 111 and storing the timing information in the timing information storage unit 113. The timing information will be described in detail later.
The timing information storage unit 113 is a memory area for storing timing information.
[0028]
The arbitration unit 114 refers to the timing information stored in the timing information storage unit 113, checks the presence / absence of a bus request from each bus master based on the clock signal from the clock generator 190, and determines the bus request. It has a function of selectively giving the bus use right to the issuing bus master sequentially. Each bus master issues a bus request to the arbitration unit 114 by activating the REQ signal line, and the arbitration unit 114 grants a bus use right to the bus master by activating the GNT signal line to any of the bus masters. Note that the bus master keeps the REQ signal line active as long as data transfer is necessary.
[0029]
<Data>
FIG. 2 is a diagram illustrating a data configuration and an example of contents of transfer rate information stored in the transfer rate information storage unit 111 transmitted from an external device.
As shown in the figure, the transfer rate information 300 is information in which a set of a request cycle 302 and one data transfer amount 303 is associated with each other for the bus masters A to C. For example, the transfer rate information is provided outside the LSI and includes a memory and a CPU, and an external device that controls the LSI 100 causes each bus master in the LSI to access the unified memory 200 and start processing involving data transfer. It is set before.
[0030]
Here, the request cycle 302 is a time interval in which the transfer rate required by each bus master is within a range to be maintained when there is data to be continuously processed. When there is data to be processed continuously, each bus master basically issues a bus request with a cycle of the request cycle 302 or less.
A single data transfer amount 303 is the amount of data that each bus master needs to transfer in the corresponding request cycle 302.
[0031]
In the example shown in the figure, when it is necessary to transfer data continuously, the bus master A must transfer data of 1000 kilobytes (KB) every 2000 microseconds (μs). This indicates that 100 KB of data must be transferred every 1000 μs, and the bus master C must transfer 400 KB of data every 4000 μs.
[0032]
That is, the bus master A is 2000. μ s is a bus master that needs to perform transfer while maintaining a transfer rate of 500 KB / ms. μ s is a bus master that needs to perform transfer with a transfer rate of 100 KB / ms, and the bus master C is 4000 μ The transfer rate information 300 in the figure indicates that the bus master needs to perform transfer while maintaining a transfer rate of 100 KB / ms in the range of s. Among the bus masters A to C, the bus master B has the smallest time margin for securing the transfer rate, and the bus master C has the largest time margin for securing the transfer rate.
[0033]
Note that an external device including a CPU or the like may determine transfer rate information 300 in accordance with the specifications of each bus master and input it to the memory control unit 110. Thus, a transfer rate that determines the control contents of the memory control unit 110 in this way. Since the information 300 can be externally input, the memory control unit 110 is general-purpose.
FIG. 3 is a diagram illustrating a data configuration and an example of contents of timing information generated in the timing information generation unit 112 and stored in the timing information storage unit 113.
[0034]
As shown in the figure, the timing information 400 includes a request detection period 401 and an intra-period bus use permission time 402 for each bus master.
Here, the request detection cycle 401 is information indicating time determined by the timing information generation unit 112 as an interval at which the arbitration unit 114 detects a bus request from the bus masters A to C.
[0035]
The intra-cycle bus use permission time 402 is a time during which each bus master should be allowed to use the memory bus, that is, the bus use so that each bus master can transfer necessary data in the request detection cycle 401. This is information indicating the time for which the right should be granted. Note that the bus bandwidth of the memory bus of the unified memory 200 is 800 KB / ms.
[0036]
Note that each time in the timing information is actually represented by, for example, the count of clock signals generated by the clock generator 190.
<Operation>
Hereinafter, the operation of the memory control unit 110 having the above-described configuration will be described.
In a state where the transfer rate information storage unit 111 stores the transfer rate information transmitted from the external device, the timing information generation unit 112 performs the operation shown in FIG.
[0037]
FIG. 4 is a flowchart showing the operation of the timing information generation unit 112.
The timing information generation unit 112 refers to the request cycle for each bus master included in the transfer rate information, and determines the shortest request cycle as the request detection cycle in the timing information (step S11).
Subsequently, the timing information generation unit 112 obtains the data transfer amount per request detection cycle for each bus master using the transfer rate information and the request detection cycle determined in step S11 (step S12), and the obtained data By dividing the transfer amount by the bus bandwidth of the memory bus, the in-period bus use permission time in the timing information is obtained (step S13). Note that the timing information generation unit 112 stores the bus bandwidth of the memory bus in a memory or the like inside the LSI, and performs the calculation in step S13 using this.
[0038]
Thus, the obtained timing information is stored in the timing information storage unit 113 by the timing information generation unit 112. Such an operation of the timing information generation unit 112 is assumed to be performed within a short period of time after the current starts to be supplied to the LSI, for example.
For example, the timing information generated by the timing information generation unit 112 based on the transfer rate information 300 having the contents illustrated in FIG. 2 has the contents illustrated in FIG.
[0039]
Next, an arbitration process performed by the arbitration unit 114 after timing information is generated will be described.
FIG. 5 is a flowchart illustrating an arbitration process performed by the arbitration unit 114.
Based on the timing information and the clock signal supplied from the clock generator 190 at regular intervals, the arbitration unit 114 waits for the time that arrives at each request detection period (hereinafter referred to as “request detection timing”), and detects the request. It is checked whether a bus request is issued from each bus master at the timing (step S21).
[0040]
The arbitration unit 114 determines whether or not a bus request from any of the bus masters has been detected at the time of the inspection in step S21 (step S22). If no bus request is detected from any of the bus masters, the arbitration unit 114 performs step The process returns to S21 and waits for the arrival of the next request detection timing.
If it is determined in step S22 that a bus request has been detected, the arbitrating unit 114 grants a bus use right to one of the bus masters that has issued the bus request (step S23).
[0041]
The arbitration unit 114 grants the bus use right to a certain bus master, and then waits for the bus use permission time within the period for the bus master to elapse by counting the clock signal. (Step S24). That is, in steps S23 and S24, a GNT signal line to a certain bus master is made active only during the intra-period bus use permission time, and thereafter made inactive.
[0042]
After step S24, the arbitrating unit 114 determines whether or not a bus request from a bus master different from the bus master that has already given the bus use right has been detected after the inspection at the time of the previous step S21 (step S25). If not detected, the process returns to step S21 to wait for the next request detection timing.
[0043]
If it is determined in step S25 that a bus request from a bus master different from the bus master that has already given the bus use right has been detected after the inspection, the arbitrating unit 114 returns to the process of step S23.
Therefore, when the passage of time is expressed as a continuation of the request detection cycle, the arbitration unit 114, for each request detection cycle, for each bus master that has issued a bus request before that cycle, for the corresponding bus use permission time in the cycle. Only the bus use right will be given.
[0044]
FIG. 6 is a timing chart showing temporal changes between the bus request from the bus masters A to C and the granting of the bus use right by the memory control unit 110.
This shows a result of the memory control unit 110 arbitrating memory access contention by each bus master based on the transfer rate information 300 illustrated in FIG.
As is apparent from the figure, the request detection cycle is 1000 μs in accordance with the bus master B having the shortest bus request cycle, and the bus masters A, B, and C that have issued a bus request at each request detection cycle are sequentially arranged. The right to use the bus is granted for each of 625 μs, 125 μs, and 125 μs. Since the bus bandwidth of the memory bus is 800 KB / ms, the bus master A is transferring data of 500 KB, the bus master B is 100 KB, and the bus master C is transferring data of 100 KB within the request detection period.
[0045]
Therefore, the bus master A transfers 1000 KB data at 2000 ms, the bus master B transfers 100 KB data at 1000 ms, and the bus master C transfers 400 KB data at 4000 ms. Data transfer can be performed with the accuracy required for the rate.
<Embodiment 2>
Hereinafter, the memory control unit according to the second embodiment of the present invention will be described. The memory control unit 110 shown in the first embodiment has a function of arbitrating memory access contention between the bus masters A to C that need to transfer data to and from the memory at a constant transfer rate. However, the memory control unit according to the second embodiment does not need to maintain a constant transfer rate, and does not need to maintain a constant transfer rate. Memory access between the bus masters A to D including the bus master D that performs data transfer with the memory irregularly It has a function to mediate the competition.
[0046]
<Configuration>
FIG. 7 is a configuration diagram of an LSI 500 including a memory control unit according to the second embodiment of the present invention. FIG. 7 shows the unified memory 200 in addition to the LSI 500.
The LSI 500 includes a memory control unit 510, a bus master A121, a bus master B122, a bus master C123, a bus master D124, and a clock generator 190, and is connected to the unified memory 200. Although not shown in FIG. 7, the LSI 500 is also connected to other external devices.
[0047]
Among the components of the LSI 500, the components that are basically the same as those of the LSI 100 shown in the first embodiment are denoted by the same reference numerals as those in FIG. 1 in FIG. 7, and detailed description thereof is omitted here. To do.
Here, the clock generator 190 is a circuit that supplies a clock signal to the memory control unit 510, the bus masters A to D, and the unified memory 200.
[0048]
The bus master D124 accesses the unified memory 200 and performs data transfer independently of the bus masters A to C. That is, the bus master D issues a bus request to the memory control unit 510 when data transfer is necessary, obtains the bus use right from the memory control unit 510, and obtains the bus use right while the clock generator 190 is obtained. The data is transferred in synchronism with the arbitration unit 514 of the memory control unit 510 at a timing based on the clock signal from.
[0049]
Note that the bus master D124 is different from the bus masters A to C that are required to perform data transfer at a constant transfer rate, that is, a type that periodically issues a bus request (hereinafter referred to as “periodic type”). A bus master that issues a bus request (hereinafter referred to as "irregular type"), for example, an MPU that receives an interrupt from the outside in response to an input from a user of a device on which an LSI is mounted, or the like. is there.
[0050]
In FIG. 7, bus requests from the respective bus masters are represented by REQ-A, REQ-B, REQ-C, and REQ-D, respectively, and the granting of the bus use right to each bus master is represented by GNT-A, GNT-B, It is represented by GNT-C and GNT-D. The memory control unit 510 arbitrates access to the unified memory 200 of the bus masters A to D based on transfer rate information transmitted from an external device. The transfer rate information storage unit 111, the timing information generation unit 112, a timing information storage unit 113, an arbitration unit 514, and an irregular master information storage unit 515.
[0051]
The irregular master information storage unit 515 is a memory area in which irregular master information indicating an irregular bus master is stored in advance. The irregular master information is information necessary for the arbitration unit 514 to recognize which of the irregular bus masters.
The arbitration unit 514 refers to the irregular master information stored in the irregular master information storage unit 515 and the timing information stored in the timing information storage unit 113, and performs predetermined processing based on the clock signal from the clock generator 190. At the timing, the bus master other than the irregular bus master, that is, the bus masters A to C of the regular bus masters is inspected for bus requests, and the bus master issuing the bus request is given the bus usage right sequentially. If there is still a time during which no bus use right is given to any of the bus masters A to C within the detection period, the bus use right is given to the irregular bus master as long as a bus request is issued from the irregular bus master. give.
[0052]
<Operation>
Hereinafter, the operation of the memory control unit 510 having the above-described configuration will be described.
The timing information generation unit 112 performs the same operation as that described in Embodiment 1 (see FIG. 4).
FIG. 8 is a flowchart illustrating an arbitration process performed by the arbitration unit 514.
[0053]
Based on the timing information and the clock signal supplied from the clock generator 190 at regular intervals, the arbitration unit 514 waits for the request detection timing to arrive, and each bus master other than the irregular bus master at the request detection timing, That is, it is checked whether or not a bus request is issued from each regular bus master (step S31).
[0054]
The arbitration unit 514 determines whether or not a bus request from any of the regular bus masters has been detected at the time of the inspection in step S31 (step S32).
If it is determined in step S32 that a bus request has been detected, the arbitration unit 514 grants a bus use right to one of the regular bus masters that issued the bus request (step S33), and counts the clock signal. By doing so, it waits for the bus use permission time within the period for the bus master to elapse, and stops giving the bus use right when the bus master passes (step S34). That is, in steps S33 and S34, the GNT signal line to one regular bus master is made active only during the intra-period bus use permission time, and thereafter inactive.
[0055]
After step S34, the arbitration unit 514 determines whether or not a bus request from a regular bus master different from the bus master that has already given the bus use right has been detected after the inspection at the time of the previous step S31. (Step S35).
In step S35, if it is determined that a bus request from a regular bus master that is different from the bus master that has already given the bus use right after the inspection has been detected at the time of the inspection in step S31, the arbitration unit 514 returns to the processing in step S33, and others. In this case, the arbitration unit 514 determines whether or not the next request detection timing has arrived (step S36). If it is determined that the next request detection timing has arrived, the process of step S31 is performed. .
[0056]
In step S32, if no bus request is detected from any bus master, the arbitrating unit 514 skips the processes of steps S33 to S35 and performs the determination process of step S36.
If it is determined in step S36 that the next request detection timing has not arrived, the arbitration unit 514 checks whether or not a bus request is issued from an irregular bus master (step S37). If a request is detected, the right to use the bus is given to the irregular bus master (step S38), and the bus request from the irregular bus master is canceled or the next request detection timing has arrived. At that time, the bus use right is stopped (step S39), and the process returns to the determination process of step S36.
[0057]
In step S37, the arbitration unit 514 also returns to the determination process in step S36 when a bus request from an irregular bus master is not detected.
Therefore, when the passage of time is expressed as a continuation of the request detection cycle, the arbitration unit 514 uses the bus within the corresponding cycle for each periodic bus master that has issued a bus request before that cycle in each request detection cycle. The right to use the bus is granted for the permitted time, and if a bus request is issued from the irregular bus master during the remaining time in the cycle, the bus usage right is granted to the irregular bus master.
[0058]
FIG. 9 is a timing chart showing temporal changes between bus requests from the bus masters A to D and granting of the bus use right by the memory control unit 510.
As shown in the figure, the arbitration unit 514 issues a bus request from the irregular bus master D for the remainder of the time when the bus usage right is granted to the regular bus masters A to C in each request detection cycle. Then, the bus master D is granted the bus use right.
[0059]
If the bus master D to which the bus use right is granted within the request detection period starting from a certain request detection timing arrives at the next request detection timing without stopping issuing the bus request within the request detection period, The assignment of the bus use right to the bus master D is cancelled. Also, if there is a regular bus master that has not issued a bus request at the request detection timing, the time during which the right to use the bus can be granted to the irregular bus master within the request detection period. become longer.
[0060]
<Modification of arbitration process>
Hereinafter, an example will be described in which the arbitration processing by the arbitration unit 514 described above is modified so that the bus use right is given to an irregular bus master earlier.
FIG. 10 is a flowchart illustrating a modification of the arbitration process performed by the arbitration unit 514.
[0061]
First, the arbitration unit 514 checks whether or not a bus request is issued from each of the regular bus masters when the request detection timing arrives, and within the cycle for all the bus masters for which the bus request has been detected. A total sum of bus use permission times is obtained, and a time obtained by subtracting the sum from the request detection period is determined as a surplus time (step S51). Here, the surplus time means a time during which the right to use the bus can be given to an irregular bus master within the request detection cycle.
[0062]
Subsequently, the arbitrating unit 514 determines whether or not a bus request from any of the regular bus masters has been detected at the time of the inspection in step S31 (step S52).
If it is determined in step S52 that a bus request has been detected, the arbitration unit 514 grants a bus use right to one of the regular bus masters that issued the bus request (step S53), and outputs a clock signal. By counting, it waits for the in-period bus use permission time for the bus master to elapse, and stops granting the right to use the bus when it elapses (step S54). That is, in steps S53 and S54, the GNT signal line to one regular bus master is made active only during the intra-period bus use permission time, and then inactive.
[0063]
If it is determined in step S52 that no bus request has been detected, the arbitration unit 514 skips the processes in steps S53 and S54 and performs the determination process in step S55.
After step S54, the arbitrating unit 514 determines whether the next request detection timing has arrived (step S55). If it has arrived, the process returns to step S51, and if not, the surplus time is not zero. Is determined (step S56).
[0064]
In step S56, when the arbitration unit 514 determines that the surplus time is not 0, that is, when it is determined that there is surplus time, the arbitration unit 514 checks whether a bus request is issued from an irregular bus master (step S56). S57), when a bus request is detected, the right to use the bus is granted to the irregular bus master, and the surplus time is counted down as the time for which the right to use the bus is granted (step S58). When the bus request from the irregular bus master is canceled or when the surplus time becomes 0, the assignment of the bus use right is stopped (step S59), and the process returns to the determination process of step S56 again.
[0065]
Note that the surplus time determined in step S51 is counted down by the amount of time for which the bus use right is granted to the irregular bus master in step S58. However, the surplus time countdown stops when the surplus time becomes zero.
If it is determined in step S56 that the surplus time is 0, or if a bus request from an irregular bus master is detected in step S57, the arbitration unit 514 has a regular type other than the bus master to which the bus use right has already been granted. It is determined whether or not a bus request from the bus master has been detected in step S51 (step S60). If not detected, the process returns to step S55, and if detected, the process returns to step S53.
[0066]
If the arbitration unit 514 determines in step S55 that the next request detection timing has arrived, the arbitration unit 514 performs processing in step S51 to inspect the bus request from each regular bus master at the next request detection timing. Return.
Through such a modified arbitration process, the arbitration unit 514 uses the bus for the period of time within the period of bus use permission to the periodic bus master that is transferring data when the irregular bus master issues a bus request. As soon as the right is granted, the right to use the bus is given to the irregular bus master, so that the irregular bus master can start data transfer promptly when the data transfer becomes necessary. That is, the arbitration unit can suppress the access latency for memory access by the irregular bus master by performing such a modified arbitration process.
[0067]
FIG. 11 is a timing chart showing temporal changes between a bus request from the bus masters A to D and the granting of the bus use right by the memory control unit 510 when the arbitration processing performed by the arbitration unit 514 is modified.
As shown in the figure, when the bus request is issued from the irregular bus master D while the arbitration unit 514 grants the bus use right to the regular bus master A, the bus master D follows the bus master A. To the regular bus masters B and C, and sequentially grants the bus use right to the regular bus masters A and B in the next request detection cycle. If a bus request is issued from the irregular bus master D while the bus usage right is being granted, the bus master B is given the bus usage right after the bus master B, and then the bus usage right is given to the regular bus master C. Is granted.
<Supplement>
Although the memory control device according to the present invention has been described based on the first and second embodiments, the present invention is of course not limited to these embodiments. That is,
(1) The number of bus masters shown in both embodiments is not limited as long as there are a plurality of bus masters. However, for all regular bus masters, transfer rate information indicating the transfer rate and the time interval within which the transfer rate should be maintained must be input to the LSI. If there is an irregular bus master, The irregular master information for identifying all irregular bus masters needs to be stored in the irregular master information storage unit 515.
[0068]
Note that a plurality of unified memories may be connected to the LSI. In this case, the memory control unit accesses the unified memory for each unified memory as described in the first or second embodiment. Any device that arbitrates access contention between all bus masters may be used.
(2) The memory control unit 110 shown in the first embodiment and the memory control unit 510 shown in the second embodiment may all be constructed as a hardware circuit, or consist of an MPU and a memory. The MPU may be configured to realize an arbitration function by executing the program.
(3) In both embodiments, the transfer rate information is information consisting of the request cycle for each bus master and the amount of data transferred once, but the transfer rate information guarantees the transfer rate and the transfer rate. Any combination of information may be used as long as the information indicates the minimum time interval to be performed.
(4) Although the transfer rate information shown in both embodiments is input from an external device, an initial value may be stored in advance.
[0069]
The transfer rate information can be input at any time, and the timing information generation unit 112 generates timing information based on the transfer rate information and stores it in the timing information storage unit 113 each time the transfer rate information is input. It is good to do. Since the arbitration unit 114 and the arbitration unit 514 determine the time for granting the bus use right to each bus master based on the timing information, dynamic arbitration control is realized.
[0070]
In the second embodiment, the bus master is classified into a regular type and an irregular type, but this is a classification depending on whether or not data transfer requiring a guaranteed transfer rate is performed, and is input to the LSI from the outside. Depending on the contents of the transfer rate information, even the same bus master may be a regular type or an irregular type.
(5) The bus bandwidth of the memory bus referred to by the timing information generator 112 shown in both embodiments may be input from outside the LSI.
(6) The memory control unit 110 shown in the first embodiment and the memory control unit 510 shown in the second embodiment transmit information for specifying request detection timing such as a request detection cycle to each bus master. In response to this, each bus master may issue a bus request in accordance with the request detection timing.
(7) In both embodiments, the grant of the bus use right to the bus master is realized by activating the GNT signal line, and the stop of the grant of the bus use right is realized by making the GNT signal line inactive. However, the present invention is not limited to these implementation methods, and may be implemented by any method as long as it can notify the bus master of permission and prohibition of bus use.
[0071]
For example, the bus mastership is notified to the bus master by instantaneously activating one signal line, and the bus mastership is notified to the bus master by instantaneously activating another signal line. It is good as well.
In the regular bus master shown in the embodiment, the REQ signal line is kept active as long as data transfer is necessary, but the method of issuing a bus request is not limited to this. For example, the memory control unit 110 and the memory control unit 510 may notify each bus master of the amount of data that can be transferred within the request detection period based on the transfer rate information, and each bus master notifies the notified data. If transmission of a quantity is required, the REQ signal line may be activated instantaneously.
(8) The unified memory 200 shown in both embodiments is not limited to a memory having a specific memory architecture, and any memory may be used.
[0072]
In addition, the memory bus that connects the bus master and the unified memory shown in both embodiments may be composed of separate signal lines for the address bus and the data bus, or may be composed of a common signal line. It is good. When configured with a common signal line, address information and data are transmitted in a time division manner between the bus master and the unified memory. The bus between the bus master and the unified memory may be connected through an interface unit in the memory control unit, and processing such as address decoding may be performed in the interface unit.
(9) In the LSI shown in each embodiment, it is basically assumed that each bus master accesses a memory area independent from each other in one unified memory. The memory area may be accessed.
(10) In the second embodiment, the timing information generation unit 112 sets the shortest request cycle among the request cycles of the regular bus master indicated in the transfer rate information as a request detection cycle, and issues a bus request for each request detection cycle. The right to use the bus is given to each regular bus master, but the request detection cycle may be equal to or shorter than the shortest request cycle of the regular bus master.
[0073]
For example, half the shortest request cycle of a regular bus master may be determined as the request detection cycle. If the request detection cycle is shortened, the right to use the bus is granted after receiving a bus request from an irregular bus master. It is possible to shorten the time required for the process.
It should be noted that information indicating how much time is used as the request detection cycle for the shortest request cycle of the regular bus master can be input from outside the LSI, and based on the information The request detection cycle may be determined.
[0074]
【The invention's effect】
As described above, the memory control device according to the present invention adjusts the access conflict to the memory by selectively granting the right to use the memory bus to any of a plurality of bus masters sharing the memory. For each of a plurality of bus masters, a transfer indicating a transfer rate at which the bus master transfers data to and from the memory and a time interval that defines a range in which the transfer should be guaranteed at the transfer rate A holding means for holding rate information, a unit time calculating means for setting a time equal to or less than the smallest one of the time intervals corresponding to each bus master as a unit time, and transferring for each bus master in the unit time at a corresponding transfer rate When the amount of data that can be obtained is V, V transfer is required based on the bus bandwidth of the memory bus. Bus usage permission time calculating means for obtaining a bus usage permission time between the buses, and corresponding bus usage for each bus master in each of a plurality of unit time zones obtained by periodically dividing the elapsed time into the unit times. Usage right granting means for granting the right to use the memory bus only for the permitted time.
[0075]
In addition, the memory control device according to the present invention arbitrates contention for access to the memory by selectively granting the right to use the memory bus to a plurality of bus masters that access mutually independent memory areas in one memory. A memory control device for each of a plurality of bus masters, which defines a transfer rate when the bus master transfers data to and from the memory and a time interval that guarantees transfer at the transfer rate Holding means for holding transfer rate information indicating unit time, a unit time calculation means for setting a time equal to or less than the smallest one of the time intervals corresponding to each bus master as a unit time, and for each bus master, depending on the corresponding transfer rate Based on the bus bandwidth of the memory bus when the amount of data that can be transferred in unit time is V A bus use permission time calculating means for obtaining a bus use permission time which is a time required for the transfer of V, and each bus master in each of a plurality of unit time zones obtained by periodically dividing the passage of time by the unit time. And usage right granting means for granting the right to use the memory bus for the corresponding bus usage permission time.
[0076]
As a result, even if the conditions related to the transfer rate requested by each bus master are not uniform, the transfer rate should be adjusted so that the conditions related to the transfer rate of the bus master with the minimum waiting time for transfer can be satisfied. As a result, each bus master can perform data transfer with a constant transfer rate with the required time accuracy.
[0077]
In addition, when this memory control device is used, even when it is necessary to change the conditions regarding the transfer rate of each bus master, it is possible to rewrite the stored transfer rate information at a transfer rate according to the request of each bus master. Each bus master can transfer data to and from the memory. From this, it can be said that this memory control device can be utilized even if the bus master subject to access contention control is replaced.
[0078]
Here, the memory control device includes a detecting unit that detects a bus request from each bus master, and the usage right granting unit detects a bus request before the start of each unit time zone by the detecting unit. However, the right to use may be given to each bus master in the unit time zone.
As a result, the bus master sharing the memory can obtain the bus use right and perform data transfer at the required transfer rate by issuing a bus request when there is data to be transferred. As a result, the circuit configuration of the memory controller is simpler than when a bus request is detected within a unit time and a bus master issuing the bus request is granted a bus use right within the unit time. Can be anything.
[0079]
The bus masters can be classified into regular bus masters that require a constant transfer rate to be maintained when data is transferred to and from the memory, and other irregular bus masters. The transfer rate information is held for each of the periodic bus masters, the bus use permission time calculating means obtains the bus use permission time for each of the periodic bus masters, and the use right granting means is for each unit time. In each band, each regular bus master where a bus request is detected before the start of the unit time slot is granted the right to use the memory bus for the corresponding bus use permission time, and the bus request is detected by the detecting means. The total bus use permission time corresponding to each scheduled bus master is subtracted from the unit time to obtain the remaining time. May be irregularly-type bus master to grant the bus use right of the memory bus as a limit.
[0080]
As a result, even when a regular bus master that needs to transfer data at a constant transfer rate and other irregular bus masters share memory, the regular bus master can transfer data with the required temporal accuracy. It becomes possible to perform data while keeping the constant.
In addition, the usage right granting unit, if a bus request from an irregular bus master is detected while the bus usage right is given to the regular bus master by the detection unit in each unit time zone, As soon as the grant of the bus use right to the regular bus master is completed, the bus use right may be granted to the irregular bus master.
[0081]
As a result, the irregular bus master can transfer data quickly after the necessity of data transfer occurs.
The holding unit may acquire and transfer the transfer rate information from outside the memory control device.
As a result, even when the transfer rate needs to be changed by changing the function of each bus master, etc., it is possible to provide appropriate transfer rate information from the outside. As a result, contention for memory access between the bus masters is appropriately arbitrated. Will come to be.
[0082]
Further, the holding unit may hold the transfer rate information in an area that can be rewritten by a device external to the memory control device.
Thereby, even when it is necessary to change the transfer rate of each bus master, the contention of memory access between the bus masters can be appropriately arbitrated by rewriting transfer rate information from the outside as needed.
[0083]
Further, the memory control device is connected to each bus master by each signal line for bus use permission, and the use right granting unit grants the bus use right to the bus master only for the bus use permission time. The signal line connected to the bus master may be activated only for the bus use permission time.
As a result, it is possible to easily realize the right to use the bus with limited time by using one signal line.
[0084]
The unit time calculation means may determine the time of the smallest time interval corresponding to each bus master as a unit time.
As a result, the transfer rate of each bus master can be adjusted relatively easily by using the bus master with the smallest transfer waiting margin as a reference.
In addition, the LSI according to the present invention includes a plurality of circuits sharing a memory, and a memory control that arbitrates a memory access conflict by selectively granting a right to use a memory bus to any one of the plurality of circuits. And each of the circuits is a circuit that requires data to be transferred to and from a memory at a constant transfer rate. Corresponding to each circuit, and holding means for holding transfer rate information indicating a transfer rate at the time of transferring data to and a time interval that defines a range in which the transfer should be guaranteed at the transfer rate Unit time calculation means for determining a time less than the smallest one of the time intervals as a unit time, and each circuit can be transferred to the unit time at a corresponding transfer rate. Bus usage permission time calculating means for obtaining a bus usage permission time which is a time required for V transfer based on the bus bandwidth of the memory bus when the data amount is V, and the time passage is periodically divided into the unit times. In each of the plurality of unit time zones obtained in this manner, each circuit is provided with usage right granting means for granting the right to use the memory bus for the corresponding bus usage permission time.
[0085]
As a result, each of the plurality of internal circuits of the LSI can perform data transfer with a necessary transfer rate with a necessary time accuracy with respect to the memory shared with each other.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an LSI 100 including a memory control unit according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a data configuration and an example of contents of transfer rate information stored in a transfer rate information storage unit 111 transmitted from an external device.
FIG. 3 is a diagram illustrating a data configuration and example contents of timing information generated by the timing information generation unit 112 and stored in the timing information storage unit 113;
FIG. 4 is a flowchart showing the operation of the timing information generator 112;
FIG. 5 is a flowchart showing an arbitration process performed by an arbitration unit 114;
FIG. 6 is a timing chart showing temporal changes between bus requests from bus masters A to C and granting of bus use rights by the memory control unit 110;
FIG. 7 is a configuration diagram of an LSI 500 including a memory control unit according to a second embodiment of the present invention.
FIG. 8 is a flowchart showing an arbitration process performed by an arbitration unit 514;
FIG. 9 is a timing chart showing a temporal change between a bus request from the bus masters A to D and grant of a bus use right by the memory control unit 510;
FIG. 10 is a flowchart illustrating a modification of the arbitration process performed by the arbitration unit 514.
FIG. 11 is a timing chart showing temporal changes between bus requests from bus masters A to D and granting of bus use rights by the memory control unit 510 when the arbitration process performed by the arbitration unit 514 is modified.
[Explanation of symbols]
100, 500 LSI
110, 510 Memory control unit
111 Transfer rate information storage unit
112 Timing information generator
113 Timing information storage unit
114, 514 Mediation Department
121-124 Bus master
190 Clock generator
200 unified memory
515 Irregular master information storage unit

Claims (19)

A memory control device that arbitrates access conflict to a memory by selectively granting the right to use the memory bus to any of a plurality of bus masters sharing the memory,
For each of the bus masters, holds transfer rate information indicating the transfer rate at which the bus master transfers data to and from the memory and the request cycle that defines the range in which transfer should be guaranteed at the transfer rate. Holding means to
A request detection cycle calculating means for determining as a request detection cycle the following times the smallest of the request period corresponding to each bus master,
For each bus master, when the amount of data that can be transferred in the request detection period according to the corresponding transfer rate is V, the bus use permission for obtaining the bus use permission time that is the time required for V transfer based on the bus bandwidth of the memory bus Time calculation means;
Usage right granting means for granting a right to use a memory bus to each bus master for a corresponding bus usage permission time in each of a plurality of request detection cycle bands obtained by periodically dividing the passage of time into the request detection cycles. A memory control device comprising: The memory control device includes detection means for detecting a bus request from each bus master,
The assignment of the right to use means, by said detecting means, for each bus master where the beginning before bus request each request detection cycle period is detected, to grant the right to use in the request detection cycle period The memory control device according to claim 1, wherein: The bus master can be classified into a regular bus master that requires a constant transfer rate to be maintained when transferring data to and from the memory, and other irregular bus masters,
The holding means holds the transfer rate information for each of a plurality of regular bus masters, and the bus use permission time calculating means obtains the bus use permission time for each regular bus master,
The right-of-use granting means, in each of the request detection period bands, uses the right to use the memory bus for the corresponding bus use permission time to each periodic bus master where a bus request is detected before the start of the request detection period band. The bus use permission time corresponding to each periodic bus master where the bus request is detected by the detection means is set to the remaining time obtained by subtracting the remaining time subtracted from the request detection cycle as an upper limit. The memory control device according to claim 2, wherein a right to use the memory bus is given to the memory control device. The right-of-use granting means, if a bus request from an irregular bus master is detected while the right of bus use is granted to the regular bus master by the detection means in each request detection period band, 4. The memory control device according to claim 3, wherein the right to use the bus is granted to the irregular bus master as soon as the right to use the bus to the type bus master ends. The memory control device according to claim 4, wherein the holding unit acquires and holds the transfer rate information from outside the memory control device. The memory control device according to claim 4, wherein the holding unit holds the transfer rate information in an area that can be rewritten by a device external to the memory control device. The memory control device is connected to each bus master via each signal line for bus use permission,
The right-of-use granting means assigns a bus use right to the bus master only for the bus use permission time by activating the signal line connected to the bus master for the bus use permission time. The memory control device according to claim 4. The memory control device according to claim 1, wherein the request detection cycle calculation unit determines a time of the smallest request cycle corresponding to each bus master as a request detection cycle . The memory control device according to claim 1, wherein the holding unit acquires and holds the transfer rate information from outside the memory control device. A memory control device that arbitrates access conflict to a memory by selectively granting a right to use a memory bus to a plurality of bus masters that access mutually independent memory areas in one memory,
For each of the bus masters, holds transfer rate information indicating the transfer rate at which the bus master transfers data to and from the memory and the request cycle that defines the range in which transfer should be guaranteed at the transfer rate. Holding means to
A request detection cycle calculating means for determining as a request detection cycle the following times the smallest of the request period corresponding to each bus master,
For each bus master, when the amount of data that can be transferred in the request detection period according to the corresponding transfer rate is V, the bus use permission for obtaining the bus use permission time that is the time required for V transfer based on the bus bandwidth of the memory bus Time calculation means;
Usage right granting means for granting a right to use a memory bus to each bus master for a corresponding bus usage permission time in each of a plurality of request detection cycle bands obtained by periodically dividing the passage of time into the request detection cycles. A memory control device comprising: The memory control device includes detection means for detecting a bus request from each bus master,
The assignment of the right to use means, by said detecting means, for each bus master where the beginning before bus request each request detection cycle period is detected, to grant the right to use in the request detection cycle period 11. The memory control device according to claim 10, wherein: The bus master can be classified into a regular bus master that requires a constant transfer rate to be maintained when transferring data to and from the memory, and other irregular bus masters,
The holding means holds the transfer rate information for each of a plurality of regular bus masters,
The bus use permission time calculating means obtains the bus use permission time for each regular bus master,
The right-of-use granting means, in each of the request detection period bands, uses the right to use the memory bus for the corresponding bus use permission time to each periodic bus master where a bus request is detected before the start of the request detection period band. The bus use permission time corresponding to each periodic bus master where the bus request is detected by the detection means is set to the remaining time obtained by subtracting the remaining time subtracted from the request detection cycle as an upper limit. The memory control device according to claim 11, wherein a right to use the memory bus is given to the memory control device. The right-of-use granting means, if a bus request from an irregular bus master is detected while the right of bus use is granted to the regular bus master by the detection means in each request detection period band, 13. The memory control device according to claim 12, wherein the right to use the bus is granted to the irregular bus master as soon as the right to use the bus to the type bus master ends. An LSI including a plurality of circuits sharing a memory, and a memory control device that arbitrates access conflict to the memory by selectively granting the right to use the memory bus to any of the plurality of circuits,
Each circuit is a circuit that requires data to be transferred to and from a memory at a constant transfer rate,
The memory control device indicates, for each of the circuits, a transfer rate at which the circuit transfers data to and from the memory and a request cycle that defines a range in which transfer is guaranteed to be performed at the transfer rate. Holding means for holding transfer rate information;
A request detection cycle calculating means for determining as a request detection cycle the following times the smallest of the request period corresponding to each circuit,
For each circuit, the bus use permission for obtaining the bus use permission time, which is the time required for the transfer of V, based on the bus bandwidth of the memory bus, where V is the amount of data that can be transferred in the request detection cycle at the corresponding transfer rate Time calculation means;
Usage right granting means for granting the right to use the memory bus to each circuit for the corresponding bus usage permission time in each of a plurality of request detection cycle bands obtained by periodically dividing the passage of time into the request detection cycles. An LSI characterized by comprising: 15. The LSI according to claim 14, wherein each of the circuits is a circuit that transfers data to and from memory areas independent of each other in the memory. The memory control device includes detection means for detecting a bus request from each circuit,
The assignment of the right to use means, by said detecting means, to each circuit at which the previously bus request the beginning of each request detection cycle period is detected, to grant the right to use in the request detection cycle period 15. The LSI according to claim 14, wherein: The circuit can be classified into a regular bus master that requires a constant transfer rate to be maintained when transferring data to and from the memory, and other irregular bus masters,
The holding means holds the transfer rate information for each of a plurality of regular bus masters,
The bus use permission time calculating means obtains the bus use permission time for each regular bus master,
The right-of-use granting means, in each of the request detection period bands, uses the right to use the memory bus for the corresponding bus use permission time to each periodic bus master where a bus request is detected before the start of the request detection period band. The bus use permission time corresponding to each periodic bus master where the bus request is detected by the detection means is set to the remaining time obtained by subtracting the remaining time subtracted from the request detection cycle as an upper limit. 17. The LSI according to claim 16, wherein a right to use the memory bus is given to the LSI. The right-of-use granting means, if a bus request from an irregular bus master is detected while the right of bus use is granted to the regular bus master by the detection means in each request detection period band, 18. The LSI according to claim 17, wherein the right to use the bus is granted to the irregular bus master as soon as the right to use the bus to the type bus master ends. 15. The LSI according to claim 14, wherein the holding unit acquires and holds the transfer rate information from outside the LSI.

Images