JPH0962640A - Access control method for shared memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the method which efficiently use processors by eliminating the idle time of a bus cycle as to a system which performs data transfer between the processors through a shared memory. SOLUTION: This method is equipped with a shared memory circuit 102 which has the shared memory 103, a port arbitration process part 104, and a ready process part 105 outputting a BUSY signal 202, a BUSY control circuit 106 which detects the BUSY signal and an acquisition reservation interruption signal 203 from a processor 101 and outputs a/CS reservation signal 206, and an OR circuit 107 which ORs a /CS signal and the /CS reservation signal and outputs the result as a /CS signal to the shared memory 103. When the processor 101 receives an interruption pulse signal 201 as the result of access to the shared memory circuit 102, the state of access to the shared memory 102 is maintained if the BUSY signal from the shared memory circuit 102 is Low, but when the signal is High, the state of access to the circuit is interrupted and an acquisition reservation interruption signal is sent out to the BUSY control circuit 106.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system in which a plurality of CPUs use a common memory, and more particularly to a shared memory bus access method in a multiprocessor system.

[0002]

2. Description of the Related Art Conventionally, in a shared memory access method of a multiprocessor system, when a processor on a first-arrival port side is accessing, a port arbitration function works and a processor on a second-arrival port side has an access right to the shared memory. Cannot be acquired, and the wait state remains until the shared memory is released. That is, the BUSY signal issued by the ready function unit of the shared memory circuit causes the processor on the last-arrival port side to wait the access cycle to the shared memory until the processor on the first-arrival port side finishes processing. FIG. 3 is a diagram for explaining this situation, and is a time chart from the shared memory acquisition request to the acquisition completion. First, when the processor requests access to the shared memory, the shared memory circuit 102 outputs an interrupt pulse signal 201 which is an answerback signal. Then B
The USY signal 202 is checked, and if the shared memory is in the BUSY state (H level) indicating that another processor is still in use, the processor enters the wait state, and enters the idle state while the shared memory cannot be accessed. BUS
When the Y signal 202 becomes L level, the processor is activated,
Start shared memory access.

[0003]

In the prior art, as described above, there was an idle time during which no processing could be performed while the processor was in the wait state. In particular, in a controller system that requires high-speed processing, when the processor on the first-arrival port side is transferring a large amount of data, there is a problem that if the idle time becomes long, the processing on the second-arrival processor is affected. there were. Therefore,
An object of the present invention is to eliminate the idle time of the bus cycle and effectively use the memory bus to efficiently use the processor.

[0004]

In order to solve the above-mentioned problems, according to the present invention, the shared memory 103 and the port arbitration processing unit 104 which gives the access right to the port are provided.
And a BUSY signal 2 that puts the processor in the wait state
Shared memory circuit 102 having ready processing section 105 for outputting 02, BUSY signal 202 and processor 10
A BUSY control circuit 106 which detects the acquisition reservation interrupt signal 203 from the 1 and outputs a / CS reservation signal 206;
S signal (chip select signal) and the / CS reservation signal 2
06 and the shared memory circuit 102 with / C
When the processor 101 receives an interrupt pulse signal 201 which is an answerback signal resulting from access to the shared memory circuit 102, the BUSY signal 2 from the shared memory circuit 102 is provided.
If 02 is Low, the access state to the shared memory circuit 102 of the processor 101 is continued, and if the BUSY signal 202 is High, the access state to the shared memory circuit 102 of the processor 101 is interrupted and the acquisition reservation allocation is performed. Send the embedded signal 203 to the BUSY control circuit 106,
The BUSY control circuit 106 is connected via the OR circuit
By sending the CS reservation signal 206 to the shared memory circuit 102, the processor 101 is made to operate in the shared memory 103.
Access to the reserved state, and during the reserved state,
The processor 101 uses the non-shared memory 108 to execute input / output processing.

[0005]

According to the above means, the processor of the late arrival port can effectively use the memory bus at the time of accessing the shared memory without keeping the bus cycle in the wait state by the BUSY selection function.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, in which 100 is a first processor system in a multiprocessor system and 300 is a second processor system in the multiprocessor system.
Processor system, 101 is a processor (CP
U), 102 is a shared memory circuit, 103 is a shared memory,
104 is a port arbitration processing unit, 105 is a ready processing unit, 106 is a BUSY control circuit, and 107 is an OR.
The circuit, 108 is a non-shared memory (RAM). When the processor 101 accesses the shared memory circuit 102, the interrupt pulse signal 201 is received from the shared memory circuit 102 as an answerback signal.
A method in which the processor 101 waits for an access to the shared memory circuit 102 when is already occupied by another processor will be described. When the processor 101 (late arrival processor) accesses the shared memory circuit 102, the port arbitration processing unit 104 and the ready processing unit 105 that determine the usage state of the shared memory 103.
And outputs a BUSY signal 202 indicating the usage state of the shared memory 103 by the other processor to the last-arriving processor 101. When the processor 101 receives the interrupt pulse signal 201 and the BUSY signal 202 is at the H level, the shared memory 103 is occupied by another processor and B
Since it is in the USY state, the acquisition reservation interrupt signal 203 is BU
It outputs to the shared memory circuit 102 via the SY control circuit 106 and the OR circuit 107, and continues to maintain the access state. In this way, the late arrival processor 101 continuously outputs an access request to the shared memory 103 and waits for the shared memory to become empty. During this period, the processor 101 continuously executes input / output processing with the outside, such as accessing the non-shared memory 108. After that, when the other processor finishes the access to the shared memory 103, the BUSY signal 202 becomes Low level, and the acquisition completion interrupt signal 204
Is detected, the acquisition reservation interrupt signal 203 is released (L
Then, the access processing to the shared memory circuit 102 is executed. FIG. 2 is a time chart from a shared memory acquisition request to acquisition completion according to the present invention. First, when the last-arriving processor (the processor 101 configuring the processor system 100 in the example of FIG. 1) accesses the shared memory circuit 102, the shared memory circuit 102
Outputs an interrupt pulse signal 201 as an answerback to the late arrival processor. Next, the BUSY signal 20
If the shared memory is in a BUSY state (H level) indicating that the first arrival processor is still in use, the first arrival processor does not use the shared memory and sets the acquisition reservation interrupt signal 203 to the H level, While the shared memory cannot be accessed, I / O processing with the outside such as accessing the non-shared memory is continuously executed. When the acquisition completion interrupt signal 204 is detected, the acquisition reservation interrupt signal 203 is set to the low level, and then the access processing of the shared memory not executed at the acquisition request is started.

[0007]

As described above, according to the present invention,
When accessing the shared memory, the memory bus can be effectively used without putting the bus cycle of the processor of the last arrival port in the wait state, and the processing speed of the controller system can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a specific embodiment of the present invention.

FIG. 2 is a time chart of memory access according to the present invention.

FIG. 3 is a time chart of memory access according to the related art.

[Explanation of symbols]

 100 first processor system 101 processor (CPU) 102 shared memory circuit 103 shared memory 104 port arbitration processing unit 105 ready processing unit 106 BUSY control circuit 107 OR circuit 108 non-shared memory 300 second processor system

Claims (1)

[Claims] 1. A shared memory access control method for a multiprocessor system for performing data transfer between processors via a shared memory, comprising: a shared memory 103; a port arbitration processing unit 104 for giving access right to a port; A shared memory circuit 102 having a ready processing unit 105 for outputting a BUSY signal 202 to bring it into a state, and a BUSY control for detecting a BUSY signal 202 and an acquisition reservation interrupt signal 203 from the processor 101 and outputting a / CS reservation signal 206. A circuit 106 and an OR circuit 107 for calculating a logical sum of the / CS signal and the / CS reservation signal 206 and outputting it to the shared memory circuit 102 as a / CS signal are provided, and the processor 101 accesses the shared memory circuit 102. The interrupt answer that is the resulting answerback signal Ruth signal 201
BUSY from the shared memory circuit 102 when
If the signal 202 is low, the processor 101 continues to access the shared memory circuit 102. If the BUSY signal 202 is high, the processor 1
01, the access state to the shared memory circuit 102 is interrupted, and the acquisition reservation interrupt signal 203 is sent to the BUSY control circuit 10.
6, and the BUSY control circuit 106 sends a / CS reservation signal 206 to the shared memory circuit 102 via the OR circuit to place the processor 101 in the reserved state for access to the shared memory 103. During the reserved state, the processor 101 uses the non-shared memory 1
A method for controlling access to a shared memory, characterized in that input / output processing is executed using 08.