JPH096733A - Parallel signal processor - Google Patents

Abstract

PURPOSE: To easily communicate data having different rates between processors. CONSTITUTION: Plural process units PU1-PU2 are provided with main processors CP11, CP21..., plural communication registers RE11, RE12, RE21, RE22... including output and input registers, communication control parts CC11, CC12, CC21, CC22... and a switch SW for sending data outputted from the communication register to a prescribed data line. The control of any arbitrary communication register, communication control part and switch are combined with each other to construct a first communication control means for controlling communication synchronously with the first transmission rate and a second communication control means for controlling communication synchronously with the second transmission rate, and respective communication means are executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel signal processing device having an improved communication function between parallel processors.
It is suitable for processing video signals and the like.

[0002]

2. Description of the Related Art An apparatus for signal processing using a parallel processor or a multiprocessor arranged in a matrix has been developed. In this device, interprocessor communication is required for exchanging data between the processors, and various interprocessor communication methods have been proposed.

For example, a paper (Karl Guttag, et.all 'A Sin
gle-Chip Multiprocessor For Multimedia: The MVP ', IE
(EE Computer Graphics & Application, pp53-64,1992)
Shows four processors, four shared memories and a network connecting them.

FIG. 6 (a) generally shows the apparatus described in the above document in a simplified form. This device basically includes processor units (PU) 11 to 14, a shared memory 15, and a bus 16. In the above-mentioned document, a shared memory is further added and a plurality of shared memories and a plurality of processor units are connected by a crossbar network.

Further, FIG. 6 (b) shows in Japanese Patent Laid-Open No. 5-2603.
Japanese Patent Publication No. 75 discloses a system disclosed as a parallel signal processing device for video signal processing. In this system,
A network switch 21 is provided so that many processors 11 to 14 can be directly connected. If this network switch 21 is provided, the scale becomes large,
The range of use is limited to business such as broadcasting stations.

Consider, for example, the case where a signal having a different data rate is to be processed. In the configuration of FIG. 6A, the processing system of the signal rate DCK2 shown by the dotted line is added to the processing system of the signal rate DCK1 shown by the solid line. However, the problem of signal group delay occurs, and depending on the arbitration of the bus, the signal group delay may differ even in the processing at the same signal rate. In the configuration of FIG. 6B, the signal rate DC indicated by the solid line
The processing system of the signal rate DCK2 is added to the processing system of K1 as shown by the dotted line.
However, in this case, the network switch becomes a crossbar switch type, which further increases the scale of this network.

Here, the different data rates mean the following. For example, in a reproduction signal from a home VTR, the color subcarrier is stable but the color envelope has jitter. Therefore, for color demodulation, the burst lock clock 4 phase-locked to the burst signal is used.
fsc is used, on the other hand, for noise reduction processing, a horizontal synchronization lock clock 910 phase-locked to the horizontal synchronization signal is used.
It is desired to treat with fh. Both (4f
sc, 910fh) may have the same frequency but different data rates. In this way, clocks DCK1, D
The phase relationship of the clock of CK2 is irrelevant, or the relationship that the least common multiple becomes gigahertz even if it is a rational multiple is referred to as different data rates.

[0008]

In the conventional parallel signal processing device described above, for example, when a common bus is used,
When communication is performed between a processor that processes a video signal with a data rate of 1 and a processor that processes a video signal with a data rate of 2, the delay in data communication may differ depending on the arbitration of the bus. It becomes impossible to manage.

Therefore, an object of the present invention is to provide a parallel signal processing device capable of stably performing communication between processors even when data rates are different.

[0010]

According to the present invention, there are provided a plurality of process units, a main processor provided in each process unit, and a plurality of communication registers including output and input registers, which are connected to the main processor. The communication control unit is provided corresponding to each of the plurality of communication registers, and a switch unit for sending the data output from the communication register to a predetermined data line when controlled by the communication control unit. A parallel signal processing device, comprising: first communication control means for controlling communication in synchronization with a first transmission rate, by combining the arbitrary communication register, communication control section, and switch means; and the arbitrary communication register. , The communication control unit and the switch means are combined,
Second communication control means for controlling communication in synchronization with a second transmission rate is constructed, the first communication means executes communication at the first transmission rate, and the second communication means It has means for executing communication at the second transmission rate.

[0011]

By the above means, it is possible to stably carry out communication at different data rates among a plurality of processors, and to send out different data rates even within the same processor.
Reception can be performed stably.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention, in which PU1, P
U2, PU3, ... PUn are process units having the same structure. In the figure, the internal structures of the process units PU1 and PU2 are shown in detail as a representative. The internal structure of the process unit PU2 will be described. First, the main processor C
There is P21, for which the communication register RE21,
RE22 is connected. In addition, the communication register RE1,
Communication controllers CC21 and CC22 corresponding to RE2 are provided. The communication control units CC21 and CC22, under the control of the main processor CP21, control the corresponding communication registers RE21 and RE22 and also control the bus interface switch SW.

Here, each process unit PU1 to PU
For the communication control units CC21 and CC22 in n, the communication clocks CCK1 and CCK from the clock generating means 30.
2 and data rate clocks DCK1 and DCK2 are commonly supplied.

The main processor CP21 has a professional communication control section CC1 for communicating with other process units.
It controls CC2, sends data to the communication registers RE1 and RE2, and receives data from the communication registers RE1 and RE2. In addition, arithmetic processing (signal processing) of internal data is performed.

The bus interface switch SW can select an independent path (bus) according to the type of data rate clock. Therefore, as many paths (buses) as the number of data rate clocks are prepared.

In the above system, there are the following operating states. (A) Each of the process units PU1 to PUn is processing a single data rate signal. (B) PU1 is
A state in which the data is being processed by the data rate clock DCK1 and the PU2 is being processed by the data rate clock DCK2. In other words, each process unit alone processes data with a single data rate clock, but the entire system performs signal processing with multiple data rate clocks. (C) The communication register RE21 of PU2 uses the data rate clock DCK1.
However, the communication register RE22 is communicating with the data rate clock DCK2. In other words, the state where the PU alone is processing signals at multiple data rates.

In the above-mentioned states (a), (b) and (c), the state (a) is the same as that in normal communication, and therefore its explanation is omitted. In the case of the state (b), the process unit PU
2, the communication control unit CC21, the communication register RE21
Operates with the data rate clock DCK2, can send data to the bus selected by the switch SW for the data rate clock DCK2, and can introduce data from the bus. Further, for example, the communication control unit CC11 and the communication register RE11 in the process unit PU1 operate by the data rate clock DCK1, and data can be sent to the bus selected by the switch SW for the data rate clock DCK1, and from the bus. Data can be introduced.

The other process units that receive the data transmitted by the data rate clock DCK2 described above are also set to operate at the data rate clock DCK2, and also receive the data transmitted by the data rate clock DCK1. The other process units are also set to operate at the data rate clock DCK1. In such processing, for example, the data rate clock DCK1 is a clock of 4 fsc and the data rate clock DCK2 is a clock of 910 fh. Such a processing mode is suitable, for example, in the case where the arithmetic processing for ACC and the line delay processing are simultaneously performed in the video signal processing. The arithmetic processing for ACC needs to sample the burst data with a clock of 4 fsc and measure the amplitude thereof, and the line delay processing (necessary for Y / C separation and comb filtering processing) uses 910 fh for the video data. Need to be delayed by the clock.

In the state (c), the process unit P
Communication control unit CC11 and communication register RE1 in U1
1 operates by the data rate clock DCK1, and data can be sent to the bus selected by the switch SW for the data rate clock DCK1. Further, for example, the communication control unit CC1 in the process unit PU1
2. Communication register RE12 is data rate clock DC
It operates by K2 and can introduce data from the bus selected by the switch SW for the data rate clock DCK2.

Correspondingly, the process unit PU2
The communication control unit CC21 and the communication register RE21 in the above operate by the data rate clock DCK2, and data can be sent to the bus selected by the switch SW for the data rate clock DCK2. Further, for example, the communication control unit CC22 in the process unit PU2,
Communication register RE22 sets data rate clock DCK1
It is possible to introduce the data from the bus selected by the switch SW for the data rate clock DCK1.

Such a process is used, for example, when a data rate conversion process is performed. That is, this is the case where the process unit PU2 receives the data of the data rate clock DCK1 from the process unit PU1, converts the data of the data rate clock DCK1 into the data of the data rate clock DCK2, sends the data, and fetches the data into the process unit PU1 again.

FIG. 2 shows a part of the inside of the first process unit PU1 of FIG. 1 in more detail. 1 are given the same reference numerals. Communication register RE
11 has an output register 111 and an input register 112. The communication control unit CC11 is reset by the selector 211 that selectively introduces one of the data rate clocks DCK1 and DCK2, the selector 212 that selectively introduces one of the communication clocks CCK1 and CCK2, and the data rate clock from the selector 211. Selector 21
Counter 213 that counts the communication clock from the counter 2, and comparators 214 and 215 that compare the output value of the counter 213 and the set value set by the main processor CP11, respectively.
And The main processor CP11 includes a latch unit 011 for latching output data, a latch unit 012 for latching input data, latch units 013, 014 for latching the previous set value, and latching selector control data. It has a latch portion 015.

The switch SW has a selector 311 for determining the bus selection and transmission timing of the transmission data, a selector 312 for selecting the input data bus, a control bus line and a data bus line corresponding to each data rate clock. .

Data A output from the latch unit 011
Is output register 11 in synchronization with the data rate clock.
The output data B is latched at 1, and the output data B from the output register 111 is supplied to the selector 311. Selector 311
Outputs the data to the bus line at the timing of the coincidence pulse from the comparator 214, and the output bus line is determined by the selection data output from the latch unit 015 of the main processor CP11.

When data is taken in, the selector 31
2 takes in the data from the bus determined by the selection data output from the latch unit 015 of the main processor CP11 and supplies it to the input register 112. The input register 112 takes in the data at the timing of the coincidence pulse from the comparator 215 and outputs it as the data D in the latch unit 01.
Give to 2. The latch unit 012 takes in the data D as the data E in synchronization with the data rate clock.

FIGS. 3A and 3B show a timing chart and an equivalent circuit shown for explaining the operation of the above system. Now, the data rate clock DCK1
Data is sent to the bus line with the communication clock CCK1. The main processor CP11 has a latch unit 01.
The data rate clock and the communication clock fetched from the selectors 211 and 212 via 5 are determined. It is also possible to control the selectors 311 and 312 via the latch unit 015 to determine the bus line for carrying the transmission data, and also the bus line for taking in the data. Further, the main processor CP11 supplies the data A to the output register 111 via the latch unit 011. Furthermore, the main processor CP11 sets a data value for setting the transmission timing to the comparator 214 via the latch unit 013.

As a result, as shown in FIG. 3A, the data A (X1, X2, X3, ...) From the latch section 011 is generated.
Outputs the data rate clock DC to the output register 111.
When the data is latched in synchronization with the rising edge of K and then output to the data bus, the comparator 2 which determines the transmission timing
When the coincidence pulse from 14 is obtained, it is output as data C and put on the bus.

FIG. 3 (a) also shows the loading. When the data C is captured, the input register 112 latches the data C at the capture timing when the coincidence pulse is obtained from the comparator 215. Next, in synchronization with the data rate clock, the latch unit 012 latches the output of the register 112 and takes it in the main processor (data E).

Here, the output timing of the data can be designed by considering the comparison value given to the comparator 214, and it can be present on the data bus by setting the comparison value given to the comparator 215. The selection of data slots for various data can be set arbitrarily. In this case, it is possible to select a clock that matches the data rate clock of the data to be handled and the communication clock.

Since it operates as described above, the result is shown in FIG.
As shown in (b), data is transmitted and received in synchronization with the data rate clock. In the diagram of FIG. 3A, the data is sent and taken in the same process unit, but the data is sent and taken in the same operation between different process units.

The present invention is not limited to the above embodiment. FIG. 4 shows another embodiment of the present invention. FIG.
The operation timing chart will be described.

In this embodiment, parts corresponding to the parts shown in FIG. 2 are designated by the same reference numerals as in FIG. In the embodiment of FIG. 2, the data on the data bus is parallel data,
In this state, it was sent and taken in. However, in the embodiment of FIG. 4, the data is transmitted as serial data on the data bus. That is, parallel data A (X0, X1, X2, X3, ...) Is output from the latch unit 011.
The parallel data A is supplied to the parallel / serial conversion unit of the data converter 120 of the communication register RE11,
Here, the serial data B is converted and output. The data transfer rate and timing of this data are determined by the communication clock CCK1 from the selector 211 of the communication control unit CC11.
Alternatively, CCK2, the latch units 221, 222, and the inverter 2
23 and the data rate clock DCK1 or DCK2 from the synchronizing circuit composed of the AND circuit 224. The serial data B is amplified by the buffer amplifier and supplied to the selector 321. The selector 321 outputs the serial data B to the data line instructed based on the selection instruction from the latch unit 015.

The timing chart of FIG. 5 also describes the operation when data is taken in. The data line in which the desired data is transmitted is the main processor C.
The selector 322 selects based on the control of P11, and the serial data of the data line is introduced into the serial / parallel conversion unit of the data converter 120. Here, using the corresponding communication clock, the serial data becomes parallel data D and is introduced into the latch unit 012. The latch unit 012 latches and takes in data using the corresponding data rate clock.

[0034]

As described above, according to the present invention,
Data having different rates can be easily communicated between the processors.

[Brief description of drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a part of the apparatus of FIG. 1 taken out.

3 is a timing chart and an equivalent circuit shown for explaining the operation of the circuit of FIG.

FIG. 4 is a diagram showing a second embodiment of the present invention.

5 is a timing chart shown for explaining the operation of the circuit of FIG.

FIG. 6 is a diagram showing a conventional parallel signal processing device.

[Explanation of symbols]

PU1 to PUn ... Process unit, CP11, CP2
1 ... Main processor, CC11, CC12, CC21, C
C22 ... communication control unit, RE11, RE12, RE21,
RE22 ... communication register, SW ... switch, 30 ... clock generating means, 011, 012, 013, 014, 01
5 ... Latch unit, 111 ... Output register, 112 ... Input register, 211, 212 ... Selector, 213 ... Counter,
214, 215 ... Comparator, 311, 312 ... Selector,
120 ... Data converter.

Claims (8)

[Claims] 1. A plurality of process units, a main processor provided in each process unit, a plurality of communication registers including output and input registers connected to the main processor, and corresponding to the plurality of communication registers, respectively. A parallel signal processing device comprising: a communication control unit provided in accordance with the above; and a switch unit that is controlled by the communication control unit to send the data output from the communication register to a predetermined data line, First communication control means for controlling communication in synchronization with a first transmission rate by combining the arbitrary communication register, communication control section, and switch means, and the arbitrary communication register,
A communication control unit and a switch unit are combined to construct a second communication control unit that controls communication in synchronization with a second transmission rate, and communication is performed at the first transmission rate by the first communication unit. And a means for causing the second communication means to perform communication at the second transmission rate. 2. The first communication means communicates via the first bus in synchronization with the first transmission rate, and the second communication means synchronizes with the second transmission rate. The parallel signal processing apparatus according to claim 1, wherein communication is performed via the second bus. 3. The first communication means and the second communication means are respectively constructed in the first and second process units, respectively, respectively, and are synchronized with each other at the same transmission rate to the first bus and the second bus, respectively. The parallel signal processing device according to claim 2, wherein the parallel signal processing device is in communication with third and fourth communication means connected to the second bus. 4. The first communication means and the second communication means are built in the same process unit, and each communicates with a communication means of a corresponding transmission rate built in another process unit. The parallel signal processing device according to claim 2, wherein 5. A plurality of process units, a main processor provided in each process unit, a plurality of communication registers including output and input registers connected to the main processor, and corresponding to the plurality of communication registers, respectively. A communication control means that is provided by means of which a plurality of types of data rate clocks and communication clocks can be selected, and the corresponding communication register operates in synchronization with any data rate clock; Sending selector means for sending the data output from the communication register to a corresponding data line according to the rate of the data, and fetch selector means for taking in data from an arbitrary data line and giving it to the corresponding communication register. A parallel signal processing device comprising: switch means including a. 6. The communication register converts the parallel data from the main processor into serial data and supplies the serial data to the corresponding sending selector means, and converts the serial data from the corresponding fetch selector into parallel data. 6. A conversion means provided to a processor is included.
The parallel signal processing device described. 7. The main processor, the communication control means, the communication register, and the switch means further correspond to a plurality of types of data rate clocks, respectively, and have a frequency higher than that of the data rate clocks. Clock generating means for generating a plurality of high types of communication clocks, a selector for selecting any of the data rate clocks and communication clocks set by the main processor, and initialization by the data rate clocks selected by the selector Similarly, a counter for counting the communication clock selected by the selector is compared with the output of the counter and the first set value set by the main processor, and when they match, a coincidence pulse is obtained. A first comparator and the main comparator when the coincidence pulse is supplied from the first comparator. Parallel signal processing apparatus according to claim 1 or 5, characterized by comprising an output means for outputting data from said communication means to the data line that is specified by the processor. 8. An input means selectively connected to a data line designated by the main processor, compares the output of the counter with a second set value set by the main processor, and when they match each other. A second comparator for obtaining a coincidence pulse in the input signal, and an input register for receiving the data selectively derived by the input means when the coincidence pulse is supplied from the second comparator. The parallel signal processing device according to claim 1, wherein the parallel signal processing device is a parallel signal processing device.