JPH0963290A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable read-out which is stable for a noise by increasing substantially a memory cell current by combining a memory cell of a NAND type mask ROM with a bipolar transistor. SOLUTION: This device is composed of a memory cell column consisting of plural memory cells (C1 , C2 , C3 , C4 ) and selecting transistors (S1 , S2 ) selecting a memory cell, one end of the selecting transistor S1 is connected to the base of a pnp bipolar transistor also an emitter is connected to a bit line BL1 . The other end of the memory cell is connected to a virtual ground line BG1 , and the virtual ground line is connected to a bias circuit B1 . A potential of the virtual ground line is controlled so that a potential of the virtual ground line connected to the selected memory cell column is lower than a potential of the bit line, also, potentials of the other virtual ground lines are same as the potential of the bit line.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a structure in which memory cells are connected in series such as a NAND type mask ROM.

[0002]

2. Description of the Related Art As a read-only memory, a memory having a NAND type structure is widely used because it is superior to other systems such as NOR type in terms of high integration. Generally, a NAND type mask ROM has a memory array structure in which a plurality of memory cell transistors are connected in series. In addition, since the cell size has been miniaturized to meet the demand for high-density integration, the current flowing through the memory cell column is very small, and is currently about 10 to 20 μA. For this reason, an extremely sensitive detection circuit is used so that a weak memory cell current can be detected. However, if a highly sensitive detection circuit is used, malfunction due to noise is likely to occur. To solve this problem, a method of increasing the channel width of the memory cell transistor to increase the memory cell current is considered, but cannot be adopted because the degree of integration is impaired. Also, a method of reducing the gate length of the memory cell transistor can be considered, but there are many problems in implementation in terms of the problem of fine processing precision and the reliability of the short channel transistor.

Against this background, recently, a method of amplifying the memory cell current by adding a bipolar transistor to the memory cell column has been proposed. FIG. 2 shows this conventional example. According to this, a bipolar transistor is provided between the node N and the bit line BL of two NAND type memory cell strings (for example, L ₁₀ and L ₁₁ ), and the current amplification of the bipolar transistor is added to the memory cell current. A current corresponding to the rate can be obtained on the bit line. Due to the increase in the memory cell current, it is possible to reduce the sensitivity of the detection circuit, prevent malfunctions due to noise, and also enable high-speed reading.

[0004]

However, on the other hand, the conventional method of adding bipolar transistors to the nodes (bit line contact portions) of each two memory cell columns requires as many bipolar transistors as the number of bit line contacts. Due to the large number of bipolar transistors used, fluctuations in the current amplification factor seriously affected product performance. Most of the recent mask ROMs have a storage capacity of 16 megabits, and in this case, the number of bipolar transistors required is 256 kilo. A current amplification factor of about 10 times is sufficient for a bipolar transistor, but if the number of bipolar transistors increases, the current amplification factor will increase to 100.
It appears from about double to about 2-3 times.

From the viewpoint of circuit design, it is desirable that the current amplification factor of the bipolar transistor is suppressed to at most 5 to 20 times even if it fluctuates, and for that purpose, it is necessary to reduce the number of bipolar transistors used. .

[0006]

A semiconductor memory device of the present invention includes a plurality of diffusion layer regions extending in one direction on a semiconductor substrate and partitioned, and a plurality of gate electrodes intersecting the diffusion layer regions. The diffusion layer region under the gate electrode is used as a channel region, and the first diffusion layer of the second conductivity type formed in the surface region of the semiconductor substrate on both sides of the gate electrode is used as a source / drain. A memory cell string formed by connecting a plurality of memory cell transistors in series, and a selection transistor connected in series with the memory cell string using the first diffusion layer of the second conductivity type as the source / drain like the memory cell transistor. A second conductive type second diffusion layer electrically connected to the other end of the select transistor as a base region, and a first conductive type third diffusion layer formed in a surface region of the base region. A bipolar transistor having the diffusion layer as an emitter region and the first conductivity type semiconductor substrate as a collector region, a bit line electrically connected to the emitter region of the bipolar transistor, and the other end of the memory cell column. And a virtual ground line electrically connected to the memory cell column, the potential of the virtual ground line connected to the predetermined memory cell column is lower than the potential of the bit line, and the potentials of the other virtual ground lines are It has a selection means for setting the same potential as the potential of the bit line.

[0007]

The present invention will be described with reference to FIG. Memory cell transistors C ₁ , C ₂ , C ₃ , C ₄ (generally 16
In many cases, a plurality of memory cells are connected in series) and a memory cell column including memory cell column selection transistors S ₁ and S ₂ is regularly arranged. The memory cell transistor is either a depletion type or an enhancement type depending on the data stored therein.

One end of the memory cell column selection transistor S ₁ is connected to the bit line B via a pnp bipolar transistor.
Is connected to L _1, the bit lines BL ₁ current detection circuit (S.
A. )It is connected to the.

The bit line contact portion (one end of the memory cell transistor C ₄ ) which is a node between the two memory cell columns L ₁₀ and L ₁₁ is connected to the virtual ground line BG ₁ .
The virtual ground lines BG _{1 to} BG ₃ are bias circuits B, respectively.
_{1 to} B ₃ are connected.

When the memory cell transistor C ₁ is read, BS ₁ connected to the gate electrode of the memory cell column selection transistor S ₁ is set to a high potential, BS ₂ connected to the gate electrode of S ₂ is set to a low potential, and the word The line W _{1 is set} to a low potential and the word lines W ₂ , W ₃ and W ₄ are set to a high potential.

Further, the bias circuit B ₁ is controlled so that the potential of the virtual ground line BG ₁ becomes low. At this time, it is necessary to control the potentials of the other virtual ground lines BG ₂ and BG ₃ to the same potential as that of the current detection circuit (SA).

Control of activation / deactivation of these word lines, BS ₁ and BS ₂ and bias circuit is all performed according to the result of decoding the input address by a decoder circuit (not shown).

In this embodiment, the memory cell transistor C
_{Since 1} is a depletion type, a cell current (I _C = 5 to 10 μA) flows in the memory cell column. Since this cell current is amplified by the pnp bipolar transistor connected to the bit line BL ₁ (current amplification factor: 10 times), a bit line current (I _BL ) of 50 to 100 μA flows through the bit line BL _1. become.

According to this embodiment, the number of bipolar transistors conventionally required for each bit line contact portion is
Since the bias circuit is provided and the current path exists only in the memory cell column corresponding to the address, it is possible to greatly reduce the current path.

[0015]

According to the present invention, since a substantially large cell current can be obtained, the sensitivity of the current detection circuit can be lowered, so that malfunction due to noise can be prevented.

Furthermore, since the number of pnp bipolar transistors can be greatly reduced, fluctuations in the current amplification factor of the bipolar transistors can be almost ignored.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an embodiment of the present invention and a sectional view of a semiconductor device.

FIG. 2 is a circuit diagram of a conventional example and a sectional view of a semiconductor device.

[Explanation of symbols]

C ₁ , C ₂ , C ₃ , C ₄ , C ₁₀ , C ₂₀ , C ₃₀ , C ₄₀
Memory cell transistors S ₁ , S ₂ , S ₁₀ , S ₂₀ Memory cell column selection transistors BL ₁ , BL ₂ , BL ₁₀ , BL ₂₀ , BL ₃₀ Bit lines BG ₁ , BG ₂ , BG ₃ Virtual ground lines B ₁ , B ₂ , B ₃ bias circuit

Claims (4)

[Claims] 1. A semiconductor substrate having a plurality of diffusion layer regions extending in one direction and partitioned and a plurality of gate electrodes intersecting the diffusion layer region, wherein the diffusion layer region below the gate electrode. A memory cell column in which a plurality of memory cell transistors each having a channel region as a channel region and having diffusion layers formed on the surface regions of the semiconductor substrate on both sides of the gate electrode as sources and drains are connected in series; A select transistor connected in series with the column, a diffusion layer electrically connected to the other end of the select transistor as a base region, and a diffusion layer formed in a surface region of the base region as an emitter region, and A bipolar transistor having a semiconductor substrate as a collector region; a bit line electrically connected to the emitter region of the bipolar transistor; The semiconductor memory device provided with the other end electrically connected to the virtual ground line of the cell columns. 2. The potential of the virtual ground line connected to the selected memory cell column is lower than the potential of the bit line, and the potentials of the other virtual ground lines are the same as the potential of the bit line. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a potential. 3. A plurality of memory cell columns in which a plurality of memory transistors are connected in series, a plurality of power source lines connected to one end of each of the plurality of memory cell columns, and a plurality of power source lines respectively connected to the plurality of power source lines. A plurality of bias circuits connecting the power supply line to the first or second power supply terminal in response to a control signal; a base commonly connected to the other ends of the plurality of memory cells and an emitter connected to the output line; And a bipolar transistor connected to the first power supply terminal. 4. A power supply line corresponding to one bias circuit according to an input address of the plurality of bias circuits is connected to the first power supply terminal, and a power supply line corresponding to another bias circuit is a second power supply line. The semiconductor memory device according to claim 3, wherein the semiconductor memory device is connected to a power supply terminal.