JPH09172020A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily connect bump electrodes on a semiconductor wafer before the wafer is diced into semiconductor chips by reducing the height of bump electrodes stepwise from the center to the periphery of the semiconductor wafer. SOLUTION: A semiconductor wafer 1 containing semiconductor chips 2 has bump electrodes 3 formed thereon in such a manner that the height of the bump electrodes 3 is reduced stepwise from the center to the periphery of the wafer. Specifically, the height of the bump electrodes 3 is adjusted so that the following equation will hold: 0.8R(R-x)/2r<=<=1.3R(R-x)/2r. This adjustment for optimization enables simple batch probing. In addition, the height of adjoining bump electrodes 3 is varied. Specifically, the bump electrodes 3 the diameters L1 23, Ln-1 , Ln and L2 24 of which are the same and the heights h1 , hn-1 , hn and h2 of which are different from one another are formed in the height ratio of 0.8<hn /hn-1 <1.2. This evades short-circuiting between adjoining bump electrodes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to improvement of a bump electrode formed on a bonding pad of a semiconductor chip to be flip-chip mounted on a circuit wiring board.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been highly integrated, and packaging technology is required to have high density. Wire bonding technology and TAB are used for high-density mounting technology of semiconductor devices.
Typical examples include technology. As the highest-density mounting technique, a flip-chip mounting technique used for high-density mounting of semiconductor devices such as computer equipment is known. This flip-chip mounting technique has become a widely known technique since the disclosure of US Pat. No. 3,401,126 and US Pat. No. 3,429,040.

FIG. 20 is a schematic diagram showing the structure of a general bump electrode. FIG. 21 is a schematic diagram showing a state where flip-chip mounting is performed using the bump electrodes shown in FIG. In the flip-chip mounting, as shown in FIG. 20, the bump electrode 3 having a protrusion shape is formed on the bonding pad 29 of the semiconductor chip 2, and as shown in FIG. This is a technique for electrically and mechanically interconnecting the bonding pad 29 and the connection terminal 27 of the circuit wiring board 25.

In the flip-chip mounting technology, since the coefficient of thermal expansion of a semiconductor chip and the coefficient of thermal expansion of a circuit wiring board are generally different from each other, stress strain occurs in the bump electrode portion. The stress strain of the bump electrode portion destroys the bump electrode mounted on the flip chip and reduces the reliability life thereof.

Reliability life is described by IBM J. Res. De
velop. , 13; 251 (1969), Nf = Cf ^1/3 γ _max ^-2 · exp (1428 / T
It is possible to improve the reliability life by reducing the maximum shear strain γ _max generated in the bump portion from the cycle life formula (C; constant, f; frequency, T _max ; maximum temperature) represented by _max ). Are known. In this reliability life formula, the maximum shear strain γ _max generated in the bump electrode is represented by the following formula.

Γ _max = {1 / (Dmin / 2) ^{2 / β} }
(V / πh ^{1 + β} ) ^{1 / β} · d · ΔT · Δα (D _min ; minimum bump diameter, β; material constant, V; solder volume, h; solder height, Δα; thermal expansion coefficient difference, ΔT ; Temperature difference, d; distance from the center of the chip to the center of the bump) In order to improve the reliability of flip-chip mounting, (1) the distance from the center point of the semiconductor chip to the center point of the bump electrode is reduced. (2) The difference between the coefficient of thermal expansion of the semiconductor chip and the coefficient of thermal expansion of the circuit wiring board is reduced.
(3) To improve heat dissipation so that the temperature difference does not increase. (4) Means such as making the bump electrode structure and the material strong against stress strain have been used. In particular, a method of increasing the height of the bump electrode connecting the circuit wiring board and the semiconductor chip is an effective method for reducing the maximum shear strain generated in the bump electrode, and many proposals have been made so far. .

This flip chip mounting is a method of mounting a bare chip on a circuit wiring board, and it is necessary to inspect a semiconductor chip before mounting. This semiconductor chip inspection is required to be inspected in a wafer state in consideration of throughput. JP-A-62-243335, JP-A-63-31129, and JP-A-3-125448.
The publication discloses a method of testing a semiconductor chip in a wafer state. Here, a method of performing a collective probing test on a semiconductor wafer to be inspected using a test head is proposed.

However, for example, Japanese Patent Laid-Open No. 1-1107
When the bump electrode is formed by using the electroplating method as described in Japanese Patent Laid-Open No. 51, the phenomenon that the bump electrode height becomes high in the peripheral portion of the wafer occurs. This is because when forming bump electrodes, the current density of the current supplied from the peripheral portion of the wafer increases only in the peripheral portion of the wafer.

For such a semiconductor wafer having a high distribution of bump electrodes in the peripheral area of the wafer and a low distribution of central area,
When inspecting using the above test head, it was necessary to apply pressure to the central portion of the back surface of the wafer. At this time, if the semiconductor wafer to be inspected is made of a brittle material such as GaAs, problems such as wafer cracking occur.

Further, a device is formed on the surface of the semiconductor wafer by Al wiring or the like to generate a compressive stress, and the device surface usually has a warped state in which the device surface is concave. For this reason, when the bump electrodes having a high height are formed in the peripheral portion of the semiconductor wafer, there is a problem that collective probing becomes extremely difficult even if pressure is applied to the back surface. A possible solution is to use a test head having a convex shape, but it has been extremely difficult to fabricate a test head that matches the warped state.

As described above, in the conventional flip-chip mounting method, stress strain caused by the difference in the coefficient of thermal expansion between the semiconductor chip and the circuit wiring board is generated in the bump electrode portion, and the bump electrode is destroyed, resulting in reliability. There was a very serious problem of lowering.

Therefore, many proposals have been made in the past so as to provide a structure in which stress is not concentrated on the bump electrodes.
In particular, the method of increasing the height of the bump electrode is an effective method for relaxing the stress strain, and many proposals have been made.

However, if the bump electrode height is increased, the bump electrode height varies widely, and it becomes difficult to make reliable connection with all the electrode pads of the circuit wiring board even if the solder is melted. There was a problem.

Therefore, when the bump electrode height is increased, it is necessary to make the bump electrode height uniform by using a method such as grinding in order to ensure the connection.

Further, in flip-chip mounting, the bump connection accuracy is improved by using the self-alignment effect of solder. For connection using self-alignment, the bump electrode diameter at the four corners of the semiconductor chip is made larger than the other bump electrode diameters, and the bump electrodes of the semiconductor chip and the electrodes of the circuit wiring board are made uniform by a certain size. A method of changing it has been proposed.

However, when the bump electrodes become extremely fine and the error between the electrode pitch of the circuit wiring board and the electrode pitch of the semiconductor chip greatly affects the connection accuracy,
There is a problem that flip chip mounting cannot be performed.

Further, in the flip chip mounting, in order to improve the mounting yield, it is required to inspect the semiconductor chip in a wafer state.

However, in a semiconductor wafer having bump electrodes formed thereon, the height of the bump electrodes around the wafer becomes higher than the height of the bump electrodes at the center of the wafer due to the influence of the current when the bump electrodes are formed by plating. Had a tendency. For this reason, there has been a problem that reliable inspection cannot be performed by batch probing using a test head, which has been proposed so far. This problem has been particularly remarkable when the wafer surface on which the bump electrodes are formed has a concave shape.

[0019]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems of the prior art. A first object of the present invention is to perform a connection inspection in the state of a semiconductor wafer before cutting semiconductor chips. An object of the present invention is to provide a semiconductor device which is easily connected and has excellent connection reliability.

A second object of the present invention is to prevent a short circuit between adjacent bumps in a semiconductor chip and to prevent the pressure at the time of assembly from being concentrated in one place and breaking the semiconductor chip. Thus, a semiconductor device with high connection reliability is provided.

[0021]

First, the present invention has a semiconductor wafer, a plurality of bonding pads provided on the semiconductor wafer, and bump electrodes formed on the bonding pads. There is provided a semiconductor device characterized in that the height of the electrode is gradually reduced from the central portion of the semiconductor wafer toward the outer peripheral portion.

At this time, preferably, where R is the outer radius of the semiconductor wafer, r is the radius of curvature of the semiconductor wafer, and h is the height of the bump electrode located at a distance x from the center of the semiconductor wafer, the bump electrode is The height of 0.8R (R
-X) /2r≦h≦1.3R (R−x) / 2r.

Secondly, the present invention is a semiconductor device comprising a semiconductor chip, a plurality of bonding pads provided on the semiconductor chip, and bump electrodes formed on the bonding pads, wherein the first bump When the height of the electrode is h ₁ , the height of the second bump electrode is h ₂ , the height of the n−1th bump electrode is h _n−1 , and the height of the nth bump electrode is h _n , the ratio of the height of the bump electrodes, 0.8 <h _n /
Provided is a semiconductor device characterized in that h _n-1 <1.2.

In the first and second inventions, the bump electrode is preferably made of a solder material containing at least lead element and tin element.

[0025]

According to the first aspect of the present invention, the height distribution of bump electrodes formed on a semiconductor wafer is gradually reduced from the central portion of the wafer to the outer peripheral portion. Such a height distribution is completely opposite to the height distribution of the bump electrodes of the conventional semiconductor wafer. For this reason, it has been impossible to perform collective probing because the bump electrode in the central portion of the wafer is small so far. However, when the semiconductor wafer according to the first invention is used, sufficient inspection can be performed using the conventional test head. .

Particularly, according to the first invention, preferably,
The bump electrode height h formed on the semiconductor wafer is 0.8R (R−x) with respect to the position x where the bump electrode is formed.
By adjusting /2r≦h≦1.3R(R−x)/2r and R ≠ x and performing optimization, batch probing can be easily performed.

Further, according to the present invention, since the bump electrode is made of solder, the bump height variation is absorbed by the plastic deformation of the solder, and the probing can be easily performed.

According to the second invention, the height of the adjacent bump electrodes are to have a variation in the range of _{0.8 <h n / h n-} 1 <1.2. Adjacent bump electrodes formed so as to have different heights have different volumes, so that a short circuit is unlikely to occur between the adjacent bump electrodes at the time of connection.

Further, within the range of distribution according to the present invention,
It is not necessary to form a bump electrode having a high height, which has been conventionally used in order to reduce the maximum shear strain generated in the bump electrode, and the problem of short circuit between adjacent bump electrodes does not occur.

Further, there has been a problem that when a bump electrode having a high height is partially present, the pressure is concentrated at one place and the semiconductor chip is broken when the assembly is performed. However, in the distribution according to the present invention, the pressure at the assembly is increased. Are almost evenly distributed on the semiconductor chip, so that highly reliable connection is possible.

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a perspective configuration diagram showing an embodiment of a semiconductor device using a semiconductor wafer according to the first invention. FIG. 2 is a sectional configuration diagram showing an embodiment of a semiconductor device using the semiconductor chip according to the second invention. 3 to 10 are process cross-sectional views showing an embodiment of a method of manufacturing a semiconductor device according to the present invention.
FIG. 3 is a diagram showing an electroplating apparatus for manufacturing a semiconductor device according to the present invention.

1 to 11, 1 is a semiconductor wafer, 2 is a semiconductor chip, 3 is a bump electrode, 4 is an outer radius R of the semiconductor wafer, 5 is a radius of curvature r of the semiconductor wafer,
6 is a position at a distance x from the center of the semiconductor wafer, 21 is the height of the first bump electrode, 22 is the height of the second bump electrode, and 23 is the first bump electrode.
The bump electrode radii L ₁ and 24 represent the second bump electrode radii L ₂ .

As shown in FIG. 1, in the semiconductor device according to the first aspect of the present invention, in a semiconductor wafer 1 having a semiconductor chip 2 having bump electrodes 3 formed on at least a plurality of bonding pads, the height of bump electrodes 3 is increased. Are formed so as to gradually decrease from the central portion of the wafer to the peripheral portion thereof, and the height of the bump electrode 3 is 0.8 R.
(R−x) /2r≦h≦1.3R (R−x) / 2r. The bump electrode 3 is preferably composed of solder containing at least lead and tin.

Further, as shown in FIG. 2, in the semiconductor device according to the second invention, in the semiconductor chip in which the bump electrodes 3 are formed on at least a plurality of bonding pads 28, the electrode diameters L ₁ 23, L _{n. -1} , L _n , and L ₂ 2
4 are the same and formed with a height _{h 1, h n-1,} h n, and the bump electrode 3 h ₂ are different 0.8 <height ratio _{h n / h n-1 <} 1.2 ing. Preferably, the formed bump electrode 3 is composed of solder.

First Embodiment The first embodiment will be described below.

The semiconductor device having the bump electrode according to the first embodiment is manufactured by the steps shown in FIGS.

First, as shown in FIG. 3, the semiconductor chip 1
A bonding pad 29 is formed on the bonding pad 29, and a passivation film 30 made of, for example, PSG (phosphorus-silica-glass) or SiN (silicon nitride) is formed except a part of the bonding pad 29. Furthermore, for example, a Cu / Ti film (Cu = 1 μm, T
i = 0.1 μm) is vapor-deposited on the entire surface. This Cu / Ti
The film is used as a cathode metal when the bumps are electroplated.

This Cu / Ti film finally becomes the barrier metal 29 of the bump electrode by forming the bump electrode 3 by electroplating and then etching a necessary portion.

Then, as shown in FIG. 4, a thick film resist AZ4903 (manufactured by Hoechst Japan) is spin-coated to form a resist film 51 having a film thickness of 100 μm.
By exposure / development, a 100 μm opening having a dimension of 5 μm on each side is formed on the Cu / Ti film as compared with the bonding pad 29 having a 90 μm square opening dimension.
The exposure is performed by irradiating a sufficient amount of exposure energy even if the resist is thick, and the development is performed by an AZ400K developer (manufactured by Hoechst Japan). Plating resist film 5
The wall angle adjustment of No. 1 is, for example, 13th, IEMT Sy
mp. As described in pp208, 1992,
It is controlled by adjusting the exposure energy, the distance between the resist and the glass mask, and the concentration of the developing solution.

In this way, as shown in FIG. 5, a silicon wafer on which a resist film 51 is formed with a larger size than the portion corresponding to the bonding pad 29 is formed into a copper sulfate plating solution containing the following mixed solution. And Cu / Ti as a cathode and a phosphorus-containing (0.03-0.08 wt%) high-purity copper plate as an anode at a bath temperature of 25 ° C. and a current density of 1-5 (A / dm ² ) gently. While stirring, the copper layer 31 is electroplated to 35 μm. The copper 31 formed at this time does not necessarily need to be plated to a thickness of 35 μm, and the film thickness can be set arbitrarily as necessary. Therefore,
The copper layer 31 does not necessarily need to be thickly deposited on Cu / Ti, and may be Cu / Ti as it is. Also, Cu / T
When forming on i, copper does not necessarily have to be a plating method, and there is no problem in forming Cu having a predetermined film thickness by using a well-known technique such as EB vapor deposition method and sputtering method. Therefore, the shape of the copper in the finally manufactured bump electrode is not particularly limited.

Copper Sulfate Plating Solution Copper Sulfate Pentahydrate 2 ounces / gallon Sulfuric acid 30 ounces / gallon Hydrochloric acid 10 ppm Thioxanthate-s-propanesulfonic acid (or thioxanthatesulfonic acid) 20 ppm Polyethylene glycol (molecular weight: 400,000) ) 40 ppm Polyethylenimine (molecular weight: 600) 2 ppm reaction product with benzyl chloride or copper sulfate pentahydrate 30 oz / gallon Sulfuric acid 8 oz / gallon hydrochloric acid 30 ppm Dithiocarbamate-s-propanesulfonic acid 30 ppm Polypropylene glycol (molecular weight: 700) 10 ppm Reaction product of polyethyleneimine and allyl bromide or dimethylsulfate 0.3 ppm Then, the plating bath was changed to the sulfonic acid solder plating solution described below, and the same as in the case of electrolytic copper plating. To, Cu /
Electroplating is performed using Ti as a cathode and a high-purity eutectic solder plate having a composition corresponding to the plating solution as an anode. The current density was 1 to 4 (A / dm ² ), and the solder composition (Pb / Sn) was almost equal to the eutectic composition or slightly shifted to the Pb side or Sn side while gently stirring at a bath temperature of 25 ° C. A solder alloy 32 having a composition is deposited on copper to a thickness of 65 μm to obtain a structure as shown in FIG.

Sulfonic acid solder plating solution Tin ion (Sn ²⁺ ) 12% by volume Lead ion (Pb ²⁺ ) 30% by volume Aliphatic sulfonic acid 41% by volume Nonionic surfactant 5% by volume Cationic surfactant 5% by volume % Isopropyl alcohol 7% by volume As an electroplating apparatus used at this time, for example, FIG.
The jet type electroplating device shown in FIG.
This type of electroplating equipment is based on ECC 1990 Pr
As described in Aceeding pp460-pp469, the current supply is performed by bringing the cathode electrode into contact with the periphery of the wafer.

As shown in FIG. 11, this electroplating apparatus has a plating apparatus main body 6 having a cup-type plating treatment tank.
1, an anode electrode 67 and a cathode electrode 66 provided on the upper part of the peripheral wall of the plating treatment tank, and a plurality of openings 7 provided at the lower part of the plating treatment tank and connected to the anode electrode 67.
And an anode plate 62 with zero.

Anode pin 63 connected to the driving power supply,
A predetermined voltage is applied by bringing the cathode pin 65 into contact with the anode electrode 67 and the cathode electrode 66, respectively. The substrate 1 to be plated is arranged above the plating tank so as to face the anode plate 62 and is connected to the cathode electrode.

The plating solution is introduced through the inlet 6 at the bottom of the plating treatment tank.
8 is introduced into the anode plate, flows through the openings 70 in the anode plate toward the substrate connected to the cathode electrode, and a plating process is performed on the substrate to deposit a plating metal. afterwards,
The waste liquid after the plating process is discharged from a discharge port (not shown) provided on the upper part of the peripheral wall of the plating process tank. In this plating process, on the substrate 1 on which a desired plated metal is deposited, the plating solution flows so as to spread radially from the central portion of the substrate to the peripheral portion.

In this apparatus, the current density has a high distribution around the wafer, and in general, the deposited plating film thickness tends to be thicker around the wafer. However, the present invention succeeded in achieving a thick plating film thickness distribution in the central portion of the wafer by optimizing the jet flow rate of the plating liquid circulating in the plating apparatus and contacting the wafer. This is because the ion diffusion layer thickness is controlled by the jet flow rate in consideration of the fact that the distribution of the ion diffusion layer thickness on the surface of the wafer that becomes the cathode electrode changes depending on the jet flow rate of the plating solution. The conventional jet flow rate was set to 5 to 8 L / min, but in the present invention, for example, 9 to 20 L / min.
Minutes, preferably 14 L / min. If the jet flow rate is slower than 9 L / min, the plating solution is not sufficiently stirred in the vicinity of the plating electrode, and the plating film thickness around the wafer tends to be thick. If it is faster than 20 L / min, The agitation tends to be too strong to allow sufficient storage.

FIG. 12 shows a film thickness distribution when solder is deposited on a semiconductor wafer using the electroplating apparatus shown in FIG. In the figure, a graph 101 indicates a jet flow rate of 6 L /
Min, graph 102, jet flow rate 20 L / min, graph 1
03 shows the case where the jet flow rate is 14 L / min, and graph 104 shows the case where the jet flow rate is 10 L / min. In the conventional method, as shown in the graph 101, the film thickness in the central portion of the wafer has a small distribution, whereas in the method according to the present invention, as shown in the graphs 102, 103, and 104, The film thickness of the part has a thick distribution. By the above method, the solder alloy which is the bump electrode material is continuously plated on the bonding pad.

Then, as shown in FIG. 7, the resist AZ4903 51 on the wafer 1 is immersed in acetone to remove it. At this time, it is also possible to use AZ remover (made by Hoechst Japan) as a stripping solution.

Then, on the wafer 1 on which the Cu / Ti layer 28 and the copper layer bump electrode are formed, for example, the viscosity adjustment of AZ4903 (manufactured by Hoechst Japan) or OFPR-800 (manufactured by Tokyo Ohka Co., Ltd.) which is the same as the plating resist is performed. The applied solution is spin-coated to form a resist film 52.

Next, a glass mask having an opening pattern having an opening dimension of 2 μm larger than the bump electrode 100 μm and a side of 104 μm is aligned with a required position and then exposed. The exposure is performed with an exposure energy of 2000 mJ, and the wafer is baked on a hot plate at 150 ° C. after the exposure. Next, the baked wafer is immersed in a developing solution and developed. By performing the above steps, the resist film 51 as shown in FIG. 8 is selectively formed on the bump electrode having the solder 32. Then, for example, ammonium persulfate,
With a mixed solution composed of sulfuric acid and ethanol, or a mixed solution composed of citric acid, hydrogen peroxide solution, and a surfactant, after removing the necessary portion of copper by etching, ammonia,
A necessary portion of titanium is removed by etching with a mixed solution composed of ethylenediaminetetraacetic acid and hydrogen peroxide solution, and the finally coated etching resist is dissolved and removed with acetone to obtain a semiconductor wafer as shown in FIG. To get

The semiconductor wafer thus obtained has a structure as shown in FIG. 10 by reflowing.

By performing the above steps, the semiconductor wafer shown in FIG. 1 and the semiconductor chip shown in FIG. 2 are formed.

[0053] The semiconductor wafer shown in FIG. 1, the bump electrode height ratio distribution h _n when the maximum height of the bump electrodes to the distance from its center and h _n, the minimum height and h _n-1
A graph showing / h _n-1 is shown in FIG. From Figure 13,
The bump electrode height ratio is h _n / h _n-1 =
It can be seen that the distribution is within a certain range that does not become 1.
This is because the cathode diffusion layer thickness is controlled by the jet flow rate, so that the diffusion layer concentration distribution on the semiconductor wafer is not the same for the semiconductor chip size.

Next, the semiconductor chip to be flip-chip mounted is inspected in a semiconductor wafer state. FIG. 14 is a diagram showing a flip-chip mounting state of the semiconductor device of the present invention. The inspection at this time can be performed in the state as shown in FIG. 14 by using the method described in Japanese Patent Publication No. 6-80708, for example.

The inspected semiconductor wafer is divided into semiconductor chips to form a semiconductor device having a bump height in a predetermined range as shown in FIG.

Second Embodiment Next, a second embodiment will be described.

The semiconductor device according to the second embodiment is the same as the semiconductor device according to the first embodiment except that each of the above-mentioned copper plating and sulfonic acid solder plating solutions uses a solution having the following composition.
It can be obtained in the same manner as in the above embodiment.

Solder Plating Solution Copper Sulfate Pentahydrate 30 oz / gallon Sulfuric Acid 8 oz / gallon Hydrochloric Acid 15 ppm Dithiocarbamate-s-Propanesulfonic Acid 45 ppm Polypropylene Glycol (Molecular Weight: 700) 15 ppm Polyethyleneimine and Allyl Bromide or Dimethyl Sulfate Reaction product 0.45ppm Sulfonic acid solder plating solution Tin ion (Sn ²⁺ ) 12% by volume Lead ion (Pb ²⁺ ) 30% by volume Aliphatic sulfonic acid 61.5% by volume Cationic surfactant 7.5 volume % Isopropyl alcohol 10.5% by volume In this way, a semiconductor wafer as shown in FIG. 1 is obtained. This semiconductor wafer is inspected in the same manner as in the first embodiment and cut into semiconductor chips to obtain semiconductor chips as shown in FIG.

The semiconductor chips according to the first and second embodiments can be mounted on a circuit wiring board formed by a normal technique.

Although the substrate material and structure of the circuit wiring board used are not particularly limited, here, the printed circuit board SLC of the type in which the insulating layer and the conductor layer are built up on the glass epoxy substrate is used. (Surface L
A process for mounting a semiconductor chip according to the present invention on a circuit wiring board will be described by taking an atomic circuit board as an example.

In this circuit wiring board, an opening of, for example, 110 μmφ is provided in the connection terminal corresponding to the bump electrode of the semiconductor chip, and Cu is exposed. A portion other than the terminal portion of the substrate is covered with solder resist. First, using a flip chip bonder that has a half mirror that is a well-known technique for alignment, the semiconductor chip and this circuit wiring board are aligned, and the bump electrodes and the connection terminals of the circuit wiring board are electrically connected, Make mechanical contact. At this time, the circuit wiring board is held on a stage having a heating mechanism and preheated to 200 ° C., which is higher than the melting point of Pb / Sn = 40/60, in a nitrogen atmosphere.

Next, while the semiconductor chip and the circuit wiring board are in contact with each other, the collet holding the semiconductor chip is placed in a nitrogen atmosphere at the same temperature as that of the stage on which the board is mounted.
By heating to 00 ° C. and melting the solder formed on the bumps, the semiconductor chip and the electrodes of the circuit wiring board are separated from each other.
Temporarily connect electrically and mechanically.

Finally, the circuit wiring board on which the semiconductor chip is mounted is passed through a reflow furnace heated to 250 ° C. having a nitrogen atmosphere to realize electrical and mechanical connection.

At this time, the self-alignment effect is generated due to the surface tension of the solder, a slight positional deviation generated at the time of mounting is corrected, and bonding can be performed at an accurate position.

If necessary, it is possible to seal resin, which is a known technique, in the gap formed by the flip-chip mounted semiconductor device and the circuit wiring board. FIG. 15 is a diagram showing a state in which a sealing resin is applied between the semiconductor device and the circuit wiring board.

The semiconductor device shown above was evaluated and the following results were obtained.

In FIG. 16, when bump electrodes were formed on a semiconductor wafer having the solder film thickness distribution shown in FIG. 1 and probed all together, the distance from the center of the bump electrodes and the probing were possible. It shows the relationship with the bump electrode height. The measurement was performed on 50 semiconductor wafers having 5 types of radii. Each parameter was generalized from the measurement result, and the radius of the semiconductor wafer was R, the radius of curvature of the semiconductor wafer was r, and the bump electrode height at a position x from the bump center was h.

As is apparent from the figure, the bump electrodes that were probable have a distribution that gradually decreases from the center of the semiconductor chip toward the outer periphery, and h = R (R-
x) / 2r centered on the line 0.8R (R
It has been found that it has a range of −x) /2r≦h≦1.3R (R−x) / 2r. Therefore, if a semiconductor wafer having a bump electrode height distribution is used, collective probing is possible.

When the state after probing was evaluated, the bump electrodes with high height were deformed by the plastic deformation of the solder. Furthermore, it was also found that bump electrodes having a height outside the scope of the present invention cannot be probed even if plastic deformation occurs.

FIG. 17 is a diagram showing a state in which a semiconductor device using a semiconductor chip according to the present invention is flip-chip mounted on a circuit wiring board. Since all the bump electrodes do not have the same height, the connected bump shapes and sizes are not the same as shown in FIG.
The bump electrode shapes after this connection are different from each other, and as a result of obtaining the distribution range in which a short circuit does not occur between adjacent bumps,
0.8 <to have a range of _{h n / h n-1 <} 1.2 is has been found.

FIG. 18 is a graph showing the connection ratio and the height ratio distribution h _n / h _n-1 when the semiconductor device according to the present invention is flip-chip mounted on a circuit wiring board. The bump electrode height is used as a parameter. As is clear from FIG.
0.8 excluding the case of _{h n / h n-1 =} 1 <h n / h n-1
<1 and _{1 <h n / h n-} 1 < range of 1.2 connection of 10
It turned out to be 0%.

This is because when h _n / h _n-1 = 1 and when the bump shape is drum-shaped, the bump shapes tend to be the same and therefore a short circuit tends to occur between adjacent bumps. is there.

[0073] In _{addition, 0.8 <h n / h n} -1 <1,1 <h
_{When n 1} / h _n-1 <1.2, the height ratio distribution is so large that electrodes that cannot be bump-connected tend to appear.

Further, apart from this experiment, a semiconductor chip in which the electrode pitch of the semiconductor chip and the electrode pitch of the circuit wiring board differ by ± 5% is flip-chip mounted on the circuit wiring board, and the same connection as in FIG. 18 is made. The relationship between the ratio and the bump height ratio distribution was obtained. As a result, it has been found that the semiconductor chip having the range of the height ratio distribution of the present invention shows the same result as the result shown in FIG. 17, and 100% connection is possible. This is because the bump electrode having a large volume and the bump electrode having a small volume have different connection shapes as shown in FIG.

FIG. 19 shows 256 bump electrodes of Pb / Sn = 40/60 on a semiconductor chip of 10 mm × 10 mm.
It is a graph which shows the result of having evaluated the reliability of the sample formed in 100 μm in diameter and flip-chip mounted on the SLC substrate. The case where the connection was opened at even one of the 256 pins was regarded as defective, and the vertical axis represents the cumulative failure rate and the horizontal axis represents the temperature cycle. The number of samples is 1000, and the temperature cycle conditions are (-55 ° C (30 minutes) to 25 ° C (5
Min) to 125 ° C (30 minutes) to 25 ° C (5 minutes)).

As is apparent from FIG. 19, the semiconductor device having the bump electrodes according to the present invention is not inferior to the conventional semiconductor device having the bump electrodes and exhibits high reliability. I understand. From these results, it was confirmed that the semiconductor device using the present invention has sufficient reliability. It was also confirmed that the reliability of the semiconductor device according to the present invention was remarkably improved when the semiconductor device was resin-sealed.

The present invention is not limited to the above-mentioned embodiment, but can be variously modified without departing from the gist of the present invention. For example, barrier metal is Au, W, A
g, Al, Cr, Ti may be used, and the bump electrode material to be formed may be, for example, a mixture of Sb, In, Ga, Ge and the like, and the effect thereof is not changed at all.

[0078]

According to the first aspect of the present invention, the height distribution of bump electrodes formed on a semiconductor wafer is gradually reduced from the central portion of the wafer to the outer peripheral portion thereof, which facilitates batch probing. It is possible. This enables connection inspection using a conventional test head.

[0079] According to the second invention, since the bump electrodes height, and with _{0.8 <h n / h n-} 1 <1.2,
A short circuit between adjacent bumps can be prevented. This is because the bump electrodes having a large volume and the bumps having a small volume have different connection shapes.

Further, within the distribution range according to the present invention, the pressure during assembly is evenly distributed on the semiconductor chip, so that the problem that the pressure is concentrated at one place and the semiconductor chip is broken can be solved. A highly reliable semiconductor device can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic perspective view showing an embodiment of a first invention.

FIG. 2 is a schematic sectional view showing an embodiment of a second invention.

FIG. 3 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 7 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 9 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 10 is a process sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 11 is a diagram showing an electroplating apparatus for manufacturing a semiconductor device according to the present invention.

FIG. 12 is a graph showing a film thickness distribution of solder deposited on a semiconductor wafer.

FIG. 13 is a graph showing the relationship between the distance from the center of the semiconductor wafer and the ratio of the maximum and minimum heights of bump electrodes.

FIG. 14 is a diagram showing a flip-chip mounting state of a semiconductor device of the present invention.

FIG. 15 is a diagram showing a state in which a sealing resin is applied between a semiconductor device and a circuit wiring board.

FIG. 16 is a diagram showing the relationship between the distance from the center of the bump electrode and the bump electrode height at which probing was possible. Mounting structure using the semiconductor device according to the present invention

FIG. 17 is a view showing a state in which a semiconductor device using a semiconductor chip according to the present invention is flip-chip mounted on a circuit wiring board.

FIG. 18 is a graph showing the relationship between the connection ratio and the height ratio distribution h _n / h _{n- 1} in the case of flip-chip mounting.

FIG. 19 is a graph showing reliability evaluation when flip-chip mounting is performed.

FIG. 20 is a diagram for explaining a conventional technique.

FIG. 21 is a diagram for explaining a conventional technique.

[Explanation of symbols]

1 semiconductor wafer 2 semiconductor chip 3 bump electrode 4 radius of semiconductor wafer R 5 radius of curvature of semiconductor wafer r 6 distance from center of semiconductor wafer x 21 first bump electrode height h ₁ 22 second bump electrode height h ₂ 23 1st bump electrode radius L ₁ 24 2nd bump electrode radius L ₂ 25 Circuit wiring board 26 Solder resist 27 Connection terminal 28 Barrier metal 29 Bonding pad 30 Passivation film 31 Copper metal 32 Solder 51 Plating resist 52 Etching resist 53 Sealing resin

Claims (3)

[Claims] 1. A semiconductor wafer, a plurality of bonding pads provided on the semiconductor wafer, and bump electrodes formed on the bonding pads, wherein the height of the bump electrodes is from a central portion of the semiconductor wafer. A semiconductor device characterized by being gradually reduced in size with respect to the outer peripheral direction. 2. The height of the bump electrode is a height of the bump electrode arranged at a distance x from the center of the semiconductor wafer, where R is the outer radius of the semiconductor wafer, r is the radius of curvature of the semiconductor wafer. When it is set to h, it is 0.8R (Rx) / 2r <= h <1.3R (Rx) /
The semiconductor device according to claim 1, wherein the expression represented by 2r R ≠ x is satisfied. 3. A semiconductor device including a semiconductor chip, a plurality of bonding pads provided on the semiconductor chip, and bump electrodes formed on the bonding pads, wherein the height of the first bump electrode is h. ₁ , where the height of the second bump electrode is h ₂ , the height of the _n−1 th bump electrode is h _n−1 , and the height of the n th bump electrode is h _n , the height of the bump electrode is _{ratio, 0.8 <h n / h n} -1 <1.2
The semiconductor device is characterized by being within the range.