JP2009135345A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has improved reliability after mounting a substrate thereon without requiring specific structure. <P>SOLUTION: The semiconductor device 1 includes: a substrate 2 having an electrode 3 formed at least on one surface; a wiring layer 5 arranged on one surface of the substrate 2; and a solder bump 9 electrically connected to the wiring layer 5. A pad 6 is arranged on a portion of the substrate 2 on which the solder bump 9 is arranged, and the pad 6 includes a metallic ring part 7 electrically connected to the wiring layer 5 and at least one and more metallic projection parts 8 arranged separately from each other in the inside of the ring part 7. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device such as a wafer level CSP (Chip Size / Scale Package) that does not use a wiring board (interposer), and a manufacturing method thereof.

  Conventionally, in a semiconductor package, for example, a so-called dual inline package or quad flat package in which a silicon chip is sealed with a resin, metal is applied to the side surface and the peripheral portion of the resin package. Peripheral terminal arrangement type with leads arranged is the mainstream.

  In contrast, in a CSP (chip scale package), particularly a semiconductor package called “wafer level CSP” (hereinafter sometimes referred to as WLCSP), an insulating resin layer, a wiring layer, a sealing layer, and the like are formed on the wafer. Further, after forming solder bumps, a plurality of chips are obtained by dicing.

In WLCSP, since the chip becomes a semiconductor chip packaged in the same size, the occupied area can be reduced and high-density mounting is possible. The WLCSP is mounted on an external circuit board using solder bumps formed on a semiconductor chip.
Generally, since the thermal expansion coefficients of the semiconductor package and the printed circuit board are different, the stress based on the difference of the thermal expansion coefficient concentrates on the terminals of the semiconductor package. This stress is a problem because cracks are generated in the solder bumps, extend, and break.

On the other hand, a structure has been proposed in which a conductive columnar member called a “post” is provided and a terminal portion is formed on an end surface of the columnar member (see, for example, Patent Document 1). At this time, in a CSP having a columnar resin post, the stress is easily dispersed by forming the post high (see, for example, Patent Document 2).
However, if a structure for stress relaxation, such as the resin post described above, is separately provided, the material and man-hours increase and the cost increases.
JP 2004-207368 A Republication 00/077784

The present invention has been devised in view of such conventional circumstances, and has as its first object to provide a semiconductor device that does not require a special structure and has improved reliability after mounting on a substrate. .
The second aspect of the present invention is to provide a method for manufacturing a semiconductor device, which does not require a special structure and can manufacture a semiconductor device with improved reliability after mounting on a substrate in a simple process. Objective.

According to a first aspect of the present invention, there is provided a semiconductor device comprising: a substrate provided with an electrode on at least one surface; a wiring layer disposed on one surface of the substrate; and a solder bump electrically connected to the wiring layer. A pad provided on a portion of the substrate where the solder bump is disposed, the pad being made of a metal ring portion electrically connected to the wiring layer; and It is characterized by having at least one or more metal protrusions spaced apart from the inside of the ring portion.
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the ring portion and the protruding portion are made of the same metal.
According to a third aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a substrate provided with an electrode on at least one surface; a wiring layer disposed on one surface of the substrate; and a solder bump electrically connected to the wiring layer. A pad is disposed on a portion of the substrate on which the solder bump is disposed, and the pad is made of a metal ring portion electrically connected to the wiring layer, and the ring portion In the method of manufacturing a semiconductor device having at least one or more metal protrusions spaced apart on the inner side, the ring part and the protrusion part are formed simultaneously.

  In the present invention, a metal ring portion electrically connected to the wiring layer at a portion where the solder bumps are disposed on the substrate, and at least one or more spaced apart from the inside of the ring portion Since the pad having the metal protrusion is arranged, even if a crack occurs in the solder bump, the extension of the crack can be suppressed by the protrusion. As a result, a semiconductor device that does not require a special structure and has improved reliability after mounting on the substrate can be provided.

  Further, in the present invention, a metal ring portion electrically connected to the wiring layer and at least one or more spaced apart on the inner side of the ring portion at a portion where the solder bumps are disposed on the substrate The metal protrusions are simultaneously formed. Thereby, even if a crack occurs in the solder bump, the extension of the crack can be suppressed by the protrusion. As a result, it is possible to provide a method for manufacturing a semiconductor device that does not require a special structure and can manufacture a semiconductor device with improved reliability after mounting on a substrate in a simple process.

  Hereinafter, an embodiment of a semiconductor device according to the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing an example of a semiconductor device of the present invention. FIG. 2 is a plan view showing a wiring layer and a pad formed on the insulating resin layer in the semiconductor device shown in FIG.
The semiconductor device 1 includes a semiconductor substrate 2 having an electrode 3 disposed on one surface, an insulating resin layer 4 having an opening 4a disposed on one surface of the semiconductor substrate 2 and exposing the electrode 3, and an insulating resin layer 4 A wiring layer 5 (conductive part) electrically connected to the electrode 3 and a solder bump 9 electrically connected to the wiring layer 5;

In particular, in the semiconductor device 1 of the present invention, as shown in FIG. 2, a pad 6 is disposed on a portion of the substrate where the solder bump 9 is disposed, and the pad 6 is electrically connected to the wiring layer 5. And a metal ring portion 7 connected to the ring portion 7 and at least one metal protrusion portion 8 spaced apart from the inside of the ring portion 7.
In order to solve the conventional problems, in the present invention, the shape of the pad arranged at the portion where the solder bump is arranged on the substrate is changed. Specifically, in contrast to the conventional circular shape, in the present invention, the pad 6 is electrically connected to the wiring layer 5 and the metal ring portion 7 is separated from the inside of the ring portion 7. It was set as the form which has the at least 1 or more metal protrusion 8 arranged. Thereby, even if a crack occurs in the solder bump 9, the extension of the crack can be suppressed by the protrusion 8. As a result, it is possible to provide a semiconductor device that does not require a special structure and has improved reliability after mounting on the substrate.

  The semiconductor substrate 2 may be a semiconductor wafer such as a silicon wafer, or may be a semiconductor chip obtained by cutting (dicing) the semiconductor wafer into chip dimensions. When the semiconductor substrate 2 is a semiconductor chip, first, a plurality of sets of various semiconductor elements, ICs, induction elements, etc. are formed on a semiconductor wafer, and then a plurality of semiconductor chips are obtained by cutting into chip dimensions. Can do.

  The electrode 3 is an electrode that is electrically connected to an electronic component (not shown) formed on the semiconductor substrate 2. The electrode 3 is made of a conductive metal such as aluminum, copper, chromium, titanium, gold, or titanium-tungsten alloy.

The insulating resin layer 4 has an opening 4 a formed at a position aligned with the electrode 3. The insulating resin layer 4 is made of, for example, a polyimide resin, an epoxy resin, a silicone resin, polybenzoxazole (PBO), a liquid crystal polymer, or the like, and has a thickness of, for example, 1 to 30 μm.
The insulating resin layer 4 can be formed by, for example, a spin coating method, a printing method, a laminating method, or the like. The opening 4a can be formed by patterning using a photolithography technique, for example.

  The wiring layer 5 is a rewiring layer (underpass) that electrically connects the electrode 3 and the solder bump 9. One end of the wiring layer 5 penetrates the insulating resin layer 4 through the opening 4 a and is electrically connected to the electrode 3. The other end portion of the wiring layer 5 is electrically connected to the ring portion 7 of the pad 6.

  For the wiring layer 5, for example, copper, chromium, aluminum, titanium, gold, nickel, palladium, titanium-tungsten alloy or the like is preferably used, and the thickness is preferably 2 to 40 μm, more preferably 5 to 20 μm. Thereby, sufficient electrical conductivity is obtained. The wiring layer 5 can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

The pad 6 is disposed on a portion of the insulating resin layer 4 where the solder bumps 9 are disposed, and is made of a metal ring portion 7 electrically connected to the wiring layer 5, and an inner side of the ring portion 7. It has at least one or more metal protrusions 8 spaced apart.
The ring portion 7 has a role of electrically connecting the wiring layer 5 and the solder bump 9 of the package.

  The protrusion 8 has a role of suppressing cracks from occurring in the solder bumps 9 after mounting the semiconductor device 1, and also stopping the extension of cracks even if cracks occur. That is, the solder bump crack often occurs at the joint surface between the solder bump and the pad. Based on this premise, when the protrusion 8 is provided as in the present structure, the crack of the solder bump 9 extends along the protrusion 8. Compared to the conventional structure, this structure has a larger bonding area between the solder bumps 9 and the pads 6, so that it takes a longer time for the cracks to break.

  At the same time, in the conventional structure, the bonding surface between the pad and the solder bump is only the surface in the horizontal direction with respect to the substrate surface. Obtainable. That is, when a crack extends along the joint surface, the extension direction must change along the shape of the protrusion. This is clearly disadvantageous for the extension of cracks compared to conventional joint surfaces.

  Further, the protrusion 8 relieves stress acting on the solder bump 9. The reason for this is that, conventionally, the stress acting on the solder bump from the outside has been alleviated mainly by the deformation of the solder bump and the pad and wiring part. As in the structure, the pad 6 is deformed in the lateral direction as compared with the conventional structure by including the ring portion 7 and at least one protrusion 8 that is spaced apart from the inside of the ring portion 7. The structure is easy to do. That is, the structure is such that stress generated on the solder bump 9 can be easily relaxed. In this structure, some of the solder bumps 9 are in contact with the insulating resin layer 4, but both have low wettability and are not in close contact.

  For the reasons described above, in the semiconductor device 1 of the present invention, the presence of the protrusions 8 can alleviate the stress acting on the solder bumps 9 and suppress the generation and extension of cracks. As a result, the reliability after board mounting is improved.

  The shape and size of the protrusion 8 are not particularly limited, but are, for example, cylindrical and have a circle diameter of about 10 μm or more. Moreover, although it does not specifically limit also about the number of the projection parts 8, It shall be 5-30, for example. Also, two or more different shapes and sizes of the protrusions 8 may be mixed.

  The ring portion 7 and the protruding portion 8 are preferably made of the same metal, and for example, copper, chromium, aluminum, titanium, gold, titanium-tungsten alloy, or the like is used. Among these, it is preferable to use copper. The pad 6 (ring part 7 and protrusion part 8) can be formed by, for example, a plating method such as an electrolytic copper plating method, a sputtering method, a vapor deposition method, or a combination of two or more methods.

As the solder bump 9, Sn-Pb eutectic solder, Sn-Ag-Cu-based lead-free high-temperature solder, or the like can be used. In addition, a material containing at least one of Pb, ln, Sn, Au, Ag, Cu, Bi, and Zn can be used. The solder bump 9 can be formed by, for example, a solder ball mounting method, an electrolytic solder plating method, a solder paste printing method, a solder paste dispensing method, a solder vapor deposition method, or the like.
The solder bump 9 includes a convex structure, and this convex structure is newly formed on the pad 6.

Moreover, it is preferable that the semiconductor device 1 further includes a sealing layer 10 disposed on one surface side of the semiconductor substrate 2 so that the electrode 3 and the wiring layer 5 are embedded.
The sealing layer 10 is for protecting the electronic component, the electrode 3 and the wiring layer 5, and is made of, for example, polyimide resin, epoxy resin, silicon resin (silicone), polybenzoxazole (PBO), or the like. The thickness is about 5 to 50 μm.

  Such a sealing layer 10 can be formed, for example, by patterning a photosensitive resin such as a photosensitive polyimide resin by a photolithography technique. In addition, the formation method of the sealing layer 10 is not limited to this method.

  Next, a method for manufacturing such a semiconductor device 1 will be described.

  The method for manufacturing a semiconductor device according to the present invention includes a semiconductor substrate 2 having an electrode 3 on at least one surface, a wiring layer 5 disposed on one surface of the semiconductor substrate 2, and a solder electrically connected to the wiring layer 5. A pad 6 is provided on a portion of the semiconductor substrate 2 where the solder bump 9 is provided, and the pad 6 is a metal ring electrically connected to the wiring layer 5. In the manufacturing method of the semiconductor device 1 having the portion 7 and at least one metal protrusion 8 disposed inside the ring portion 7, the ring portion 7 and the protrusion 8 are formed simultaneously. It is characterized by that.

3 and 4 are cross-sectional views showing each step in the method for manufacturing a semiconductor device of the present invention.
In the present invention, the metal ring portion 7 electrically connected to the wiring layer 5 and the inside of the ring portion 7 are spaced apart from each other at the portion where the solder bumps 9 on the semiconductor substrate 2 are disposed. At least one or more metal protrusions 8 are formed at the same time. Thereby, even if a crack occurs in the solder bump 9, the extension of the crack can be suppressed by the protrusion 8. As a result, it is possible to provide a method for manufacturing a semiconductor device that does not require a special structure and can manufacture a semiconductor device with improved reliability after mounting on a substrate in a simple process.
Hereinafter, each step will be described in detail.

(1) First, as shown in FIG. 3 (a), a conductive metal film is formed on a semiconductor substrate 2 by vacuum deposition, sputtering, or the like, and the metal film is patterned to form a semiconductor substrate. Electrode 3 is formed at a predetermined position on 2.
Further, a passivation film (not shown) made of silicon nitride or the like is formed on the semiconductor substrate 2. An opening is formed at a position where the passivation film is aligned with the electrode 3, and the electrode 3 is exposed.

(2) Next, as shown in FIG. 3B, an insulating resin layer 4 is formed on one surface of the semiconductor substrate 2.
The insulating resin layer 4 has an opening 4 a formed at a position aligned with the electrode 3. The insulating resin layer 4 is made of, for example, polyimide resin, epoxy resin, silicone resin, polybenzoxazole (PBO), and the thickness thereof is, for example, 1 to 30 μm.
The insulating resin layer 4 can be formed by, for example, a spin coat method, a spray coat method, or the like. The opening 4a can be formed by patterning using a photolithography technique, for example.

The insulating resin layer 4 can be formed by using a laminating method or a printing method. In addition, a laser processing method or a plasma etching method can be used for patterning the resin.
In the case of a laminating method, a sheet-shaped resin patterned in advance can be pressure-bonded by laminating. Further, a method of directly forming a film and patterning a resin by a screen marking method is also possible. In these cases, the resin does not need to be photosensitive.

(3) A seed layer (not shown) is formed on the insulating resin layer 4 by sputtering, vapor deposition, coating, chemical vapor deposition, electroless plating, or the like.
The seed layer is composed of a lower layer serving as an adhesion layer for ensuring adhesion to the insulating resin layer 4 and an upper layer serving as a power feeding layer used for feeding when the wiring layer 5 and the pad 6 are formed. The seed layer prevents the wiring layer 5 and the pad 6 from entering and diffusing into the insulating resin layer 4. When the wiring layer 5 and the pad 6 penetrate and diffuse into the insulating resin layer 4, the adhesion is remarkably impaired.

For the adhesion layer, for example, a metal such as chromium, titanium, titanium-tungsten alloy, or nickel is used, and the thickness is preferably 10 to 3000 nm.
Copper, chromium, aluminum, titanium, titanium-tungsten alloy, gold, or the like is used for the power feeding layer, and the thickness is preferably 100 to 3000 nm.

  The thickness of the seed layer composed of the adhesion layer and the power feeding layer is preferably in the range of 110 to 6000 nm. In particular, if the thickness of the adhesion layer is less than 10 nm, the wiring layer 5 and the pad 6 may enter and diffuse into the insulating resin layer 4. Further, if the thickness of the adhesion layer exceeds 3000 nm, it is not preferable because it takes time to pattern the adhesion layer.

Further, a resist 20 having a resist opening is formed on the seed layer. At this time, the resist 20 in the portion where the pad 6 is formed is patterned so that the ring portion 7 and the protruding portion 8 are formed. After that, as shown in FIG. 3C, the wiring layer 5 and the pad 6 are formed by plating growth in the resist opening, and then the resist 20 is removed (see FIG. 3D). At this time, the thickness of the resist 20 is preferably thicker than that of the wiring layer 5 and the pad 6 made of a plated film to be grown. As a plating method, both electrolytic plating and electroless plating can be used.
Further, in order to improve the adhesion with the solder, at least one metal of Cu, Au, Ag, Ni, and Pd may be deposited by electrolysis or electroless plating.

Next, the region on the seed layer where plating is not formed is removed by etching to expose the insulating resin layer 4. Note that, in order to remove the seed layer in an unnecessary region, a dry etching method using plasma can be used in addition to an etching method using an etching solution.
The wiring layer 5 and the pad 6 thus formed preferably have a thickness of 5 to 20 μm.

(4) Next, as shown in FIG. 3E, the sealing layer 10 is formed on the insulating resin layer 4 and the wiring layer 5. The sealing layer 10 is made of a photosensitive resin such as a photosensitive polyimide resin, an epoxy resin, a silicon resin (silicone), or polybenzoxazole (PBO) using a spin coating method or a laminating method, and a photolithography technique. It can be formed by patterning.

  At that time, an opening 10 a that exposes at least the pad 6 is provided in the sealing layer 10. The diameter of the opening 10a can be adjusted by the opening diameter of the photomask used during exposure. The thickness of the sealing layer 10 is about 5 to 50 μm.

In addition, for the formation of the sealing layer 10, an electrodeposition method, a spray coating method, or a printing method can also be used. In addition, a laser processing method or a plasma etching method can be used for patterning the resin.
In the case of a laminating method, a sheet-shaped resin patterned in advance can be pressure-bonded by laminating. Further, a method of directly forming a film and patterning a resin by a screen marking method is also possible. In these cases, the resin does not need to be photosensitive.

(5) Next, as shown in FIG. 4, on the pad 6 exposed by the opening 10a of the sealing layer 10, a solder ball mounting method, an electrolytic solder plating method, a solder paste printing method, a solder paste dispensing method, The solder is transferred by a solder vapor deposition method or the like, and then the solder balls are melted by using a reflow furnace to form solder bumps 9 on the pads 6.
Thus, the semiconductor device 1 as shown in FIG. 1 is obtained.

  In the semiconductor device thus obtained, the metal ring portion 7 electrically connected to the wiring layer 5 and the inside of the ring portion 7 are separated from the portion where the solder bumps 9 are disposed on the substrate. Since the pads 6 having at least one or more metal projections 8 arranged in this manner are arranged, even if a crack occurs in the solder bump 9, the extension of the crack can be suppressed by the projection 8. . Thereby, a special structure is not required, and the reliability after mounting on the board is improved.

  The semiconductor device and the method for manufacturing the same according to the present invention have been described above. However, the present invention is not limited to this, and can be appropriately changed without departing from the spirit of the present invention.

  The present invention can be widely applied to semiconductor devices and manufacturing methods thereof.

Sectional drawing which shows an example of the semiconductor device manufactured by this invention. The top view which shows a wiring layer and a pad in the semiconductor device shown in FIG. Sectional drawing which shows an example of the manufacturing method of the semiconductor device which concerns on this invention in process order. Sectional drawing which shows the process following FIG. 3 in order.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor device, 2 Semiconductor substrate, 3 Electrode, 4 Insulating resin layer, 5 Wiring layer, 6 Pad, 7 Ring part, 8 Protrusion part, 9 Solder bump, 10 Sealing layer.

Claims (3)

A semiconductor device comprising: a substrate provided with an electrode on at least one surface; a wiring layer disposed on one surface of the substrate; and a solder bump electrically connected to the wiring layer,
Pads are disposed on the substrate on the substrate where the solder bumps are disposed, and the pads are separated from the metal ring part electrically connected to the wiring layer and the inside of the ring part. A semiconductor device having at least one or more metal protrusions arranged in a row.   The semiconductor device according to claim 1, wherein the ring portion and the protrusion are made of the same metal. A substrate provided with an electrode on at least one surface; a wiring layer disposed on one surface of the substrate; and a solder bump electrically connected to the wiring layer;
Pads are disposed on the substrate on the substrate where the solder bumps are disposed, and the pads are separated from the metal ring part electrically connected to the wiring layer and the inside of the ring part. In the method of manufacturing a semiconductor device having at least one or more metal protrusions arranged
A method of manufacturing a semiconductor device, wherein the ring portion and the protrusion are formed simultaneously.

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