JP3400263B2 - Semiconductor device, circuit wiring board, and semiconductor device mounting structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, a circuit wiring substrate and a structure with a semiconductor device mounted thereon, having bump electrode structure of high reliability. SOLUTION: A semiconductor device is provided with a semiconductor chip 1, bonding pads 2 formed on the semiconductor chip 1, and bump electrodes 8 on the bonding pads 2. The bump electrode 8 includes a first metal layer 4 formed on the bonding pads 2, a second metal layer 5 formed on the first metal layer 4, and a third metal layer 7 formed on the second metal layer 5 and connected to a circuit wiring substrate. Further, in proximity to the interface between the second metal layer 5 and the third metal layer 7, there is a concentrated region wherein at least one kind of element selected among a group of carbon, sulfur and oxygen is dispersed at a concentration higher than that of the internal region 6 of the second metal layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a circuit wiring board, and a semiconductor device mounting structure in which they are connected by a flip chip mounting technique.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been highly integrated,
The packaging technology is also required to have high density. Wire-bonding technology and TAB technology are typical of high-density mounting technology for semiconductor devices. In recent years, flip-chip mounting technology has been used as the highest-density mounting technology for semiconductor devices such as computer equipment. It has come to be widely used as a technique for mounting at high density. For example, flip-chip mounting technology as shown in FIG. 16 is disclosed in US Pat. No. 3,401,126 and US Pat. No. 34290.
Since it was disclosed in Japanese Patent Publication No. 40, etc., it has become widely known.

In the flip-chip mounting technology, the constituent material of the semiconductor device 1 and the constituent material of the circuit wiring board 21 on which the semiconductor device 1 is mounted are different, so that the displacement caused by the difference in the thermal expansion coefficient is different from that of the semiconductor device 1. It occurs on the circuit wiring board 21. The generated displacement of the semiconductor device 1 and the circuit wiring board 21 causes stress strain in the bump electrodes 8 connecting the semiconductor device 1 and the circuit wiring board 21. This stress strain destroys the bump electrode 8 to be flip-chip mounted and shortens the reliability life. Therefore, the stress strain has been relaxed so far by using the following method.

For example, the arrangement of the bump electrodes may be changed to reduce the distance from the center point of the semiconductor device to the center point of the bump electrode, or the coefficient of thermal expansion of the semiconductor device may be set in consideration of the material of the circuit wiring board. Similar to or match the coefficient,
As disclosed in Japanese Patent Laid-Open No. 58-23462, it is possible to reduce the temperature change of a semiconductor device mounted by flip chip,
As shown in Japanese Patent Application Laid-Open No. 61-194732, resin has been filled in the gap between the semiconductor device and the circuit wiring board.

Further, it has been proposed that the bump electrode itself has a structure that is strong against stress strain. In particular, Microelectronics Packaging Handbook (Micr
o Electronics Packaging Handbook), stress strain applied to bump electrodes of flip chip mounting structure decreases in inverse proportion to bump height, and connection reliability increases with bump height. Many proposals have been made to increase the bump height in order to improve the bump height.

As a method for increasing the bump height, as described in Japanese Patent Laid-Open No. 62-117346,
It is typical to use a bump electrode structure with a multi-stage structure in which a polyimide tape is interposed, but when a polyimide tape is used, bump formation is complicated, high technology is required, and the number of processes increases as the number of stages increases. Then, there is a problem that the cost for forming the electrode becomes high.

Therefore, it has been proposed to form a metal as a pillar material in the bump electrode and use this metal as a standoff to increase the bump height.

US Pat. No. 3,030,093 describes a structure in which copper balls are placed in the solder. According to this structure, the copper pole acts as a standoff, and the bump electrode height can be increased. In addition, JP-A-5
Japanese Patent No. 235102 discloses a structure in which mushroom-type copper pillars are arranged. According to this structure, by increasing the height of the mushroom type copper pillar material,
It is possible to make the bump electrode height higher than ever. Further, Japanese Patent Laid-Open No. 60-57957 proposes that a copper pole having a high aspect ratio is arranged in a bump metal to form a bump having a high height, and a bump shape is formed into a staggered shape to improve reliability. Has been done.

Further, in the proceedings pp5-pp13 of the 1992 Autumn Meeting of the Institute of Electronics, Information and Communication Engineers, as shown in FIG.
There has been proposed a method of improving the connection strength by making the shape of the copper pillar material 5 arranged inside the bump electrode 8 into an inverted trapezoid and curving the upper surface.

According to many of these proposed structures, since the bump electrode 8 can be increased in height, the reliability life can be improved to some extent. However, in the case where extremely high reliability is required such as high-end supercomputers in recent years, it is not always a sufficient method from the viewpoint of reliability.

This is because when the pillar material 5 made of copper is arranged in the bump electrode 8 in order to increase the height of the bump electrode 8, when the bump electrode 8 is fine, it is present in the pillar material metal 5. This is because the residual stress is particularly noticeable and causes the bump metal 8 to break due to the peeling of the barrier metal.

Therefore, in Japanese Patent Application No. 7-7079,
As shown in FIG. 18, the pillar material portion 5 for increasing the height of the fine bump electrode on the semiconductor chip has a concentration of 10 ⁻⁴ wt%.
-40% by weight of carbon, 10 ^-4 % by weight to 30% by weight of sulfur, 10 ^-4 % by weight to 10% by weight of oxygen, and by optimizing the material configuration of the bump electrode 8, reliability is improved. It is proposed to improve.

According to this method, the reliability can be improved to some extent as compared with the conventional methods, but the stress strain generated between the metals composed of the materials having different thermal expansion coefficients is reduced. A new problem arises in that the pillar material surface of the bump electrode is intensively applied and the pillar material of the bump electrode itself is destroyed. At the interface between the solder 7 and the pillar material 5, intermetallic peeling as shown in FIG. There was a problem that 10 occurred. The problem is that the pillar material 5 is copper and the connecting metal 7 is Pb / S.
Since n solder is used, C at the interface between solder 7 and copper 5
It was also one of the causes that the u-Sn intermetallic compound was formed. Further, with the recent development of semiconductor integrated circuits, the wiring in the circuit wiring board is also in the direction of higher density, and miniaturization using various methods is progressing. However,
When the thin film wiring is finely processed, the wiring cross-sectional area decreases,
As a result, the wiring resistance increases, so that it cannot be applied to wiring that requires high-speed signal transmission.

As a method for solving this problem, Japanese Patent Publication No. 2-40233 discloses a pattern plating method in which a portion other than the wiring formation portion is covered with a resist and electroplated.

However, according to this method, the obtained plating film thickness strongly depends on the surface condition of the substrate, so that the surface roughness of the plating film becomes larger than the surface roughness of the substrate. Furthermore, the internal stress of the plated film becomes large, causing problems such as peeling of wiring and defects such as cracks in the film.

This problem has been solved by using a plating solution containing an organic substance that reduces the surface roughness of the plating film and improves the mechanical properties.

However, when this method is used, the plating film becomes thicker on the side wall portion of the resist pattern, and there is a problem that a uniform film thickness cannot be obtained. Further, since the discontinuous portion of the physical properties is formed, the wiring is likely to be cracked, and there is a problem that the reliability of the wiring as a whole is lowered. These problems are caused by MCM-D in which plated wiring and a low dielectric constant polyimide insulating film are combined to form a laminate.
In such cases, it was particularly apparent. This is because if the plating wiring film thickness is not constant over the entire substrate, it becomes difficult to make the size of the via metal formed on the wiring constant, and it becomes impossible to reliably electrically connect the multilayer wiring metal. This is because.

A method for electrically and stably connecting circuit wirings between different multi-layer wiring layers is proposed in Japanese Patent Publication No. 2-40233, but it causes an increase in the number of steps and a decrease in yield and a cost reduction. It wasn't always enough because it would be high.

Therefore, in Japanese Patent Application No. 6-19314, 50% by weight of copper and nickel as shown in FIG. 20 is used.
A method has been proposed in which carbon and sulfur are dispersed and arranged on average in the wirings 23a and 23b made of the above-described materials.

According to this method, the carbon concentration and the sulfur concentration in the plating film, which affect the plating film thickness and the mechanical properties, are made uniform in the width direction of the pattern.
The film thickness can be made uniform over the entire substrate regardless of the width dimension of 23b. Therefore, the mechanical properties of the wirings 23a and 23b can be made uniform, and the film thickness distribution of the substrate 21 as a whole can be made small, so that it is possible to form the circuit wiring substrate 21 that is robust against thermal cycles and has high reliability. It will be.

When this method is applied to a multilayer wiring board,
Although the reliability can be secured to some extent, a long-term reliability test was performed and the failure mode was analyzed.
In some cases, the microcracks 20 were generated on the surface of the circuit wiring metal 23a and the wiring was partially open, as shown in FIG. Further, the crack 20 is generated also in the via metal 23b portion which is also the wiring connected to the multilayer wiring, the via connection is opened, and the reliability is not always sufficient.

Therefore, the electronic equipment mounted with the semiconductor device structure flip-chip mounted by using the conventional method cannot secure the reliability sufficiently, and the extremely high reliability of the high-end supercomputer and the like. There was a problem in adapting to the electronic equipment that is required.

[0023]

As described above, in the flip-chip mounting in which the bump electrodes formed on the semiconductor chip and the electrode pads of the circuit wiring board are interconnected, the stress caused by the difference in the thermal expansion coefficient is increased. Strain concentrates on the bump electrode,
The bump electrodes were broken.

Therefore, many methods have been proposed so far for alleviating the stress strain and improving the connection reliability.
For example, when a rigid pillar material metal made of copper is arranged in the bump electrode to increase the height of the bump electrode, the residual stress inherent in the pillar material metal becomes apparent, and the bump electrode is broken by peeling the barrier metal.

Therefore, a proposal was made to uniformly disperse carbon, sulfur and oxygen of a predetermined concentration in the metal to be formed as the pillar material to improve the reliability. However, due to the stress strain applied to the surface of the pillar material, the pillar material is There was a new problem of destruction.
This is due not only to the coefficient of thermal expansion of the copper and the solder, which are the pillar materials, but also to Cu-
It was also caused by the generation of Sn and was not always sufficient in terms of reliability.

In order to realize a high-performance circuit wiring board that enables high-speed signal propagation and high-density mounting,
Since it is important to obtain wiring with low resistance and fine width, even if the electroplating method effective for forming wiring with fine width is used, the surface roughness of the plating film is However, there are problems in ductility and film thickness uniformity.

Furthermore, when manufacturing a multilayer wiring board in which wiring having a low resistance and a fine width dimension and an insulating film having a low dielectric constant, such as a polyimide film, are manufactured, electrical characteristics and electrical characteristics can be obtained without increasing the number of steps. It was not possible to secure reliability.

Therefore, it has been proposed to uniformly disperse carbon and sulfur in the width direction of the pattern in the wiring made of a material containing 50% by weight or more of copper and nickel. According to this method, a circuit wiring having a uniform film thickness and excellent mechanical characteristics can be realized, so that a multilayer wiring board having a strong connection against thermal shock can be realized to some extent.

However, in the long-term reliability test of the circuit wiring board, there are problems that cracks occur on the wiring metal surface, the wiring becomes open, and connection failure occurs at the via connection portion, and this is not always a sufficient method. It was

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device having a highly reliable bump electrode structure capable of relieving stress concentrated on a bump electrode for flip-chip mounting. To aim.

Another object of the present invention is to provide a circuit wiring board having a high density and excellent electrical characteristics and reliability.

Still another object of the present invention is to provide a highly reliable semiconductor mounting structure in which a semiconductor device is flip-chip mounted on a circuit wiring board.

[0033]

In order to solve the above problems, the present invention (claim 1) provides a semiconductor chip, a bonding pad formed on the semiconductor chip, and a bump electrode formed on the bonding pad. And
The bump electrode is formed on the first metal layer formed on the bonding pad, the second metal layer arranged on the first metal layer, and the second metal layer, and the circuit wiring is formed. A third metal layer for connecting to the substrate,
In the vicinity of the interface where the second metal layer contacts the third metal layer, at least one selected from the group consisting of carbon, sulfur, and oxygen has a higher concentration than the internal region of the second metal layer. There is provided a semiconductor device having a high-concentration region dispersed therein.

According to the present invention (claim 2), in the above semiconductor device (claim 1), the second metal layer is made of a metal material containing 50% by weight or more of copper, nickel or an alloy thereof. It is characterized by

According to the present invention (claim 3), in the semiconductor device (claim 1 or 2) described above, the high concentration region of the second metal layer is 1 × 10 ⁻⁴ wt% to 0.1 wt%. Of carbon,
3 × 10 ⁻⁴ wt% to 10 wt% sulfur, and 1 × 10
It is characterized by containing at least one selected from the group consisting of ^-5 wt% to 0.1 wt% oxygen.

According to the present invention (claim 4), in the semiconductor device (claims 1 to 3) described above, the high concentration region of the second metal layer has a maximum dimension of 2 in a vertical cross section of the second metal layer.
It is characterized by having a thickness of 0% or less.

The present invention (Claim 5) is a circuit wiring board comprising circuit wiring on at least one of the surface of the substrate and the inside of the substrate, wherein the surface of the circuit wiring is carbon, rather than its internal region. Provided is a circuit wiring board having a high-concentration region in which at least one selected from the group consisting of sulfur and oxygen is dispersed at a high concentration.

According to the present invention (claim 6), in the above-mentioned circuit wiring board (claim 5), the circuit wiring is made of a metal material containing 50% by weight or more of copper, nickel or an alloy thereof. Characterize.

According to the present invention (claim 7), in the above-mentioned circuit wiring board (claim 5 or 6), the high-concentration region of the circuit wiring is 1 × 10 ⁻⁴ wt% to 0.1 wt% carbon. Three
X10 ^-4 wt% to 10 wt% sulfur, and 1 x 10 ^-5
It is characterized by containing at least one selected from the group consisting of oxygen of 0.1% by weight to 0.1% by weight.

According to the present invention (claim 8), in the above-mentioned circuit wiring board (claims 5 to 7), the high-concentration region of the circuit wiring has a maximum dimension of 20 in a vertical cross section of the circuit wiring.
% Or less.

According to the present invention (claim 9), in the above-mentioned circuit wiring board (claims 5 to 8), the circuit wiring is a multi-layer circuit wiring provided in multiple layers on the board, and a via metal interconnecting the circuit wiring. And at least one selected from the group consisting of metal terminals for component connection mounted on the substrate.

According to the present invention (claim 10), the semiconductor device (claims 1 to 4) described above is flip-chip mounted on a circuit wiring board having circuit wiring on at least one of the surface and the inside of the board. Provided is a semiconductor device mounting structure.

The present invention (claim 11) comprises a semiconductor chip, a bonding pad formed on the semiconductor chip, and a bump electrode formed on the bonding pad, wherein the bump electrode is the bonding pad. A first metal layer formed on the first metal layer, a second metal layer arranged on the first metal layer, and a second metal layer formed on the second metal layer for connecting to a circuit wiring board. Provided is a semiconductor device mounting structure, wherein a semiconductor device having a metal layer of No. 3 is flip-chip mounted on the above-mentioned circuit wiring board (claims 5 to 9).

The present invention (Claim 12) includes the above semiconductor device (Claims 1 to 4), the semiconductor device according to any one of Claims 1 to 4, and the above circuit wiring board (Claim 1). 5-9) A semiconductor device mounting structure is provided, which is flip-chip mounted on the semiconductor device mounting structure.

The first aspect of the present invention, in which the present invention is described more specifically below, is a semiconductor chip, a bonding pad formed on the semiconductor chip, and a bump electrode formed on the bonding pad. A semiconductor device comprising: The bump electrode is formed on the first metal layer formed on the bonding pad, the second metal layer arranged on the first metal layer, and the second metal layer. Third to be connected to the substrate
And a metal layer of the second metal layer near the interface where the second metal layer contacts the third metal layer, and is selected from the group consisting of carbon, sulfur, and oxygen rather than the internal region of the second metal layer. There is a high-concentration region in which at least one of them is dispersed in a high concentration.

In such a semiconductor device, the first metal layer plays a role of firmly adhering the semiconductor chip and the bump electrode, and the material thereof is Cu / T.
i, Cu / Cr, Ni / Ti, Ni / Cr, Ni / W /
Ti, Ni / W-Ti, Cu / W / Ti, Cu / WT
i, Pt / Ni / Ti, Cu / Ni / Ti, Ni / Cu
A laminated film of / Ti or the like can be used. The thickness of the first metal layer is preferably about 0.1 to 3 μm.

The second metal layer plays a role as a pillar material of the bump electrode, and the material thereof is copper,
Nickel, copper alloy, nickel alloy, copper-nickel alloy,
Copper-nickel-titanium alloy, copper-nickel-chromium alloy, copper-chromium alloy, nickel-chromium alloy, aluminum-nickel alloy, palladium-copper alloy and the like can be used. The thickness of the second metal layer is preferably about 1 to 50 μm.

As the third metal layer, PbSn, InA
g, InPb, BiInSn, BiInPb, SnA
A solder such as g or AuSn can be used. When the solder is PbSn, its composition is 20 Pb / Sn.
It is preferably about / 80 to 45/5. The thickness of the third metal layer is preferably about 3 to 100 μm.

A preferred combination of materials for the first, second and third metal layers is Cu / Ti laminated film-copper-solder.

The concentration of carbon, sulfur and oxygen that can be contained in the high concentration region of the second metal layer is such that carbon is 1 × 10 ⁻⁴ wt%.
0.1% by weight, preferably 1 × 10 ⁻³ % by weight to 0.01
% By weight, sulfur 3 × 10 ⁻⁴ % by weight to 10% by weight, preferably 3 × 10 ⁻³ % by weight to 0.01% by weight, oxygen 1 × 1
0 ^-5 wt% to 0.1 wt%, preferably 1 × 10 ^-4 wt% to 0.001 wt%. If the concentration is below the lower limit, the stress relaxation effect of the present invention is hindered, and if it exceeds the upper limit, the metal resistance is abnormally increased, which causes a connection open failure.

In the high-concentration region of the second metal layer, for example, a film of the same material as that of the metal material forming the second metal layer is formed by electroplating using a plating bath having a predetermined composition. Can be obtained by performing electroplating while changing the composition of the plating bath so that the concentrations of carbon, sulfur and oxygen are high.

The concentration of carbon, sulfur and oxygen that can be contained in the high concentration region of the second metal layer is about 1.5 to 3 times the concentration of carbon, sulfur and oxygen contained inside the second metal layer. Is preferred.

According to the semiconductor device of the first aspect of the present invention, the interface in contact with the third metal, which is the surface of the second metal layer serving as the pillar material of the bump electrode, is different from the internal region. And because carbon, sulfur and oxygen are dispersed in high concentration,
The ductility becomes high at the surface portion of the second metal layer where the stress is most concentrated, and the material structure can be made strong against stress strain. Therefore, it is possible to realize a highly reliable semiconductor device without the metal as the pillar material being destroyed as in the past.

Particularly when a metal material containing 50% by weight or more of copper or nickel is used as the second metal layer,
This constituent material has low ductility until now, and it has been difficult to secure sufficient reliability against stress strain. However, according to this aspect, carbon, sulfur, and oxygen are not generated near the surface of the second metal layer. Since the region in which the concentration is higher than that of the internal region is formed, the ductility is significantly improved.

Particularly, in the high concentration dispersion region of the second metal layer, carbon is 1 × 10 ⁻⁴ wt% to 0.1 wt% and sulfur is 3 wt%.
× 10 ^-4 wt% to 10 wt%, oxygen is 1 x 10 ^-5 wt%
To 0.1% by weight, and the thickness of the high-concentration dispersion region is set to 20% or less of the maximum dimension in the vertical cross section of the second metal layer, thereby significantly improving reliability. Is possible.

A second aspect of the present invention provides a circuit wiring board having circuit wiring on at least one of the surface of the substrate and the inside of the substrate. Also in this aspect, as in the first aspect, the surface of the circuit wiring has a high concentration in which at least one selected from the group consisting of carbon, sulfur, and oxygen is dispersed in a higher concentration than in the internal region thereof. It is characterized by the existence of a density region.

In such a circuit wiring board, the material of the circuit wiring is copper, nickel, copper alloy, nickel alloy,
Copper-nickel alloy, copper-nickel-titanium alloy, copper-nickel-chromium alloy, copper-chromium alloy, nickel-chromium alloy, palladium-nickel alloy, palladium-copper alloy and the like can be used.

Carbon which may be contained in the high concentration region of the circuit wiring,
Regarding the concentration of sulfur and oxygen, carbon is 1 × 10 ⁻⁴ wt% to 0.1.
% By weight, preferably 1 × 10 ⁻³ % by weight to 0.01% by weight, sulfur 3 × 10 ⁻⁴ % by weight to 10% by weight, preferably 3 × 10 ⁻³ % by weight to 0.01% by weight, oxygen Is 1 × 10 ^-5
% By weight to 0.1% by weight, preferably 1 × 10 ^-4 % by weight
It is 0.001% by weight. If the concentration is below the lower limit, the stress relaxation effect of the present invention is hindered, and if it exceeds the upper limit, the metal resistance is abnormally increased, which causes a connection open failure.

The high concentration region of the circuit wiring can be formed by the same method as the high concentration region of the second metal layer in the first mode.

Carbon which may be contained in the high concentration region of the circuit wiring,
The concentration of sulfur and oxygen depends on the carbon contained inside the circuit wiring,
It is preferably about 1.5 to 3 times the concentration of sulfur and oxygen. According to the semiconductor device of the second aspect of the present invention, the surface region of the circuit wiring has a structure in which carbon, sulfur, and oxygen are dispersed at a higher concentration than in the internal region. The strength against the stress strain on the wiring surface is improved, and it is possible to prevent a defect in the circuit wiring caused by the stress strain caused by the temperature cycle.

In particular, when a metal material containing 50% by weight or more of copper or nickel is used for the circuit wiring, this constituent material has low ductility until now, and sufficient reliability against stress strain must be ensured. However, according to this aspect, there is a region in which carbon, sulfur, and oxygen are dispersed in a higher concentration than the internal region in the vicinity of the surface of the circuit wiring. It has a significantly improved effect.

In particular, the high-concentration dispersed region of the circuit wiring is
1 × 10 ⁻⁴ wt% to 0.1 wt% carbon, 3 × 1 sulfur
0 ^-4 wt% to 10 wt%, oxygen is 1 x 10 ^-5 wt%
By setting it to 0.1% by weight, the thickness of the high-concentration dispersion region is set to 2 times the maximum dimension in the vertical cross section of the second metal layer.
By setting the size to 0% or less, the reliability can be significantly improved.

Further, the circuit wiring according to the second aspect of the present invention is a circuit wiring forming a multilayer circuit wiring board, a via metal interconnecting the circuit wiring, or a component terminal metal mounted on the circuit wiring board. It is possible to prevent the open defect in the via part, which has been a problem until now, when the multilayer circuit wiring is configured, and it is possible to prevent the occurrence of cracks in the external terminal, which improves reliability. It is possible to realize a semiconductor device having high cost.

A third aspect of the present invention provides a semiconductor device mounting structure in which a semiconductor device is flip-chip mounted on a circuit wiring board. In this case, at least one of the semiconductor device and the circuit wiring board can be the semiconductor device according to the first aspect of the present invention or the circuit wiring board according to the second aspect.

According to the third aspect of the present invention, a high-concentration dispersion layer is provided on at least one of the semiconductor device and the circuit wiring board, that is, on the second electrode surface of the bump electrode of the semiconductor device, or the circuit wiring is formed. By providing the high-concentration dispersion layer on the circuit wiring surface of the substrate, or by providing the high-concentration dispersion layer on both of them, a semiconductor device mounting structure having high reliability can be realized.

[0066]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

The following Examples 1 to 3 relate to the first aspect of the present invention.

[Embodiment 1] FIG. 1 is a sectional view showing a semiconductor device having bump electrodes according to the present embodiment. In FIG. 1, reference numeral 1 indicates a semiconductor chip, and a bonding pad 2 made of aluminum or an alloy mainly composed of aluminum is formed on the semiconductor chip 1, and the semiconductor chip 1 except for the bonding pad 2 portion. Above, for example, PSG (phosphorus-silica-glass)
Alternatively, the passivation film 3 made of SiN (silicon nitride) is formed.

On the bonding pad 2, Cu / Ti
A first metal layer 4 made of (a laminated film of a Cu film and a Ti film) is formed, and a second metal layer 5 made of copper is formed on the first metal layer 4.
Are formed. Further, around the second metal layer 5,
A copper thin film 6 containing carbon, sulfur or oxygen in a high concentration is formed. Further, a third metal layer 7 made of a solder alloy is formed on the copper thin film 6. These first metal layer 4, second metal layer 5, copper thin film 6 and third metal layer 7
Thus, the bump electrode 8 is formed.

The semiconductor device configured as described above is manufactured according to the steps shown in FIGS. The manufacturing process will be described below in the order of steps.

First, as shown in FIG. 2A, a bonding pad 2 is formed on a semiconductor chip 1 and, for example, PSG (phosphorus-silica-glass) or SiN (silicon nitride) is removed except for the bonding pad 2. For example, a Cu / Ti laminated film 2 is formed on the entire surface of the semiconductor device chip 1 on which the passivation film 3 composed of is formed, and a cathode metal for forming bump electrodes by electroplating is formed.

The Cu / Ti laminated film 4 forms a first metal layer which finally becomes a barrier metal of the bump electrode by forming a bump electrode by electroplating and then etching a necessary portion. Therefore, the material is not limited to the Cu / Ti laminated film, but for the sake of explanation, the Cu / Ti laminated film is used. Similarly, the semiconductor chip 1 does not need to be silicon, but in the present embodiment, it is silicon for the sake of explanation.

Next, as shown in FIG. 2 (b), a thick film resist AZ4903 (manufactured by Hoechst Japan Co., Ltd.) was formed to a film thickness of 100 μm by a spin coating method, and an opening size of 40 μm square was formed by exposure and development. Has a dimension in which one side is 5 μm larger than the bonding pad it has,
The resist pattern 12 having an opening of 45 μm is formed by Cu.
/ Ti laminated film. The exposure is performed with sufficient amount of exposure energy even if the resist is thick, and the development is AZ.
This is performed using a 400K developer (manufactured by Hoechst Japan). At this time, the angle adjustment of the portion of the resist surface in contact with the thin film metal can be controlled by adjusting the exposure energy, the distance between the resist surface and the glass mask, and the concentration of the developing solution. For more details, see 13th IEM
T Symposium pp 288,1992.

In this way, the semiconductor chip 1 having the resist pattern 11 having an opening smaller than the bonding pad in the portion corresponding to the bonding pad is dipped in a copper sulfate plating solution containing the following solution. Then, at a bath temperature of 25 ° C., the Cu / Ti laminated film 4 was used as a cathode, and a phosphorus-containing (0.03 to 0.08 wt%) high-purity copper plate was used as an anode, and the current density was 1 to 5 (A / dm ² ) and was moderate. An electroplating operation is performed with stirring to form a second metal film 5 made of copper to a thickness of 30 μm, as shown in FIG.

FIG. 5 shows a schematic sectional view of an electroplating apparatus used in the electroplating process. This apparatus is of a type in which the main surface of the wafer is arranged downward and plating is performed. The plating solution contained in the plating tank 50 is jetted by a pump and flows in the direction of the arrow. With such an electroplating apparatus, an electroplating film having a uniform film thickness can be obtained. In the figure, reference numeral 51 is an anode plate, 52 is an anode pin, 53 is a cathode pin, 54 is a cathode electrode, and 55 is an anode electrode.

The second metal layer 5 does not necessarily need to be plated to a thickness of 30 μm, and there is no problem if it is thicker than the thickness of the first metal layer 4 due to the mutual relationship with the thickness of the first metal layer. .

Copper sulphate pentahydrate 2 ounces / gallon Sulfuric acid 30 ounces / gallon hydrochloric acid 10 ppm Thioxysantate-S-propanesulfonic acid (or thioxysantate sulfonic acid) 20 ppm Polyethylene glycol (molecular weight: 400,000) ) 40 ppm Polyethyleneimine (molecular weight: 600) and reaction product of benzyl chloride 2 ppm Next, as shown in FIG. 3 (a), a resist pattern 11 having an opening in the bonding pad portion was formed using acetone. Dissolve and remove. Next, the plating solution is immersed in a copper sulfate plating solution consisting of the following mixed solution, and the bath temperature is 25 ° C.
Then, the Cu / Ti laminated film is used as a cathode, and phosphorus-containing (0.0
3 to 0.08 wt%) A high purity copper plate is used as an anode, and electroplating operation is performed while gently stirring at a current density of 1 to 5 (A / dm2) to form a copper film 6 as shown in FIG. 3 (b). 5
It is formed to a thickness of μm.

Copper sulfate pentahydrate 30 oz / gallon Sulfuric acid 8 oz / gallon Hydrochloric acid 30 ppm Dithiocarbamate-S-propanesulfonic acid 30 ppm Polypropylene glycol (molecular weight: 700) 10 ppm Polyethyleneimine and allyl bromide or dimethylsulfate Reaction product of 0.3 ppm, the copper thin film 6 electroplated using the electroplating solution described above has a carbon content higher than that of the second metal layer 5 made of electroplated copper. It has a composition in which both sulfur and oxygen are dispersedly contained at a high concentration.

Further, a thick film resist AZ4903 was again formed to a thickness of 100 μm by a spin coating method, and a dimension of one side of the projection was larger than this projection at a position corresponding to the projection of the copper thin film 6 by 10 μm. With 60μ
An opening m is formed by exposure / development to obtain a thick film resist pattern 12 as shown in FIG. 3 (c).

Then, the plating solution is immersed in a sulfonic acid solder plating solution described below to use the Cu / Ti laminated film 4 as a cathode and a composition corresponding to the plating solution as in the case of electrolytic copper plating. Electroplating is performed using, for example, a high-purity eutectic solder plate as an anode. Current density is 1
4 (A / dm ² ), a solder alloy having a composition in which the solder composition (Pb / Sn) is approximately equal to the eutectic composition or slightly shifted to the Pb side or the Sn side while gently stirring at a bath temperature of 25 ° C. , A thickness of 15 μm is deposited on the copper film 6, and a third metal layer 7 is formed as shown in FIG.

Composition of Sulfonic Acid Solder Plating Solution Tin ion (Sn ²⁺ ) 12 vol% Lead ion (Pb ²⁺ ) 30 vol% Aliphatic sulfonic acid 41 vol% Nonionic surfactant 5 vol% Cationic surfactant 5 vol% isopropyl alcohol 7 vol% In this manner, bump electrode carbons composed of the first to third metal layers are formed by continuously plating each metal layer on the bonding pad. Then, FIG. 3 (e)
As shown in FIG. 3, the resist pattern 12 on the wafer is dissolved and removed by using acetone.

Next, a solution in which the viscosity of an image reversal resist AZ5214E (manufactured by Hoechst Japan Co., Ltd.) is spin-coated on the wafer on which the bump electrodes on the Cu / Ti laminated film are formed, is used as an etching resist. Form a film. Viscosity adjustment requires high viscosity in order to perform etching accurately even when the metal film to be plated is thick. At this time, the resist film has a shape corresponding to the bump metal on the surface, and is 10 μm above the bump metal.
m, and the portion where the bump metal was not formed had a film thickness of 55 μm.

Next, exposure is performed after aligning a glass mask having an opening pattern of 64 μm on each side with an opening size of 4 μm larger than the bump electrode size of 60 μm to a required position. Exposure energy is 2000 mJ / cm
Step ² and bake the wafer on a hot plate at 150 ° C after exposure. Next, the baked wafer is immersed in a developing solution for development.

By performing the above steps, the resist pattern 13 is selectively formed only on the third metal layer 7, as shown in FIG.

Although the image reversal type resist is used in this embodiment, the positive type resist OFPR is used in the aspect ratio shape in which the resist can be formed up to the side surface portion of the third metal layer.
-800 (Tokyo Ohka Co., Ltd.) or negative resist OMR
It is also possible to use -85 (manufactured by Tokyo Ohka Co., Ltd.).

Then, using a mixed solution of ammonium persulfate, sulfuric acid and ethanol, or a mixed solution of citric acid, hydrogen peroxide solution and a surfactant, the Cu film portion of the Cu / Ti laminated film 2 is selectively selected. After etching away, the Ti film portion of the Cu / Ti laminated film 2 was removed by etching with a mixed solution of ammonia, ethylenediamine tetraacetic acid and hydrogen peroxide solution, and finally the third metal layer was coated. The resist pattern 13 is dissolved and removed using acetone to obtain the structure shown in FIG.

By performing the above steps, the second metal layer 5 and the copper thin film 6 having different carbon, sulfur, or oxygen contents are formed on the bonding pad, and the surroundings are solder (third metal). 1 and 4 coated with layer 7)
The bump electrode 8 having a diameter of 100 μm shown in (c) was formed.

Example 2 A bump electrode was formed in the same manner as in Example 1 except that nickel was used instead of copper as the second metal layer.

For nickel plating, the Cu / Ti film 4 formed on the wafer was connected to the cathode of the electroplating apparatus by using the same electroplating apparatus as shown in FIG.
This was done using a high purity nickel plate as the anode.

The electroplating conditions were a liquid temperature of 55 ° C., a current density of 1 to 2 (A / dm ² ), and a nickel plating film having a thickness of about 30 μm was formed while gently stirring the nickel plating solution. .

A solution having the following composition was used as the nickel plating solution.

Nickel sulfate hexahydrate 300 g / liter Nickel chloride hexahydrate 60 g / liter Boric acid 50 g / liter Saccharin 500 ppm to 5000 ppm Formalin 1000 ppm to 2000 ppm Subsequently, similarly to the case of copper plating, a resist film on a wafer. Is dissolved and removed with acetone, and the plating solution is immersed in a mixed solution consisting of the following to electroplate second nickel to a film thickness of 5 μm.

The solution for forming the second nickel by electroplating has an increased concentration of the additive containing carbon, sulfur or oxygen as compared with the plating solution for electroplating the first nickel.

Nickel sulfate hexahydrate 300 g / liter Nickel chloride hexahydrate 60 g / liter Boric acid 50 g / liter Saccharin 7000 ppm to 20000 ppm Formalin 3000 ppm to 8000 ppm In the following steps, methanol, hydrochloric acid and copper sulfate were used as etching solutions. The procedure is the same as the case of forming copper as the second metal layer except that the contained solution is used.

In the above Examples 1 and 2, an example using copper and nickel as the second metal layer is described, but an alloy mainly containing copper or nickel may be used.

Example 3 A bump electrode was formed in the same manner as in Examples 1 and 2 except that a copper / nickel alloy was used instead of copper and nickel as the second metal layer.

The reliability of the semiconductor devices according to Examples 1 to 3 obtained as described above was evaluated, and the following results were obtained.

That is, the solder having the composition of Pb / Sn = 40/60 was used as the third metal layer on the 10 mm × 10 mm semiconductor chip used for explaining the method for manufacturing the semiconductor device, and the second When 256 bump electrodes using copper as a metal layer were formed with a diameter of 100 μmφ and the shear strength of the bump electrode according to Example 1 was measured, it was 80 k.
It had a strength of g / mm ² .

On the other hand, in the conventional bump electrode structure in which the high concentration layer of carbon, sulfur and oxygen is not provided on the surface of the second metal layer made of copper, the shear strength is 40 kg / m.
m ² and the shear strength is 60 kg / mm ² in the structure in which carbon, sulfur and oxygen are uniformly dispersed in the second metal layer, in comparison with the structure of the bump electrode in Example 1, It was confirmed that the connection strength to the semiconductor chip was improved and the reliability was high.

Similarly, in the structure of the bump electrode according to Example 2 in which nickel is used as the second metal layer, the shear strength is 70 kg / mm ² , whereas the surface of the second metal layer made of nickel is In the structure of the conventional bump electrode in which a high concentration layer of carbon, sulfur and oxygen is not provided in the above, the shear strength is 30 kg / mm ² , and carbon, sulfur and oxygen are evenly distributed in the second metal layer made of nickel. The shear strength was 55 kg / mm ² in the structure dispersed in. As described above, it was confirmed that the structure of the bump electrode according to the second embodiment had a clearly improved connection strength with respect to the semiconductor chip and had high reliability.

Further, in the structure of the bump electrode according to the third embodiment using the copper / nickel alloy as the second metal layer, the shear strength is 75 kg / mm ^{2 although it} varies depending on the alloy ratio.
On the other hand, in the conventional bump electrode structure in which the high-concentration layer of carbon, sulfur, and oxygen is not provided on the surface of the second metal layer made of the copper / nickel alloy, the shear strength is 40 k.
a g / mm ^2, carbon second metal layer made of copper / nickel alloy, sulfur, shear strength with oxygen and uniformly dispersing the structure was 65 kg / mm ^2. in this way,
It has been confirmed that the structure of the bump electrode according to the third embodiment is clearly improved in connection strength with respect to the semiconductor chip and has high reliability.

The above results indicate that the residual stress on the surface of the second metal layer, which was separately evaluated, was reduced by about 10% as compared with the conventional residual stress due to the structure in which carbon, sulfur and oxygen were uniformly dispersed. In addition, due to the heat applied when the solder bumps are reflowed, the copper forming the second metal layer has little Cu-Sn or NiSn generated by reacting with the solder, and the metal diffusion can be sufficiently controlled. Conceivable.

Further, the bump shear strength of the semiconductor device according to Example 1 in which a high concentration layer of carbon, sulfur and oxygen was provided on the surface of the second metal layer made of copper was evaluated after the 150 ° C., 1000 H high temperature storage test. As a result, the shear strength is 75 to 8
Although it hardly changed at 0 kg / mm ² , in the conventional bump electrode structure in which the high concentration layer of carbon, sulfur and oxygen is not provided on the surface of the second metal layer made of copper,
30 kg / mm ² , carbon in the second metal layer made of copper,
55 kg / mm for a structure in which sulfur and oxygen are evenly dispersed
It fell significantly to ² .

Further, in the case of the bump electrode according to Example 2 in which a high concentration layer of carbon, sulfur and oxygen is provided on the surface of the second metal layer made of nickel, the shear strength is 65 to 70 kg / m.
There is almost no change in m ² , whereas in the conventional bump electrode structure in which the high concentration layer of carbon, sulfur and oxygen is not provided on the surface of the second metal layer made of nickel, it is 25 kg.
/ Mm ² , 40 kg / mm ^{2 for} a structure in which carbon, sulfur and oxygen are uniformly dispersed in the second metal layer made of nickel
And fell significantly.

Further, in the case of the bump electrode according to Example 3 in which the high concentration layer of carbon, sulfur and oxygen is provided on the surface of the second metal layer made of the alloy of copper and nickel, the shear strength is 70 to 7.
While there is almost no change at 5 kg / mm ² , in the conventional bump electrode structure in which the high concentration layer of carbon, sulfur and oxygen is not provided on the surface of the second metal layer made of an alloy of copper and nickel, In the structure in which carbon, sulfur and oxygen are uniformly dispersed in the second metal layer of 20 kg / mm ² and the alloy of copper and nickel, it is greatly reduced to 45 kg / mm ² .

This shows that the structure according to the present invention hardly causes intermetallic diffusion due to high temperature storage and has high reliability.

From the above results, it was confirmed that the structure of the semiconductor device according to the present invention (Examples 1 to 3) is extremely high in reliability as compared with the structure of the conventional semiconductor device.

The following Examples 4 to 7 relate to the second aspect of the present invention.

[Embodiment 4] FIG. 6 is a cross-sectional view showing a circuit wiring board according to this embodiment and a diagram showing distributions of carbon concentration, sulfur concentration and oxygen concentration in the cross section. Figure 6
In FIG. 1A, reference numeral 21 indicates a glass epoxy substrate, and a circuit wiring pattern 23 is arranged on the glass epoxy substrate 21 via an adhesive metal layer 22 made of a Cu / Ti laminated film. On the surface of the circuit wiring pattern 23, a high-concentration region 24 made of the same material as the circuit wiring pattern 23 and having a high concentration of carbon, sulfur, and / or oxygen is formed.

The circuit wiring pattern 23 has a width of 30 μm.
Those having a diameter of m or less and those having a diameter of more than 30 μm are formed. From FIG. 6A, it can be seen that the film thickness is constant regardless of the width dimension of the circuit wiring pattern, and that the film thickness is not thick near the sidewall of the resist pattern.

FIGS. 6B to 6D show distributions of carbon concentration, sulfur concentration and oxygen concentration in a partial cross section of this circuit wiring board. In the circuit wiring board according to the present embodiment, carbon contained in the outer peripheral portion of the circuit wiring pattern in the width direction is 1 × 10 ⁻⁴ wt% to 0.1 wt% and sulfur is 3 wt%.
× 10 ^-4 wt% to 10 wt%, oxygen is 1 x 10 ^-5 wt%
Is within the range of 0.1 wt.
Has a dimension of 20% or less of the width dimension of the entire circuit wiring pattern 23.

Next, FIG. 6A configured as described above.
A method of manufacturing the circuit wiring board shown in will be described with reference to FIGS. 7 and 8.

First, as shown in FIG. 7A, the Cu / Ti laminated film 22 is continuously formed on the surface of the glass epoxy substrate 21. The total thickness of these metal films is about 1 μm. Here, the copper film acts as a plating cathode, and the titanium film acts as a metal layer that enhances the adhesion between the copper film and the glass epoxy substrate. Therefore, the thickness of the titanium film may be small, and about 0.1 μm is sufficient. Although the adhesion between copper and glass epoxy is low, peeling of the copper film can be prevented by forming the titanium film as the adhesive layer. However, since the surface of titanium is easily oxidized, it is preferable to continuously form the upper copper film in the same vacuum. By thus forming the laminated film of the titanium film and the copper film, it is possible to form a low-resistance plating cathode having high adhesion.

Then, for example, AZ4903 (manufactured by Hoechst Japan) is applied to the surface of the glass epoxy substrate 21 by a spin coating method to form a plating resist film having a film thickness of 20 μm, and prebaking is performed at 90 ° C. Then, an opening having a predetermined wiring pattern shape having a width of 15 μm to 10 μm is formed by exposure / development, and a plating resist pattern 31 is formed as shown in FIG. 7B.

The glass epoxy substrate 21 on which the resist pattern 31 is formed in this manner is installed in the electroplating apparatus shown in FIG. 5 to form the copper wiring pattern 23. Figure 5
As shown in, the electroplating apparatus contains a plating solution in a plating tank, in which an anode and a cathode are arranged in parallel.

The electroplating is carried out by connecting the copper film on the glass epoxy substrate 21 to the cathode of the electroplating apparatus and using a phosphorus-containing (0.03-0.08 wt%) high-purity copper plate as the anode. The plating conditions are a liquid temperature of 25 ° C and a current density of 1 to 5
As (A / dm ² ), as shown in FIG.
An electroplated copper film 23 having a film thickness of about 18 μm is formed. The electroplated copper film 23 constitutes a circuit wiring pattern.

The following solutions can be used as the plating solution.

Copper sulfate pentahydrate 75 g / l Sulfuric acid 100 ml / l Hydrochloric acid 0.15 ml / l Thioxysantate-S-propanesulfonic acid (or thioxysantate sulfonic acid) 40 ppm Polyethylene glycol (molecular weight: 400, 000) 80 ppm Reaction product of polyethyleneimine (molecular weight: 600) with benzyl chloride 4 ppm Subsequently, the resist AZ4903 on the wafer where the bonding pad portion is opened is dissolved and removed using acetone. Next, the plating solution is immersed in a copper sulfate plating solution consisting of the following mixed solution, and at a bath temperature of 25 ° C., Cu / Ti
Using the laminated film as a cathode, phosphorus-containing (0.03-0.
(8 wt%) Using a high-purity copper plate as an anode, copper was formed on the entire surface of the wafer by electroplating to a thickness of 5 μm while gently stirring at a current density of 1 to 5 (A / dm ² ). A copper thin film 24 is formed as shown in FIG.

Copper sulfate pentahydrate 75 g / liter Sulfuric acid 100 ml / liter Hydrochloric acid 0.15 ml / liter Dithiocarbamate-S-propanesulfonic acid 40 ppm Polypropylene glycol (molecular weight: 700 40 ppm Polyethyleneimine and allyl bromide or dimethyl sulfate and Reaction product of 1.2 ppm, and further, a thick film resist AZ4903 is applied and formed on the glass epoxy substrate 21 on which the wiring pattern 23 is formed by a spin coating method to form a plating resist film having a film thickness of 20 μm. Prebaking is performed at a temperature of C. After that, the plating resist film is patterned by exposure / development, and a wiring pattern 23 having a copper thin film 24 formed on its surface is covered with a resist pattern 27 as shown in FIG. To do.
Note that the resist width is 3 μm larger than the wiring width,
It is preferable to perform exposure by using a glass mask having a pattern dimension in which a conversion error is also taken into consideration.

Then, the Cu / Ti laminated film is removed by etching except the portion covered with the resist pattern 27. As the etchant used for removing each thin film, the mixed solution described below can be used.

That is, after etching the copper film with a mixed solution containing ammonium persulfate, sulfuric acid and ethanol, the titanium film is etched with a mixed solution containing ethylenediaminetetraacetic acid, ammonia and hydrogen peroxide solution.

Finally, by removing the resist pattern using acetone, as shown in FIG.
A circuit wiring board is obtained.

Example 5 A circuit wiring board was prepared in the same manner as in Example 4 except that nickel was used as the wiring metal. For the nickel plating film, an electroplating device similar to the device shown in FIG. 5 was used, the copper film on the glass epoxy substrate 21 was connected to the cathode of the electroplating device, and the high purity nickel plate was connected to the anode. Form. The electroplating conditions are a liquid temperature of 55 ° C. and a current density of 1 to 2 (A / dm ² ), and the electroplating solution is agitated by a circulation pump to obtain a nickel plating film having a thickness of about 18 μm.

A solution having the following composition can be used as the plating solution.

Nickel Sulfate Hexahydrate 300 g / L Nickel Chloride Hexahydrate 60 g / L Boric Acid 50 g / L Saccharin 500 ppm-5000 ppm Formalin 1000 ppm-2000 ppm Subsequently, a resist film on a wafer was formed in the same manner as in the case of copper. It is dissolved and removed with acetone and the plating solution is immersed in a mixed solution consisting of the following, and a nickel thin film is electroplated to a thickness of 5 μm on the surface of the circuit wiring pattern made of nickel.

The solution for forming this nickel thin film by electroplating increases the concentration of the additive containing carbon, sulfur and oxygen, as compared with the plating solution for electroplating the circuit wiring pattern made of nickel. I am doing it.

Nickel Sulfate Hexahydrate 300 g / L Nickel Chloride Hexahydrate 60 g / L Boric Acid 50 g / L Saccharin 7000 ppm to 20000 ppm Formalin 3000 ppm to 8000 ppm [Example 6] Instead of copper and nickel as the second metal layer A circuit wiring board was manufactured in the same manner as in Examples 1 and 2 except that the copper / nickel alloy was used.

As described above, when the cross section of the circuit wirings on the circuit wiring boards obtained in Examples 4 to 6 was observed with a scanning electron microscope, as shown in FIG. A good film was obtained, and the film did not become thick near the side wall of the pattern. Further, the concentration distributions of carbon, sulfur and oxygen were measured by Auger electron spectroscopy.
The results shown in (b) to (d) were obtained. That is,
In the present embodiment, when the wiring is formed by the electroplating method, the concentration of the polyether compound, the organic sulfur compound added to the copper plating solution, or the other organic additive added to the nickel plating solution is set within a predetermined range. Because it is prescribed
The concentrations of carbon, sulfur and oxygen in the plating liquid film can be mutually changed.

Therefore, the deposited plating film does not depend on the width dimension of the wiring and can have a uniform film thickness and uniform mechanical properties, so that the film thickness distribution is small and it is highly reliable against thermal shock. The circuit wiring can be obtained.

Example 7 FIG. 9 shows an example of a multilayer wiring board formed by using the present invention. As shown in FIG. 9, the Cu / Ti laminated film 42 is selectively formed on the glass epoxy substrate 41 as in the above-described embodiment. A first wiring layer composed of a wiring pattern 43a made of copper and a planarization insulating film 44a made of polyimide is provided on the Cu / Ti laminated film 42. A first contact layer composed of a via stud 45a made of copper and an interlayer insulating film 46a made of polyimide is provided on the first wiring layer.

The first contact layer has the same structure as that of the first wiring layer, that is, the wiring pattern 43b.
And a second wiring layer constituted by the planarization insulating film 44b. On top of that, via stud 4
5b and an interlayer insulating film 46b are provided as a second contact layer, and the wiring pattern 43c is provided on the uppermost layer.
And a planarization insulating film 44c are provided to form a third wiring layer to form a multilayer wiring board. External connection terminals 48 are provided on the uppermost wiring pattern 43c.

The multilayer wiring board constructed as described above is
It is manufactured as follows by the same method as in Examples 4 and 5 above. That is, first, the glass epoxy substrate 41
A titanium film and a copper film are sequentially stacked on top to form a Cu / Ti stacked film 42. Then, a copper plating film or a nickel plating film is formed to obtain the wiring pattern 43a. Then, on this substrate 41, for example, Photo Nice UR-314
0 (manufactured by Toray) is applied as a photosensitive polyimide precursor,
After prebaking at 110 ° C, 1 by exposure / development
A contact hole having a side of about 10 μm is formed. Furthermore, imidization is performed by heat treatment at 400 ° C. for about 30 minutes to obtain the planarizing insulating film 44a.

Here, the film thickness of the polyimide precursor at the time of application is set so that the film thickness after the heat treatment becomes approximately the same as the film thickness of the wiring. Further, in order to prevent disconnection of the conductive film in the contact hole during the subsequent conductive film formation, the exposure and development conditions are controlled so that the angle between the bottom surface of the contact hole and the sidewall of the polyimide film is 110 ° C. or more. Is preferred. In this way, on the contact hole formed in the substrate flattened by the polyimide film, one side is 20 μm and the height is 1 μm.
A stud 45a of about 5 μm is formed. The stud is made of the same metal as the wiring material, and can be obtained by the same process as in the above embodiment. Further, an interlayer insulating film 46a made of a polyimide film is formed in the same manner as the step of forming the flattening insulating film.

After the steps from the formation of the wiring layer to this step are repeated twice, the wiring pattern 43c and the planarizing insulating film 44c are formed on the uppermost layer by the same method as in the above embodiment.
A multilayer wiring board is formed as shown in FIG. Further, if necessary, by repeating the steps from the formation of the wiring layer to the interlayer insulation, a multilayer wiring board having a desired number of layers can be obtained.

Incidentally, also in this embodiment, since the polyether compound and the organic sulfur compound are added to the plating solution at a predetermined concentration, the distribution state of carbon, sulfur and oxygen in the width direction of the wiring patterns 43a to 43c. Will be the same as the distribution described above. That is, the concentrations of carbon, sulfur and oxygen in the width direction of the wiring are
Carbon contained in the outer peripheral portion is 1 × 10 ⁻⁴ wt% to 0.1 wt%, sulfur is 3 × 10 ⁻⁴ wt% to 10 wt%, and oxygen is 1
The concentration is in the range of 10 ⁻⁵ wt% to 0.1 wt%, and the high concentration region 49 is 2 in the width dimension of the entire wiring pattern.
It has a size of 0% or less.

FIG. 22 shows the relationship between the wiring width and the wiring thickness when the wiring is formed with a thickness of 15 μm. 5 ppm of a polyether compound and 5 ppm of an organic sulfur compound are added to the electroplating solution in the case of manufacturing the conventional circuit wiring. As shown in FIG. 22, the distribution of the wiring film thickness in the circuit wiring board of the present invention is controlled to 3% or less. It is noteworthy that the wiring film thickness does not increase even when the wiring width is 30 μm or less. On the other hand, the film thickness of the conventional circuit wiring is thicker than 30 μm at the boundary, and on the other hand, the film thickness becomes thin beyond this, and the distribution is about 15%.

As described above, in the circuit wiring board of the present invention, the uniformity of the film thickness on the entire board is significantly improved.
Further, as a result of improving the uniformity of the film thickness, it becomes possible to form a uniform contact hole in the polyimide film regardless of the width of the wiring when the wiring is multi-layered using the polyimide film.

Furthermore, in the heat step for forming the polyimide film, the substrate expands and contracts by heating and cooling, but the copper plating film is homogeneous and has high ductility regardless of its size, so that the occurrence of cracks is controlled. ing.

As a reliability evaluation test, -60 ° C. (5 mi
n) -120 degreeC (5 min), the thermal shock test was done. The result is shown in FIG. From FIG. 10, as compared with the conventional wiring having a structure in which carbon, sulfur, and oxygen are uniformly dispersed and arranged, in the structure in which carbon, sulfur, and oxygen according to the present embodiment are dispersed and arranged in a high concentration in the outer peripheral portion. With respect to the wiring, the occurrence of poor connection was reduced to about 1/2, and it was confirmed that the reliability was improved.

Further, with respect to the circuit wiring board of this example and the conventional circuit wiring board, the connection resistance of the connecting portion between different wiring layers of the multilayer wiring and the shear strength at this portion were measured. Circuit wiring board connection resistance is about 2
It was decreased by 0%, and the shear strength of this part was increased by about 30%.

Therefore, according to this embodiment, it is possible to realize a multilayer circuit wiring board having excellent reliability.

The following Example 8 relates to the third aspect of the present invention.

[Embodiment 8] In this embodiment, a semiconductor device mounting structure is realized by flip-chip mounting the semiconductor device obtained in Embodiment 1 on the circuit wiring board obtained in Embodiment 4. FIG. 11 is a cross-sectional view showing the structure of the semiconductor device mounting structure according to this embodiment.

In addition, Example 4 according to the second aspect of the present invention.
In the above description, the glass epoxy substrate is used for the description in 6, but the circuit wiring board material is not limited to glass epoxy as a matter of course. For example, an alumina substrate may be used, and an AlN substrate, a silicon wafer or the like may be used. It can be used while.

Further, the semiconductor chip mounting connection terminals on the substrate are provided with solder (Pb / S) made of, for example, lead or tin.
n = 40/60) is preferably formed,
It is not particularly limited to this.

The solder may be deposited by electroplating at the substrate manufacturing stage, or may be screen-printed by a known technique, and its forming method is not particularly limited.

The manufacturing process of the semiconductor device mounting structure according to this embodiment will be described below with reference to FIGS. 12 and 13.

First, the semiconductor device A obtained according to the first embodiment is processed according to the fourth embodiment as shown in FIG. 12A by a flip-chip bonder which is a well-known technique for performing alignment using a half mirror. The obtained circuit wiring board B is aligned. Then, as shown in FIG. 12B, the solder layer 7 (third layer) of the bump electrode 8 of the semiconductor device A is formed.
Of the metal layer) and the connection terminal 48 of the circuit wiring board B,
Make mechanical contact. At this time, the circuit wiring board B is held on the stage 58 having a heating mechanism, and Pb / Sn =
It has been preheated to 200 ° C. above the 40/60 melting point in a nitrogen atmosphere.

Further, the semiconductor chip A and the circuit wiring board B
, The semiconductor chip A and the circuit wiring are melted by heating the collet holding the semiconductor chip A to the same temperature as the stage on which the substrate is mounted at 200 ° C. in a nitrogen atmosphere to melt the solder layer 7 of the bump 8. The connection terminal 48 of the board B is temporarily connected electrically and mechanically. Finally, the circuit wiring board on which the semiconductor chip is mounted is passed through a reflow furnace heated to 250 ° C. having a nitrogen atmosphere to realize electrical and mechanical connection. At this time, the self-alignment effect is generated due to the surface tension of the solder, a slight positional deviation generated at the time of mounting is corrected, and the bonding can be performed at an accurate position.

FIG. 12C is a sectional view of the connected semiconductor devices, in which the semiconductor chip A is mounted vertically on the circuit wiring board B.

If necessary, it is also possible to seal a resin, which is a known technique, in the gap formed by the flip-chip mounted semiconductor device and the circuit wiring board. As shown in FIG. 12B, the sealing with the resin is performed by supplying the sealing resin 42 from the dispenser 41 onto the circuit wiring board.

As the encapsulating resin, for example, an epoxy resin containing bisphenol epoxy, an imidazole curing catalyst, an acid anhydride curing agent, and spherical silica filler in a weight ratio of 45 wt% can be used. Also, for example, cresol novolac type epoxy resin (ECON
-195XL; manufactured by Sumitomo Chemical Co., Ltd.) 100 parts by weight, phenol resin 54 parts by weight as curing agent, fused silica 100 parts by weight as filler, benzyldimethylamine 0.5 parts by weight, carbon black 3 as other additive. It is also possible to use an epoxy resin melt obtained by crushing, mixing and melting parts by weight and 3 parts by weight of the silane coupling agent, and the material thereof is not particularly limited. Further, the sealing resin can be arranged so as to extend so as to cover the connection metal up to the periphery of the gap formed by the semiconductor chip A and the circuit wiring board B. By thus extending and arranging, the connection reliability of the semiconductor chip is significantly improved. In FIG. 12 (c),
The cross-sectional block diagram of the resin-sealed semiconductor device is shown.

Further, when the connection reliability of the semiconductor device mounting structure according to the present invention was evaluated, the following results were obtained.

A Pb / S film was formed on the main surface of a 10 mm × 10 mm semiconductor chip used for explaining the method of manufacturing a semiconductor device.
This is a result of evaluating reliability using a sample in which 256 n = 40/60 connection electrodes were formed with a diameter of 100 μmφ and mounted on a circuit wiring board. The case where the connection was opened even at one of 256 pins was regarded as a defect, and the vertical axis shows the cumulative defective rate and the horizontal axis shows the temperature cycle. 10 samples
00, temperature cycle test conditions are (-55 ℃ (30m
in) to 25 ° C (5 min) to 125 ° C (30 min)
It was performed at -25 ° C (5 min)). The result is shown in FIG.

The following can be seen from FIG. That is,
The semiconductor device mounting structure having a structure in which carbon, sulfur and oxygen are not dispersed in the bump electrode and the circuit wiring is 1
Poor connection occurred at 500 cycles and 100% at 2000 cycles. A semiconductor device in which carbon, sulfur, and oxygen are evenly dispersed has improved reliability up to 2500 cycles, but has a defect of 50% at 3000 cycles. These defects were found in the interface between the core material metal and the solder in the bump electrode and in the multilayer wiring connection portion in the circuit wiring board, and all were caused by stress strain.

On the other hand, in the structure according to this embodiment, 3
It was found that defects did not occur up to 500 cycles and the reliability was extremely improved.

Furthermore, the sample according to the present embodiment was tested at 85 ° C. and 85 ° C.
When stored at% RH and V _DD = 5V, the results shown in FIG. 15 were obtained. That is, from FIG. 15, it can be seen from FIG. 15 that a semiconductor device mounting structure having a structure in which carbon, sulfur, and oxygen are not dispersed in bump electrodes and circuit wiring up to the present has a corrosion failure at 500H and a failure of 100H at 1500H. It became%. Further, it can be seen that in a semiconductor device having a structure in which carbon, sulfur, and oxygen are uniformly dispersed, no defects occur up to 2500H and reliability is improved, but defects are 100% at 3000H.

All of these defects were electrical corrosion of the core material metal in the bump electrode, which is copper or nickel or an alloy of copper and nickel, or the circuit wiring.

On the other hand, in the structure according to this embodiment, 3
It was found that no defects occurred up to 000H and the reliability was extremely high.

Therefore, from the above evaluation results, it is understood that the semiconductor device mounting structure according to the present embodiment is a highly reliable mounting structure having excellent resistance to thermal cycles and high temperature and high humidity.

The present invention is not limited to the above embodiments, but can be variously modified without departing from the scope of the invention. For example, the film thickness of the core metal material that is the pillar material or the metal formed as the wiring material is not particularly limited, and can be variously changed.

[0162]

As described above, according to the semiconductor device of the first aspect of the present invention, the interface which comes into contact with the third metal, which is the surface of the second metal layer serving as the pillar material of the bump electrode, is formed. Since carbon, sulfur, and oxygen are dispersed in a higher concentration than in the internal region, the ductility becomes high at the surface portion of the second metal layer where the stress is most concentrated, and it is strong against stress strain. Can be made of various materials. Therefore, it is possible to realize a highly reliable semiconductor device without the metal as the pillar material being destroyed as in the past.

In particular, when a metal material containing 50% by weight or more of copper or nickel is used as the second metal layer,
This constituent material has low ductility until now, and it has been difficult to secure sufficient reliability against stress strain. However, according to this aspect, carbon, sulfur, and oxygen are not generated near the surface of the second metal layer. Since the region in which the concentration is higher than that of the internal region is formed, the ductility is significantly improved.

Particularly, in the high concentration dispersion region of the second metal layer, carbon is 1 × 10 ⁻⁴ wt% to 0.1 wt%, and sulfur is 3 wt%.
× 10 ^-4 wt% to 10 wt%, oxygen is 1 x 10 ^-5 wt%
To 0.1% by weight, and the thickness of the high-concentration dispersion region is set to 20% or less of the maximum dimension in the vertical cross section of the second metal layer, thereby significantly improving reliability. Is possible.

Further, according to the semiconductor device of the second aspect of the present invention, the surface region of the circuit wiring has a structure in which carbon, sulfur and oxygen are dispersed at a higher concentration than the internal region. Therefore, the strength against the stress strain on the surface of the circuit wiring is improved, and the defect in the circuit wiring caused by the stress strain caused by the temperature cycle can be prevented.

In particular, when a metal material containing 50% by weight or more of copper or nickel is used for the circuit wiring, this constituent material has low ductility until now, and sufficient reliability against stress strain must be ensured. However, according to this aspect, there is a region in which carbon, sulfur, and oxygen are dispersed in a higher concentration than the internal region in the vicinity of the surface of the circuit wiring. It has a significantly improved effect.

In particular, the high concentration dispersion area of the circuit wiring is
1 × 10 ⁻⁴ wt% to 0.1 wt% carbon, 3 × 1 sulfur
0 ^-4 wt% to 10 wt%, oxygen is 1 x 10 ^-5 wt%
By setting it to 0.1% by weight, the thickness of the high-concentration dispersion region is set to 2 times the maximum dimension in the vertical cross section of the second metal layer.
By setting the size to 0% or less, the reliability can be significantly improved.

Further, the circuit wiring according to the second aspect of the present invention is the circuit wiring which constitutes the multilayer circuit wiring board, the via metal which interconnects the circuit wiring, or the metal for component terminals which is mounted on the circuit wiring board. It is possible to prevent the open defect in the via part, which has been a problem until now, when the multilayer circuit wiring is configured, and it is possible to prevent the occurrence of cracks in the external terminal, which improves reliability. It is possible to realize a semiconductor device having high cost.

Further, according to the third aspect of the present invention, at least one of the semiconductor device and the circuit wiring board, that is,
By providing a high concentration dispersion layer on the second electrode surface of the bump electrode of the semiconductor device, or by providing a high concentration dispersion layer on the circuit wiring surface of the circuit wiring board, or by providing a high concentration dispersion layer on both of them. Thus, it is possible to realize a semiconductor device mounting structure having high reliability.

Furthermore, the metal material constituting the semiconductor device, the circuit wiring board, and the semiconductor device mounting structure according to the first to third aspects of the present invention is a region in which carbon, sulfur and oxygen are arranged in high concentration. Since it has an outer peripheral portion, it is possible to prevent corrosion against the intrusion of moisture, and the structure has extremely high reliability.

Therefore, by using the semiconductor device, the circuit wiring board, and the semiconductor device mounting structure according to the first to third aspects of the present invention, semiconductors can be densely formed as compared with the case of using the conventional technique. It becomes possible to mount the chip with high reliability.

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first aspect of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 4 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 5 is a diagram showing an electroplating apparatus for manufacturing a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view showing a circuit wiring board according to a second aspect of the present invention and a diagram showing distributions of carbon concentration, sulfur concentration, and oxygen concentration in the cross section.

FIG. 7 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 8 is a cross-sectional view showing a manufacturing process of the semiconductor device shown in FIG.

FIG. 9 is a cross-sectional view showing another example of the circuit wiring board according to the second aspect of the present invention.

FIG. 10 is a characteristic diagram showing the results of reliability evaluation tests of the circuit wiring board according to the second aspect of the present invention and the conventional circuit wiring board in comparison.

FIG. 11 is a sectional view showing a semiconductor device mounting structure according to a third aspect of the present invention.

12 is a cross-sectional view showing a manufacturing process of the semiconductor device mounting structure shown in FIG.

13 is a cross-sectional view showing the manufacturing process of the semiconductor device mounting structure shown in FIG.

FIG. 14 is a characteristic diagram showing a comparison of the results of reliability evaluation tests of the semiconductor device mounting structure according to the third aspect of the present invention and the conventional semiconductor device mounting structure.

FIG. 15 is a characteristic diagram showing the results of reliability evaluation tests of the semiconductor device mounting structure according to the third aspect of the present invention and the conventional semiconductor device mounting structure for comparison.

FIG. 16 is a cross-sectional view for explaining a conventional technique.

FIG. 17 is a cross-sectional view for explaining a conventional technique.

FIG. 18 is a sectional view for explaining a conventional technique.

FIG. 19 is a cross-sectional view for explaining a conventional technique.

FIG. 20 is a sectional view for explaining a conventional technique.

FIG. 21 is a diagram for explaining a conventional technique.

FIG. 22 is a characteristic diagram showing the relationship between the wiring width and the wiring thickness in comparison between the present invention and the prior art.

[Explanation of symbols]

1 ... Semiconductor chip 2 ... Bonding pad 3 ... passivation film 4 ... First metal layer 5 ... second metal layer 6 ... High concentration region in bump electrode 7 ... Third metal layer 8 ... Bump electrode 11, 12, 31 ... Plating resist 21 ... Circuit wiring board 22 ... Adhesive metal 23 ... Circuit wiring 24 ... High concentration area 27 ... Etching resist 41 ... Glass epoxy substrate 42 ... Cu / Ti laminated film 43a, 43b, 43c ... Wiring pattern 44a, 44b, 44c ... Insulating film for planarization 45a, 45b ... Via stud 46a, 46b ... Interlayer insulating film 48 ... External connection terminal 50 ... Plating layer 51 ... Anode plate 52 ... Anode pin 53 ... Cathode pin 54 ... Cathode electrode 55 ... Anode electrode

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI H01L 21/92 603A (56) References JP-A-7-231151 (JP, A) JP-A-5-152376 (JP, A) JP-A-9-205096 (JP, A) JP-A-9-129648 (JP, A) JP-A-9-129647 (JP, A) JP-A-8-45939 (JP, A) JP-A-10-261642 (JP, A) JP-A-7-211722 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01K 21/60 H01L 21/60 311 B23K 35/22 310 H05K 1/09

Claims (12)

(57) [Claims] 1. A semiconductor chip, a bonding pad formed on the semiconductor chip, and a bump electrode formed on the bonding pad, wherein the bump electrode is formed on the bonding pad. A metal layer, a second metal layer disposed on the first metal layer,
And this is formed on the second metal layer, a third metal layer to be connected to the circuit wiring board, near the interface of the second metal layer is in contact with the third metal layer, A semiconductor device having a high-concentration region in which at least one selected from the group consisting of carbon, sulfur, and oxygen is dispersed at a higher concentration than in the internal region of the second metal layer. 2. The semiconductor device according to claim 1, wherein the second metal layer is made of a metal material containing 50% by weight or more of copper, nickel, or an alloy thereof. 3. The high concentration region of the second metal layer is 1 ×
10 ⁻⁴ wt% to 0.1 wt% carbon, 3 × 10 ⁻⁴ wt%
-10 wt% sulfur, and 1 x 10 ^-5 wt% -0.1
3. The semiconductor device according to claim 1, which contains at least one selected from the group consisting of oxygen by weight. 4. The high-concentration region of the second metal layer is the second
4. The semiconductor device according to claim 1, wherein the thickness of the metal layer is 20% or less of the maximum dimension in the vertical cross section. 5. A circuit wiring board having circuit wiring on at least one of the surface of the substrate and the inside of the substrate, wherein the surface of the circuit wiring has a group consisting of carbon, sulfur, and oxygen rather than an internal region thereof. A circuit wiring board having a high-concentration region in which at least one selected from the above is dispersed at a high concentration. 6. The circuit wiring board according to claim 5, wherein the circuit wiring is made of a metal material containing 50% by weight or more of copper, nickel, or an alloy thereof. 7. The high concentration region of the circuit wiring is 1 × 10.
^-4 wt% to 0.1 wt% carbon, 3 x 10 ^-4 wt% to 1
7. The circuit wiring according to claim 5, which contains at least one selected from the group consisting of 0% by weight of sulfur and 1 × 10 ⁻⁵ % by weight to 0.1% by weight of oxygen. substrate. 8. The high-concentration region of the circuit wiring has a thickness that is 20% or less of a maximum dimension in a vertical cross section of the circuit wiring. Circuit wiring board. 9. The circuit wiring is at least selected from the group consisting of multi-layer circuit wiring provided in multiple layers on a substrate, a via metal interconnecting the circuit wiring, and a component connecting metal terminal mounted on the substrate. Contracts characterized by being one type
9. The circuit wiring board according to any one of claims 5 to 8. 10. The semiconductor device according to claim 1 is flip-chip mounted on a circuit wiring board having circuit wiring on at least one of the surface of the substrate and the inside of the substrate. A characteristic semiconductor device mounting structure. 11. A semiconductor chip, a bonding pad formed on the semiconductor chip, and a bump electrode formed on the bonding pad, the bump electrode being a first electrode formed on the bonding pad. metal layer, the first second metal layer disposed on the metal layer, and formed on the second metal layer, a semiconductor having a third metal layer to be connected to the circuit wiring board A semiconductor device mounting structure, wherein the device is flip-chip mounted on the circuit wiring board according to any one of claims 5 to 9. 12. The semiconductor device according to any one of claims 1 to 4 is flip-chip mounted on the circuit wiring board according to any one of claims 5 to 9. Semiconductor device mounting structure.