JPH09160834A - Computer using falsh memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To remove a data bit error phenomenon and to improve the reliability at operation program execution time by an inexpensive means by ANDing data of two operation programs and using the AND result for an operation program to be run. SOLUTION: The same data are written in a flash memory 2a and a flash memory 2b in advance and a CPU 1 when reading the data out of the flash memory 2a reads the data out of the flash memory 2b at the same time and an AND circuit 6 ANDs the data of the two operation programs read out of the two flash memories 2a and 2b, so that the AND result is used for the operation program to be run. Consequently, a data bit error phenomenon that the flash memory 2a or 2b has can be removed from the read data and the reliability of operation program execution can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer using a flash memory for detecting data bit corruption of an operation program of a central processing unit stored in the flash memory.

[0002]

2. Description of the Related Art FIG. 8 is a block diagram of a computer using a conventional flash memory disclosed in, for example, Japanese Patent Laid-Open No. 6-199339, in which 1 is a central processing unit (hereinafter (Referred to as CPU) 2 is a flash memory in which an operation program of the CPU 1 is stored and which can be collectively erased and written. 3 is a writing circuit for writing the operation program in the flash memory 2, 4 is a writable memory (hereinafter referred to as RAM) provided for executing the operation program, and 5a and 5b are peripherals such as an external storage device. It is a peripheral device control unit that controls the device.

Next, the operation will be described. Generally, a computer has a CPU and a memory that stores an operation program of the CPU. Previously, a read-only memory (hereinafter referred to as a ROM) that cannot be electrically erased was used as a memory for storing the operation program. However, once the operation program is stored in the ROM, the ROM itself is replaced when the operation program is replaced. Had to do. Therefore, as a memory for storing the operation program, a flash memory 2 that can be collectively erased and written in a batch is often used. The writing circuit 3 is a circuit for applying a voltage to the writing terminal of the flash memory 2 to enable writing.

[0004]

Since the conventional computer using the flash memory is constructed as described above,
The flash memory 2 is often used as a memory for storing the operation program of the CPU 1. However, recently, it has been reported that the data bit garbled phenomenon in which the written data "0" spontaneously volatilizes to "1" occurs in the flash memory 2 with a certain probability. When data bits are garbled in the operation program stored in the flash memory 2, the CPU 1 runs out of control, resulting in a malfunction. Further, an error correction circuit can be used as a countermeasure when the data bit of the flash memory 2 is garbled, but there is a problem that the computer becomes expensive because the circuit is expensive.

Further, since there is no means for easily knowing that the data bit garbled of the flash memory 2 has occurred, when an operation failure occurs due to the data bit garbled of the flash memory 2, it takes a lot of time to restore the normal operation. Therefore, even if it is found that the data bit corruption of the flash memory 2 has occurred, the correct operation program must be manually stored again in the flash memory 2 as a means for correcting the data bit corruption of the flash memory 2. Therefore, there is a problem that it takes a lot of time to store the operation program.

Further, the flash memory 2 deteriorates depending on the number of times of erasing and writing and environmental conditions, and the probability of occurrence of a data bit garbled phenomenon in which written data spontaneously volatilizes increases, but since there is no means to know the deterioration, There is also a problem that it is difficult to prevent malfunction of the flash memory 2 due to garbled data bits.

The present invention has been made in order to solve the above problems, and a flash memory which improves the reliability at the time of executing an operation program by an inexpensive means even if there is a data bit garbled phenomenon of the flash memory. The purpose is to obtain the calculator used.

[0008]

A computer using a flash memory according to a first aspect of the present invention stores the same operation program of the central processing unit in two flash memories, respectively, and the central processing is performed from the two flash memories. The logical product of the data of the two operating programs read according to the command of the device is obtained by the logical product circuit, and the result of the logical product is used as the operating program to be executed.

A computer using a flash memory according to a second aspect of the present invention stores the same operation program of the central processing unit in each of the two flash memories, and the two flash memories respond to a command from the central processing unit. When the exclusive OR circuit of the read data of the two operation programs is taken by the exclusive OR circuit and the difference of the data is detected by the exclusive OR circuit, the data of the operation program is stored. The address is recorded in the recording circuit.

In a computer using a flash memory according to a third aspect of the present invention, the central processing unit reads the address recorded in the recording circuit during the idle time of the process, and
The write circuit is instructed to correct erroneous data stored in the addresses of the operation programs of the two flash memories.

A computer using a flash memory according to a fourth aspect of the present invention stores the same operation program of the central processing unit in each of the two flash memories, and the two flash memories respond to a command from the central processing unit. The exclusive OR of the read data of the two operation programs is taken by the exclusive OR circuit, and the number of times when the difference of the data is detected by the exclusive OR result is counted by the counting circuit, and the counted value is a predetermined value. When it reaches, the central processing unit is caused to perform an interrupt process to notify the deterioration of the flash memory.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. 1 is a block diagram showing a computer using a flash memory according to a first embodiment of the present invention. In the figure, 1 is a CPU (central processing unit) that controls the entire computer, and 2a and 2b are two batch erasable and writable flash memories in which the same operation program of the CPU 1 is stored. 3a and 3b are write circuits for writing the operation program in the flash memories 2a and 2b, 4 is a RAM (writable memory) provided for executing the operation program, and 5a and 5b are peripherals such as an external storage device. It is a peripheral device control unit that controls the device.
Reference numeral 6 denotes a logical product circuit which calculates the logical product of the data of the two operating programs read from the two flash memories 2a and 2b in response to the instruction of the CPU 1 and uses the logical product result as the operating program to be executed. Reference numeral 7 is a control circuit for switching the AND circuit 6 to the input state in response to the above command from the CPU 1.

Further, FIG. 2 shows two flash memories 2
When data bit garbling occurs in one of the flash memories 2a, 2b
It is a truth diagram of the data read from b and the data originally expected.

Next, the operation will be described. In the flash memories 2a and 2b, all the bits are "1" before writing, and writing is performed by writing "0" in a necessary portion. However, it has recently been reported that a data bit garbled phenomenon in which written data "0" naturally volatilizes to "1" occurs in a flash memory with a certain probability. The data bit garbled phenomenon is always caused by a change from "0" to "1".
In FIG. 2, when the garbled data "0" → "1" in the flash memory 2a occurs, the data in the flash memory 2b is "0", and the read data "1" from the flash memory 2a and the data read from the flash memory 2b are read. The product of read data '0' is '0', which is in agreement with the correct expected data. In addition, when the garbled data “0” → “1” of the flash memory 2b occurs, the flash memory 2
The data of a is "0", and the product of the read data "0" from the flash memory 2a and the read data "1" from the flash memory 2b is "0", which matches the correct expected data.

As described above, according to the first embodiment, the same data is written in the flash memory 2a and the flash memory 2b in advance, and when the CPU 1 reads the data from the flash memory 2a, the flash memory 2b reads the data. By reading the data at the same time and taking the product of the read data from the two flash memories 2a and 2b in the logical product circuit 6, the data bit garbled phenomenon of the flash memory 2a or 2b is removed from the read data, and the operation program is executed. There is an effect that the reliability of can be improved.

Embodiment 2 3 is a block diagram showing a computer using a flash memory according to a second embodiment of the present invention. In the figure, 8 is two flash memories 2
An exclusive OR circuit for obtaining the exclusive OR of the data of the two operation programs read from a and 2b according to the command of the CPU 1 and detecting the difference in the data, and 9 is the exclusive OR result of the difference in the data. The recording circuit 10 records the address where the data of the operation program is stored, when 10 is detected, and is a selection circuit which is selected by the instruction of the CPU 1 during the idle time of the processing of the CPU 1 and turns on the circuit. is there. In the second embodiment, the CPU 1 reads the address recorded in the recording circuit 9 in the idle time of the process, and the two flash memories 2a,
The write circuits 3a and 3b are instructed to correct erroneous data stored in the address of the operation program 2b. Other configurations are the same as those of the first embodiment shown in FIG. 1, and thus redundant description will be omitted.

Further, FIG. 4 is a flow chart showing a procedure of detection of occurrence of data bit garbled, address recording and data correction when data bit garbled occurs, and FIG. 5 shows data bit garbled in one of two flash memories. FIG. 6 is a truth diagram showing data read from two flash memories and modified data when they occur.

Next, the operation will be described. In FIG. 4, after occurrence of data bit garbled (step ST1), C
When the data read from the PU1 is garbled (step ST2), the exclusive OR of the read data from the two flash memories 2a and 2b is obtained by the exclusive OR circuit 8 (step ST2).
3) If they match, the operation returns to the normal operation (step ST4). If they do not match, the address of the unmatched portion is recorded in the recording circuit 9 (step ST5).

Further, the CPU 1 reads the address recorded in the recording circuit 9 through the selection circuit 10 in the idle time of the processing, further reads the data of the two flash memories 2a and 2b stored at the address, and reads the two data. Bits with different data in the flash memories 2a and 2b
By surely correcting to "0" based on the command to the write circuits 3a and 3b (step ST6), the data bit can be easily corrected without executing complicated calculation, and the flash memories 2a and 2b can be easily corrected. The time to store the correct program again can be saved.

As described above, according to the second embodiment, of the data written in the two flash memories 2a and 2b, the garbled address of the data bit is automatically recorded in the recording circuit 9. Memory 2a,
When the data bit of 2b becomes garbled and malfunction occurs,
Recovery work can be facilitated. Further, there is an effect that the data bit of the address of the location where the garbled data bit of the flash memories 2a and 2b is recorded can be automatically corrected in the idle time of the processing of the CPU 1.

Embodiment 3 6 is a block diagram showing a computer using a flash memory according to a third embodiment of the present invention. In the figure, 11 counts the number of times that the exclusive OR result by the exclusive OR circuit 8 detects a difference in data, and when the predetermined value is reached, causes the CPU 1 to perform an interrupt process to deteriorate the flash memories 2a and 2b. This is a counter (counting circuit) for notifying. Other configurations are the same as those of the first embodiment shown in FIG. 1, and thus redundant description will be omitted.

Next, the operation will be described. FIG. 7 is a flow chart showing a detection procedure of data bit garbled occurrence, address recording, and a count procedure of data bit garbled occurrence, when the CPU 1 reads data from the flash memory 2a. Read data at the same time (step ST
2) By detecting the exclusive OR of the read data from the two flash memories 2a and 2b by the exclusive OR circuit 8 (step ST3), the data mismatch is detected.

The number of times this data does not match is counted by the counter 11 (step ST7). CPU
1 resets the counter 11 in a pre-registered time period (step ST8), but when the count number reaches the pre-registered 20 times (step ST8) (step ST8).
9), the CPU 1 is interrupted (step ST1
0), the CPU 1 activates the abnormality processing (step ST1
1) It is possible to notify the outside that the frequency of garbled data bits is high.

[0024]

As described above, according to the first aspect of the invention, the same operation program is stored in the two flash memories, and the logical product of the data of the two operation programs read from the two flash memories is obtained. Is configured by the logical product circuit and the logical product result is used as the operation program to be executed. Therefore, the data bit garbled phenomenon of the flash memory is removed from the read data to reduce the reliability when the operation program is executed. There is an effect that can be improved by means.

According to the second aspect of the present invention, the same operation program is stored in two flash memories,
When the exclusive OR circuit takes the exclusive OR of the data of the two operation programs read from one flash memory, and the result of the exclusive OR detects the difference of the data, the data of the above operation program is Since the stored address is recorded in the recording circuit, there is an effect that the recovery work can be facilitated by an inexpensive means when the malfunction occurs due to the garbled data bit of the flash memory.

According to the third aspect of the present invention, the central processing unit reads the address recorded in the recording circuit in the idle time of the processing, and reads the address stored in the address of the operation program of the two flash memories. Since it is configured to correct erroneous data, there is an effect that it is possible to save the time for storing the correct operation program in the flash memory again when the data bit of the flash memory is garbled.

According to the invention described in claim 4, the same operation program is stored in two flash memories,
The exclusive OR circuit of the data of the two operation programs read from one flash memory is taken by the exclusive OR circuit, and the counting circuit counts the number of times that the exclusive OR result detects the difference in the data, and the total is calculated. Since the central processing unit is configured to cause an interrupt process when the numerical value reaches a predetermined value, an abnormal process of the central processing unit is activated by an interrupt to notify the deterioration of the flash memory to notify the deterioration of the flash memory. This has the effect of preventing malfunctions due to garbled data bits.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a computer using a flash memory according to a first embodiment of the present invention.

FIG. 2 is a truth diagram of data read from two flash memories and originally expected data when data bit garbling occurs in one of the two flash memories.

FIG. 3 is a configuration diagram showing a computer using a flash memory according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing a procedure for detecting occurrence of data bit corruption, address recording, and data correction when data bit corruption occurs.

FIG. 5 is a truth diagram showing data read from two flash memories and corrected data when data bit garbling occurs in one of the two flash memories.

FIG. 6 is a configuration diagram showing a computer using a flash memory according to a third embodiment of the present invention.

FIG. 7 is a flowchart showing a detection procedure of data bit garbled occurrence, address recording, and a count procedure of data bit garbled occurrence when the data bit garbled occurs.

FIG. 8 is a configuration diagram showing a computer using a conventional flash memory.

[Explanation of symbols]

1 CPU (central processing unit), 2a, 2b flash memory, 3a, 3b write circuit, 4 RAM (writable memory), 6 AND circuit, 8 exclusive OR circuit,
9 recording circuit, 11 counter (counting circuit).

Claims (4)

[Claims] 1. A flash memory in which the same operation program of a central processing unit is stored and which can be collectively electrically erased and written, a write circuit for writing the operation program in the two flash memories, and the operation program. The writable memory provided for execution and the logical product of the data of the two operation programs read from the two flash memories according to the instruction of the central processing unit are ANDed, and the logical product result is executed. A computer using a flash memory provided with an AND circuit as an operation program. 2. A flash memory in which the same operation program of the central processing unit is stored and which can be collectively electrically erased and written, a write circuit for writing the operation program in the two flash memories, and the operation program A writable memory provided for execution and an exclusive OR for detecting data difference between two operation programs read from the two flash memories in response to a command from the central processing unit. A computer using a flash memory including a logical OR circuit and a recording circuit that records an address where the data of the operation program is stored when the exclusive OR result detects a difference in data. 3. The central processing unit reads the address recorded in the recording circuit during the idle time of the processing, and corrects the incorrect data among the data stored at that address in the operation programs of the two flash memories. The computer using the flash memory according to claim 2, wherein the writing circuit is instructed. 4. A flash memory in which the same operation program of the central processing unit is stored and which can be collectively erased and written, a write circuit for writing the operation program in the two flash memories, and the operation program A writable memory provided for execution and an exclusive OR for detecting data difference between two operation programs read from the two flash memories in response to a command from the central processing unit. The logical OR circuit and the number of times the exclusive OR result detects a difference in data are counted, and when the count value reaches a predetermined value, the central processing unit is caused to perform an interrupt process to prevent the deterioration of the flash memory. A computer using a flash memory equipped with a notification counting circuit.