JPH1011284A - Controlled storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a controlled storage device capable of being switched to an alternate storage at the time of accessing a 1-bit error frequently occurring place by providing the alternate storage of this place. SOLUTION: The controlled storage device is provided with a register file 11 storing a 1-bit error generating address, a register file 16 counting the number of error occurring times to store the address of not less than prescribed number of times, a register file 23 storing the alternate address of this address, a comparator group 17 and a logic circuit 20 comparing an access address and the error occurring address with respect to the controlled storage device to switch to the alternate address, and a storing area indicated by the alternate address in a specific area in a controlled storage part 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control storage device for storing control data such as a microprogram.
In particular, the present invention relates to a control storage device in which a storage location indicated by a 1-bit error frequent address is replaced with a register file.

[0002]

2. Description of the Related Art According to Japanese Patent Application Laid-Open No. 58-169254, which is a conventional error processing method for a control storage device, when an uncorrectable error occurs in a control storage device, the SVP is notified.
The data at the erroneous address read from the external storage device by the SVP is replaced with data stored in the external storage device, and when an uncorrectable error occurs at the same address thereafter, the data is replaced with the data in the external storage device. Is disclosed.

According to Japanese Patent Application Laid-Open No. 58-225445, the holding means holds the corrected data for which a correctable error has been detected from the data storage device and its address, and when the same address is accessed next time, An error processing method is disclosed in which correction data is read from a holding unit and written back to a data storage device to improve data processing speed.

In a control storage device, 1-bit error correction,
There is a known one that employs an error correction code for 2-bit error detection. With the adoption of a large-capacity and highly-integrated random access memory in the control storage device, the frequency of occurrence of intermittent errors increases, and the frequent occurrences of 1-bit errors become 2-bit errors that cannot be corrected. The likelihood of failure is increasing. In the above publication, 1
No effective measures have been taken to prevent an increase in the possibility that a bit error location will generate an error of two or more bits.

[0005]

According to the above-mentioned prior art, the first problem is to prevent a two-bit error from occurring at a place where one-bit errors occur frequently and causing a fatal system failure. There is a measure.

[0006]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a control storage device having a switching memory for providing an alternative storage for a location where a 1-bit error frequently occurs and accessing the alternative storage when the location is accessed. In a control storage device having an error correction function of read control data according to the present invention, a control storage unit for storing the control data, a first register file for holding an address of the control storage unit in which a 1-bit error has occurred, and A logic circuit for counting the number of occurrences of the 1-bit error, a second register file for holding an address at which the number of occurrences of the 1-bit error is equal to or greater than a predetermined number, and the address held in the second register file A third register file holding the alternative address of the third register file and a fourth register pointed to by the alternative address. A register file, when an address for accessing the control storage unit coincides with the address held in the second register file, an address switching circuit for switching said address to said alternative address,
A register file read / write circuit for reading / writing control data from / to a fourth register pointed to by the alternative address, and causing a one-bit error frequently occurring place in the control storage unit to be replaced with a fourth register file pointed to by the alternative address. It is characterized by the following.

Further, the fourth register file is a specific area of the control storage unit.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

Referring to FIG. 1 showing the configuration of one embodiment of the present invention, a control storage device includes an address register 1 for storing an access address, a control storage unit 2 for storing control data, and a control storage unit 2. 1-bit error correction circuit 3 for correcting a 1-bit error in read control data
A data register 4 for temporarily storing read control data, a 1-bit error detection circuit 5 for detecting the occurrence of a 1-bit error in the control data of the data register 4, and a write output from the 1-bit error detection circuit 5. A register 6 for holding the enable signal (WE) for a certain timing, an add register 7 for temporarily holding an address while detecting a 1-bit error, a register 8 for storing the number of errors, and a 1-bit error detection circuit 5 When a 1-bit error is detected, a logic circuit 9 of a counter that counts up the register 8 by +1 and an AND circuit 1 that gates the address of the address register 7 where the 1-bit error is detected
0, a register file 11 for sequentially storing the addresses in the address of the logic circuit 9, a comparator group 12 for comparing the error address of the register file 11 with the error address of the AND circuit 10, and a match detected by the comparator group 12. A logic circuit 13 for detecting whether or not the number of the same error addresses exceeds a certain value, a register file 16 for storing the addresses in which the logic circuit 13 has made an error more than a certain number of times, and counting the number of the addresses. Register 14 and logic circuit 15 and register file 1
A comparator group 17 for detecting the coincidence of the address of the address register 6 with the address of the address register 1, and a selection circuit 19 for selecting an address of the address register 1 or an alternative address with an output obtained by performing an OR operation on the output of the comparator group 17 with an OR circuit 18 A logic circuit 20 for designating an alternative address by the output of the comparator group 17, a register 21 for generating an alternative address for an error address of a certain number of times or more, and a logic circuit 2
2 and a register file 23 for storing an alternative address
And.

Next, the operation of this embodiment will be described.

At the time of read scanning, the number of errors at the address where a 1-bit error has occurred does not exceed a predetermined value, so that the same address as that of the address register 1 does not exist in the register file 16. The selector 19 selects the address data of the address register 1. At the time of normal operation, the address selected by the selector 19 is stored in the address register 7, and at the same time, the data of the address is read from the control storage unit 2 and stored in the data register 4. In the data read from the data register 4, a one-bit error is detected by a one-bit error detection circuit 5, and the one-bit error is corrected by a one-bit error correction circuit 5. The write enable signal WE of the control storage unit 2 output from the one-bit error detection circuit 5 is
The 1-bit error is corrected by the above, and is held in the timing register 6 during the rewriting timing. The register file 11 contains the address (W) created by the logic circuit 9.
In A), the address of the address register 7 when the 1-bit error detection circuit 5 detects a 1-bit error is written.

The register file 11 holds addresses where a 1-bit error has occurred in the past. The comparator 12 and the logic circuit 13 compare the address of the address register 7 with the address of the register file 11 by the comparator group 12 to find out which address has generated a 1-bit error and how many times the address has occurred.
1 can be detected.
The address at which the 1-bit error read from the register file 11 has occurred a predetermined number of times or more is written to the address of the register file 16 specified by the logic circuit 15. Further, the substitute address created by the logic circuit 22 is stored in the address of the register file 23 designated by the logic circuit 15. The address stored in the register file 16 indicates an address where a 1-bit error has occurred a predetermined number of times or more in the control storage unit 2. Register file 1
When the same address as the address stored in the address register 6 is read from the address register 1, an access is made to a specific area of the control storage unit 2 indicated by the substitute address stored in the register file 23 corresponding to the address.

[0013]

As described above, the effect of the present invention is to prevent the occurrence of a non-correctable error by providing an alternative storage location for a location in the control storage unit where correction-correctable errors frequently occur.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Address register 2 Control storage part 3 1-bit error correction circuit 4 Data register 5 1-bit error detection circuit 6 Timing register 7 Address register 8 Register 9 Logic circuit 10 AND circuit 11 Register file 12 Comparator group 13 Logic circuit 14 Register 15 Logic circuit 16 Register File 17 Comparator Group 18 OR Circuit 19 Selector 20 Logic Circuit 21 Register 22 Logic Circuit 23 Register File

Claims (2)

[Claims] 1. A control storage device having an error correction function for read control data, a control storage unit for storing the control data, and a first register for holding an address of the control storage unit in which a 1-bit error has occurred. A file, a logic circuit that counts the number of occurrences of the 1-bit error, a second register file that holds an address where the number of occurrences of the 1-bit error is equal to or greater than a predetermined number, and a second register file that holds the address. A third register file for holding an alternative address of the address, a fourth register file including a fourth register indicated by the alternative address, and an address for accessing the control storage unit held in a second register file When the address matches
An address switching circuit that switches the address to the alternative address; and a register file read / write circuit that reads / writes control data to / from a fourth register pointed to by the alternative address. A control storage device, wherein a fourth register file indicated by the substitute address is substituted. 2. The control storage device according to claim 1, wherein the fourth register file is a specific area of the control storage unit.