JPH09107028A - Element isolation method for semiconductor device - Google Patents
Element isolation method for semiconductor deviceInfo
- Publication number
- JPH09107028A JPH09107028A JP8225456A JP22545696A JPH09107028A JP H09107028 A JPH09107028 A JP H09107028A JP 8225456 A JP8225456 A JP 8225456A JP 22545696 A JP22545696 A JP 22545696A JP H09107028 A JPH09107028 A JP H09107028A
- Authority
- JP
- Japan
- Prior art keywords
- trench
- pattern
- element isolation
- polishing
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims description 23
- 238000005498 polishing Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000011810 insulating material Substances 0.000 claims abstract description 15
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000005299 abrasion Methods 0.000 claims abstract 4
- 239000000126 substance Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 2
- 239000002184 metal Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 31
- 150000004767 nitrides Chemical class 0.000 abstract description 7
- 239000012212 insulator Substances 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 31
- 238000010586 diagram Methods 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 230000002159 abnormal effect Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体装置の製造方
法に係り、特にトレンチに埋め立てられた素子分離層の
平坦度を改善し得る半導体装置の素子分離方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for element isolation of a semiconductor device capable of improving the flatness of an element isolation layer buried in a trench.
【０００２】[0002]
【従来の技術】半導体素子の高集積化によりパターン密
度が高くなり、且つ素子の間隔も縮まっている。これに
より、従来の素子分離方法である局部的酸化による素子
分離方法（LOCal Oxidation of Silicon: ＬＯＣＯＳ）
のような方法では素子間の電気的分離を十分に達成し得
ない。2. Description of the Related Art Due to the high integration of semiconductor devices, the pattern density is increasing and the distance between the devices is decreasing. Thus, a conventional element isolation method (LOCal Oxidation of Silicon: LOCOS) by local oxidation is used.
Such a method cannot sufficiently achieve electrical isolation between elements.
【０００３】かかるＬＯＣＯＳの問題点を改善するため
の方法としてＳＴＩ(Shallow Trench Isolation）方法
が注目されている。このＳＴＩ方法は半導体基板にトレ
ンチを形成し、ここに酸化物のような絶縁物質を埋め立
てる方法である。ＳＴＩ方法は、素子分離膜の形成にお
いて前記ＬＯＣＯＳ類のように熱酸化工程に依らないの
で、熱酸化工程によるＬＯＣＯＳ類の短所をある程度減
らすことができる。さらに、技術的にトレンチの深さを
調節することにより１Ｇ ＤＲＡＭ級以上の高集積化に
必要な０．２μｍ以下の幅の寸法を有する素子分離層の
形成が可能となった。An STI (Shallow Trench Isolation) method has been attracting attention as a method for improving the problem of LOCOS. The STI method is a method of forming a trench in a semiconductor substrate and filling an insulating material such as an oxide therein. Since the STI method does not depend on the thermal oxidation process like the LOCOS in forming the element isolation film, the disadvantages of the LOCOS due to the thermal oxidation process can be reduced to some extent. Further, by technically adjusting the depth of the trench, it becomes possible to form an element isolation layer having a width dimension of 0.2 μm or less, which is necessary for high integration of 1 G DRAM class or higher.
【０００４】トレンチに絶縁物質を埋め立てるために、
トレンチの形成されている半導体基板上に絶縁物質を均
一に蒸着させる。その結果、トレンチを形成しない領域
でも絶縁膜が蒸着される。したがって、望まない領域に
蒸着された絶縁物質を取り除かなければならなく、この
ために多様な方法が試みられている。そのうち最も有力
な方法が化学的−機械的研磨（Chemical Mechanicl Pol
ishing: 以下、ＣＭＰと称する）である。To fill the trench with insulating material,
An insulating material is uniformly deposited on the semiconductor substrate in which the trench is formed. As a result, the insulating film is deposited even in the region where the trench is not formed. Therefore, the insulating material deposited on the undesired areas must be removed, and various methods have been tried for this purpose. The most powerful method is chemical-mechanical polishing (Chemical Mechanicl Pol
ishing: hereinafter referred to as CMP).
【０００５】このＣＭＰ方法は、ＣＭＰに強い耐研磨層
を半導体基板上に形成した後、半導体基板にトレンチを
形成し、トレンチの形成された結果物上に絶縁層を蒸着
したのち、耐研磨層が露出されるまで絶縁物質に対して
ＣＭＰを施す。このＣＭＰ工程は半導体基板に形成され
た絶縁物を横方向に取り除くので、トレンチの埋立及び
食刻方法として理想的なものと見なされる。In this CMP method, a polishing resistant layer resistant to CMP is formed on a semiconductor substrate, a trench is formed in the semiconductor substrate, an insulating layer is deposited on the resultant product in which the trench is formed, and then the polishing resistant layer is formed. CMP the insulating material until exposed. This CMP process laterally removes the insulator formed on the semiconductor substrate, and is considered to be an ideal method for filling and etching the trench.
【０００６】しかしながら、ＣＭＰ工程の研磨率は絶縁
層の高さ、耐研磨層の密度に対して敏感に変化し、この
ためＣＭＰ後絶縁層の平坦度が非常に劣化する問題があ
る。特に、トレンチの幅が数ｍｍ程度に大きくなると、
ＣＭＰ後絶縁層の中央部が皿状になるディッシング現象
が発生して不安定な素子分離特性及び段差を引き起こす
問題がある。However, the polishing rate in the CMP process is sensitive to the height of the insulating layer and the density of the polishing-resistant layer, which causes a problem that the flatness of the insulating layer after CMP is extremely deteriorated. Especially when the width of the trench is increased to several mm,
After CMP, there is a problem that a dishing phenomenon occurs in which the central portion of the insulating layer is dished, which causes unstable element isolation characteristics and a step.
【０００７】ディッシング現象は、図１Ａに示すよう
に、ＣＭＰ前に基板上に全体的に形成された段差が存在
する場合、段差の低い方（ｂ）の研磨率が段差の高い方
（ａ）の研磨率より高くて研磨後に研磨された物質の厚
さが中央に近づくほど薄くなる（ｃ）。このようなディ
ッシング現象が、図１Ｂに示すように、ＳＴＩの平坦化
工程で発生すると、フィールド領域の中央部ではフィー
ルド酸化膜のシニングが生じ、セルアレイや広い活性領
域の中央部ではシリコン窒化膜（斜線部分）上の絶縁膜
が研磨し切れない。従って、シリコン窒化膜が取り除け
なく、よって活性領域が限定されない。As shown in FIG. 1A, when there is a step formed entirely on the substrate before the CMP, the dishing phenomenon has a lower step (b) and a higher polishing rate (a). The polishing rate is higher than the polishing rate, and the thickness of the substance polished after polishing becomes thinner toward the center (c). As shown in FIG. 1B, when such a dishing phenomenon occurs in the planarization process of STI, thinning of the field oxide film occurs in the central portion of the field region, and the silicon nitride film ( The insulating film on the shaded area cannot be completely polished. Therefore, the silicon nitride film cannot be removed and thus the active region is not limited.
【０００８】図１Ｃに示したように、層間絶縁膜（ＩＬ
Ｄ）形成工程でディッシングが発生すると、ＣＭＰ後の
ＩＬＤの厚さが領域により異なる。これにより、後続く
コンタクトホール（斜線部分）形成工程で活性領域とフ
ィールド領域で食刻すべき層間絶縁膜の深さが変わる問
題がある。ＣＭＰ工程においてディッシング現象のよう
なパターンの密度、寸法による異常研磨現象を減らすた
めにダミーパターンの挿入、ＣＭＰ前の写真食刻(pre-C
MPphoto-etching)方法が一般に用いられている。As shown in FIG. 1C, the interlayer insulating film (IL
D) If dishing occurs in the formation process, the thickness of the ILD after CMP varies depending on the region. As a result, there is a problem that the depth of the interlayer insulating film to be etched in the active region and the field region is changed in the subsequent contact hole (shaded portion) forming step. In the CMP process, dummy patterns are inserted to reduce abnormal polishing phenomenon due to pattern density and dimensions such as dishing phenomenon, and photo-etching (pre-C before CMP).
MP photo-etching) method is commonly used.
【０００９】図２Ａ乃至図２Ｃは異常研磨現象を防止す
るためのＣＭＰ前の写真食刻工程を説明するための断面
図である。図２Ａを参照すると、トレンチにより段差の
形成された半導体基板２０に絶縁層２４を形成し、広い
トレンチ領域の前記絶縁層上に平坦化ブロッキングマス
ク２６(Planarization Block Mask:ＰＢＭ）を形成して
段差の広い部位の高さを他の部位の高さと類似に形成す
る。次いで、前記ＰＢＭ２６の形成された結果物の全面
に平坦化レジスト２８を塗布する。2A to 2C are sectional views for explaining a photolithography process before CMP for preventing abnormal polishing. Referring to FIG. 2A, an insulating layer 24 is formed on a semiconductor substrate 20 having a step formed by a trench, and a planarization blocking mask 26 (Planarization Block Mask: PBM) is formed on the insulating layer in a wide trench region to form the step. The height of the wide part of the body is made similar to the height of other parts. Then, a planarizing resist 28 is applied on the entire surface of the resultant product on which the PBM 26 is formed.
【００１０】図２Ｂを参照すると、前記平坦化レジスト
層２８、ＰＢＭ２６及び絶縁層２４に対して反応性イオ
ン食刻法（Reactive Ion Etching; ＲＩＥ）を用いて食
刻した後、シリコン窒化膜２２の表面が露出されるまで
その結果物に対してＣＭＰを行って平坦な表面を有する
素子分離層を形成する。Referring to FIG. 2B, the planarization resist layer 28, the PBM 26, and the insulating layer 24 are etched using a reactive ion etching (RIE) process, and then the silicon nitride film 22 is formed. The resulting product is subjected to CMP until the surface is exposed to form a device isolation layer having a flat surface.
【００１１】[0011]
【発明が解決しようとする課題】前記した従来の方法に
よれば、図２Ｃに示すように、ＰＢＭ２６を形成するた
めに感光膜をパタニングするとき、ミスアライン又はオ
ーバーフィリング現象が発生することによってレジスト
の厚さが変わる問題があった。本発明の目的は異常研磨
現象を防止してトレンチに埋め立てられた素子分離層の
平坦度を改善し得る半導体装置の素子分離方法を提供す
ることにある。According to the above-mentioned conventional method, as shown in FIG. 2C, when the photoresist film is patterned to form the PBM 26, a misalignment or an overfilling phenomenon occurs, so that the resist is removed. There was a problem that the thickness changed. An object of the present invention is to provide an element isolation method for a semiconductor device, which can prevent abnormal polishing phenomenon and improve the flatness of an element isolation layer buried in a trench.
【００１２】[0012]
【課題を解決するための手段】前記の目的を達成するた
めに本発明による半導体装置の素子分離方法は、半導体
基板上に耐研磨層を形成する第１段階と、前記耐研磨層
上に、フィールド領域にダミーパターンを挿入して形成
された感光膜パターンを形成する第２段階と、前記感光
膜パターンをマスクとして前記耐研磨層をパタニングす
る第３段階と、前記パタニングされた耐研磨層をマスク
として前記半導体基板にトレンチを形成する第４段階
と、トレンチの形成された結果物に絶縁物質を蒸着して
前記トレンチを埋め立てる第５段階と、前記耐研磨層の
表面が露出されるまで前記絶縁物質をＣＭＰする第６段
階とを含むことを特徴とする。In order to achieve the above object, the element isolation method for a semiconductor device according to the present invention comprises a first step of forming a polishing resistant layer on a semiconductor substrate, and a step of forming the polishing resistant layer on the polishing resistant layer. A second step of forming a photosensitive film pattern formed by inserting a dummy pattern in the field region, a third step of patterning the polishing resistant layer using the photosensitive film pattern as a mask, and a third step of forming the patterned polishing resistant layer. A fourth step of forming a trench in the semiconductor substrate as a mask, a fifth step of filling the trench by depositing an insulating material on a resultant product in which the trench is formed, and a step of exposing the surface of the polishing resistant layer until the surface is exposed. A sixth step of CMP the insulating material.
【００１３】前記耐研磨層はシリコン窒化膜、酸化膜、
金属膜、有機物中のいずれか一つの物質より構成された
単一膜又は前記物質よりなる複合膜を用いて形成され
る。前記第２段階で形成するダミーパターンは、活性領
域の縁部を取り囲む連続的又は断続的に連結されたパタ
ーンよりなるガードリングを含むことが望ましい。か
つ、前記ガードリングは活性領域の縁部から素子分離特
性に影響を及ぼさない距離ほど離れていることが望まし
い。The polishing-resistant layer is a silicon nitride film, an oxide film,
It is formed using a metal film, a single film made of any one of organic substances, or a composite film made of the above substances. It is preferable that the dummy pattern formed in the second step includes a guard ring formed of a pattern that continuously or intermittently surrounds an edge of the active region. In addition, it is desirable that the guard ring is separated from the edge of the active region by a distance that does not affect the element isolation characteristics.
【００１４】前記５段階で蒸着される絶縁物質の厚さ
は、前記絶縁物質が蒸着された後のダミーパターンの挿
入された部位とセル領域との段差が±１μｍ以内になる
ように調節することが望ましい。The thickness of the insulating material deposited in the above five steps is controlled so that the step between the cell where the dummy pattern is inserted and the cell region is within ± 1 μm after the insulating material is deposited. Is desirable.
【００１５】[0015]
【発明の実施の形態】以下、添付した図面に基づき本発
明の実施の形態を詳細に説明する。上述したように、Ｃ
ＭＰ工程時、段差の高い部分の面積が周辺の面積に比し
て小さいほど、且つその高さが低いほど全体的に平坦化
し易い。従って、ＣＭＰ以前に全般的な高さを均一に
し、周辺に比して高い部分の面積を縮めると、ディッシ
ング現象を防止して平坦化し易い。Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. As mentioned above, C
During the MP process, the smaller the area of the high step portion compared to the peripheral area and the lower the height, the easier the overall flattening. Therefore, if the overall height is made uniform before CMP and the area of the portion higher than the periphery is reduced, it is easy to prevent dishing and flatten the surface.
【００１６】本発明はこのような原理を用いたものであ
り、広いトレンチにセル領域のパターンと同一のダミー
パターンを挿入して、全体的に均一の高さに調節するこ
とによりディッシング現象を抑える。図３Ａは一般のＤ
ＲＡＭのレイアウト図であり、図３Ｂは本発明によるレ
イアウト図である。The present invention uses such a principle, and suppresses the dishing phenomenon by inserting a dummy pattern identical to the pattern of the cell region into a wide trench and adjusting the height to a uniform height as a whole. . FIG. 3A shows a general D
FIG. 3 is a layout diagram of a RAM, and FIG. 3B is a layout diagram according to the present invention.
【００１７】図面の参照符号３０は活性領域を限定する
ためのマスクパターン、４０はセル領域、４５は前記セ
ル領域に形成されるパターンを形成するためのマスクパ
ターン、５０はフィールド領域、５５は前記フィールド
領域に挿入されたダミーパターンを形成するためのマス
クパターンをそれぞれ示す。図３Ｂの改善されたレイア
ウト図においては、広いトレンチを有するフィールド領
域５０に、トランジスタの動作に影響を及ぼさない範囲
内でセル部位に形成されたパターン４５と同一のダミー
パターンを挿入するようにレイアウトされている。従っ
て、同図に示したように、ＣＭＰ直前に大部分の面積が
セル部位と同一の高さを有することによってディッシン
グ現象が防止される。かつ、このダミーパターンはセル
領域のパターンと同一でなくても、ＣＭＰ観点からセル
部位とダミーパターン部位との段差を低減させ得るライ
ン・スペースパターンなども含むことができる。Reference numeral 30 in the drawings denotes a mask pattern for limiting an active region, 40 denotes a cell region, 45 denotes a mask pattern for forming a pattern formed in the cell region, 50 denotes a field region, and 55 denotes the above. The mask patterns for forming the dummy patterns inserted in the field regions are shown respectively. In the improved layout diagram of FIG. 3B, the layout is such that the same dummy pattern as the pattern 45 formed in the cell portion is inserted into the field region 50 having a wide trench within a range that does not affect the operation of the transistor. Has been done. Therefore, as shown in the figure, the dishing phenomenon is prevented by having most of the area having the same height as the cell portion immediately before CMP. In addition, the dummy pattern may include a line / space pattern that can reduce the step between the cell portion and the dummy pattern portion from the viewpoint of CMP even if it is not the same as the pattern of the cell region.
【００１８】図４は前記図３Ｂのレイアウト図を具体的
に示したレイアウト図である。図４を参照すると、フィ
ールド領域に活性領域のトランジスタの動作に影響を与
えない範囲内でセル部位と同一のダミーパターンを挿入
することによりＣＭＰ直前に大部分の面積がセル部位と
同一な高さを保つようにする。この際、活性領域とフィ
ールド領域との境界部には、連続的または断続的なガー
ドリング６０を形成して、アイランドパターンの崩れを
防止する。FIG. 4 is a layout diagram specifically showing the layout diagram of FIG. 3B. Referring to FIG. 4, a dummy pattern, which is the same as the cell part, is inserted in the field region within a range that does not affect the operation of the transistor in the active region. Try to keep At this time, a continuous or intermittent guard ring 60 is formed at the boundary between the active region and the field region to prevent the island pattern from collapsing.
【００１９】さらに、フィールド領域に挿入された前記
ダミーパターンは、ＣＭＰ工程時のディッシング現象を
抑えることができ、フィールド領域が素子分離領域とし
ての電気的な役割を果たすほど、その数と活性領域との
距離を調節する。参照符号３５はゲートラインを形成す
るためのマスクパターンである。図５Ａ乃至図５Ｃは本
発明による素子分離方法を説明するための断面図であ
る。Further, the dummy pattern inserted in the field region can suppress the dishing phenomenon during the CMP process, and the number of the dummy patterns inserted into the field region and the number of active regions are increased as the field region plays an electrical role as an element isolation region. Adjust the distance of. Reference numeral 35 is a mask pattern for forming a gate line. 5A to 5C are cross-sectional views illustrating an element isolation method according to the present invention.
【００２０】図５Ａはフィールド領域にトレンチを形成
する段階の断面図である。これは、半導体基板７０上に
パッド酸化膜７２及び窒化膜７４を順に積層する第１段
階と、図４のマスクパターンを用いた写真食刻工程を施
して前記窒化膜７４及びパッド酸化膜７２をパタニング
する第２段階と、露出された半導体基板７０を食刻する
ことによりトレンチ７６を形成する第３段階とよりな
る。FIG. 5A is a sectional view showing a step of forming a trench in the field region. The first step is to sequentially stack the pad oxide film 72 and the nitride film 74 on the semiconductor substrate 70, and the photolithography process using the mask pattern of FIG. 4 is performed to remove the nitride film 74 and the pad oxide film 72. It comprises a second step of patterning and a third step of forming the trench 76 by etching the exposed semiconductor substrate 70.
【００２１】前記パッド酸化膜７２はストレス緩和用、
前記窒化膜７４はトレンチ形成時食刻阻止層として、そ
してＣＭＰ工程時の耐研磨層として用いられる。前記第
２及び第３段階により、本発明のレイアウトにより広い
トレンチ領域に後続くＣＭＰ工程時のディッシング現象
を抑えるためのダミーパターン７８が形成される。The pad oxide film 72 is for stress relief,
The nitride film 74 is used as an etch stop layer during trench formation and as a polishing resistant layer during the CMP process. According to the second and third steps, the dummy pattern 78 for suppressing the dishing phenomenon in the subsequent CMP process is formed in the wide trench region according to the layout of the present invention.
【００２２】図５Ｂは層間絶縁層８０を形成した状態の
断面図である。具体的に、トレンチの形成された結果物
上に前記トレンチを埋め立てるための絶縁物質、例えば
ＣＶＤ酸化膜を蒸着して絶縁層８０を形成する。この
際、広いトレンチ７６に形成された前記ダミーパターン
７８により、前記絶縁層８０が蒸着された後、全体的に
高さが均一となる。FIG. 5B is a sectional view showing a state where the interlayer insulating layer 80 is formed. Specifically, an insulating material for filling the trench, for example, a CVD oxide film is deposited on the resultant product in which the trench is formed to form the insulating layer 80. At this time, due to the dummy pattern 78 formed in the wide trench 76, the height becomes uniform after the insulating layer 80 is deposited.
【００２３】図５ＣはＣＭＰを行った後の断面図であ
る。具体的に、前記窒化膜７４の表面が露出されるまで
絶縁層８０をＣＭＰする第１段階と、前記窒化膜７４を
取り除く第２段階とよりなる。同図に示すように、広い
トレンチ７６に挿入されたダミーパターン７８によりＣ
ＭＰ工程時のディッシング現象を抑えることができ、従
って平坦な素子分離層を形成し得る。FIG. 5C is a cross-sectional view after performing CMP. Specifically, it comprises a first step of CMP the insulating layer 80 until the surface of the nitride film 74 is exposed, and a second step of removing the nitride film 74. As shown in the figure, the dummy pattern 78 inserted in the wide trench 76 causes C
The dishing phenomenon during the MP process can be suppressed, and thus a flat element isolation layer can be formed.
【００２４】[0024]
【発明の効果】前記した本発明によれば、段差の広いフ
ィールド領域に素子の動作に影響を及ぼさない範囲内で
セル領域と同一の段差のダミーパターンを挿入して、Ｃ
ＭＰ直前に大部分の面積が均一な高さを保つようにする
ことで、ＣＭＰ時のディッシング現象が抑えられる。According to the present invention described above, a dummy pattern having the same step as that of the cell region is inserted in the field region having a large step, within the range that does not affect the operation of the device, and C
The dishing phenomenon at the time of CMP can be suppressed by maintaining the uniform height of most of the area immediately before MP.
【００２５】本発明は前記実施例に限定されず、本発明
の技術的思想内で当分野の通常の知識を持つ者により多
くの変形が可能なのは明らかである。例えば、セル部位
と同一のパターンをダミーパターンとして用いるのは、
電子ビームなどを用いてマスクを製造するときのデータ
量を増やせる。このデータ量を縮める方法として、ライ
ン・スペースパターンまたはアイランドパターンなどを
フィールド領域に形成することにより、ＣＭＰ直前のセ
ル部位とダミーパターンの挿入されたフィールド部位と
の段差を、ダミーパターンを挿入する前より減らすこと
ができる。The present invention is not limited to the above embodiments, and it is obvious that many modifications can be made by a person having ordinary skill in the art within the technical idea of the present invention. For example, using the same pattern as the cell part as the dummy pattern is
The amount of data when manufacturing a mask using an electron beam or the like can be increased. As a method for reducing the amount of data, a line / space pattern or an island pattern is formed in the field region so that the step between the cell portion immediately before CMP and the field portion in which the dummy pattern is inserted can be formed before the dummy pattern is inserted. Can be reduced more.
【図１】Ａ乃至Ｃはディッシング現象を説明するための
断面図である。1A to 1C are cross-sectional views for explaining a dishing phenomenon.
【図２】Ａ乃至Ｃはディッシング現象を抑えるための従
来の一方法を説明するための断面図である。2A to 2C are cross-sectional views for explaining a conventional method for suppressing the dishing phenomenon.
【図３】ＡはＤＲＡＭを製造するための従来の一般的な
レイアウト図であり、Ｂは本発明によるダミーパターン
の挿入されたＤＲＡＭのレイアウト図である。3A is a conventional general layout diagram for manufacturing a DRAM, and FIG. 3B is a layout diagram of a DRAM in which a dummy pattern according to the present invention is inserted.
【図４】前記図３Ｂのレイアウトを具体的に示したレイ
アウト図である。FIG. 4 is a layout diagram specifically showing the layout of FIG. 3B.
【図５】Ａ乃至Ｃは本発明の素子分離方法を用いたＳＴ
Ｉ方法を説明するための断面図である。5A to 5C are STs using the element isolation method of the present invention.
It is sectional drawing for demonstrating I method.
３０ マスクパターン ３５ マスクパターン ４０ セル領域 ４５ マスクパターン ５０ フィールド領域 ５５ マスクパターン（感光膜パターン） ６０ ガードリング ７０ 半導体基板 ７２ パッド酸化膜 ７４ 窒化膜（耐研磨層） ７６ トレンチ ７８ ダミーパターン ８０ 絶縁層（絶縁物質） 30 mask pattern 35 mask pattern 40 cell region 45 mask pattern 50 field region 55 mask pattern (photosensitive film pattern) 60 guard ring 70 semiconductor substrate 72 pad oxide film 74 nitride film (polishing resistant layer) 76 trench 78 dummy pattern 80 insulating layer ( Insulation material)
Claims (5)
段階と、 前記耐研磨層上に、フィールド領域にダミーパターンを
挿入して形成された感光膜パターンを形成する第２段階
と、 前記感光膜パターンをマスクとして前記耐研磨層をパタ
ニングする第３段階と、 前記パタニングされた耐研磨層をマスクとして前記半導
体基板にトレンチを形成する第４段階と、 トレンチの形成された結果物に絶縁物質を蒸着して前記
トレンチを埋め立てる第５段階と、 前記耐研磨層の表面が露出されるまで前記絶縁物質をＣ
ＭＰする第６段階とを含むことを特徴とする半導体装置
の素子分離方法。1. A first anti-polishing layer is formed on a semiconductor substrate.
A second step of forming a photoresist pattern formed by inserting a dummy pattern in a field region on the abrasion resistant layer; and a third step of patterning the abrasion resistant layer using the photoresist pattern as a mask. A fourth step of forming a trench in the semiconductor substrate using the patterned polishing-resistant layer as a mask; a fifth step of depositing an insulating material on the resultant product in which the trench is formed to fill the trench; The insulating material is replaced with C until the surface of the polishing layer is exposed.
And a sixth step of performing MP.
膜、金属膜、有機物中のいずれか一つの物質より構成さ
れた単一膜又は前記物質よりなる複合膜より形成される
ことを特徴とする請求項１に記載の半導体装置の素子分
離方法。2. The polishing resistant layer is formed of a silicon nitride film, an oxide film, a metal film, a single film made of any one of organic substances, or a composite film made of the substances. The element isolation method for a semiconductor device according to claim 1.
は、活性領域の縁部を取り囲む連続的又は断続的に連結
されたパターンよりなるガードリングを含むことを特徴
とする請求項１に記載の半導体装置の素子分離方法。3. The dummy pattern formed in the second step includes a guard ring formed of a pattern that is continuously or intermittently connected and surrounds an edge of the active region. Element isolation method for semiconductor device.
素子分離特性に影響を及ぼさない距離ほど離れているこ
とをことを特徴とする請求項３に記載の半導体装置の素
子分離方法。4. The element isolation method for a semiconductor device according to claim 3, wherein the guard ring is separated from an edge of the active region by a distance that does not affect element isolation characteristics.
さは、前記絶縁物質が蒸着された後のダミーパターンの
挿入された部位とセル領域との段差が±１μｍ以内にな
るように調節する厚さであることを特徴とする請求項１
に記載の半導体装置の素子分離方法。5. The thickness of the insulating material deposited in the fifth step is such that a step between a portion where the dummy pattern is inserted and a cell region after depositing the insulating material is within ± 1 μm. A thickness that is adjusted.
6. The element isolation method for a semiconductor device according to claim 1.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019950028482A KR0155874B1 (en) | 1995-08-31 | 1995-08-31 | Isolating method and planerizing method |
| KR1995P28482 | 1995-08-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09107028A true JPH09107028A (en) | 1997-04-22 |
Family
ID=19425779
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8225456A Pending JPH09107028A (en) | 1995-08-31 | 1996-08-27 | Element isolation method for semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH09107028A (en) |
| KR (1) | KR0155874B1 (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| KR0155874B1 (en) | 1998-12-01 |
| KR970013074A (en) | 1997-03-29 |
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