JPH08195906A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE: To reduce the amount of hardware concerning a sample-and-hold (S/H) circuit with which the value of a charge storage level is held by deciding a reference level part to be the reference of a charge storage level part in an output signal waveform from a charge-coupled device(CCD) for one pixel at the transition timing of a clamp signal. CONSTITUTION: The output signal of the CCD is delayed for a prescribed time by a delay line 1. Corresponding to a phase difference between this delayed signal and the output signal, the clamp signal to a clamp-and-hold circuit 3 is generated by a comparator 2. Thus, since a CDS clock is generated from the output signal itself from the CCD, it is not necessary to provide an external dedicated circuit for generating the CDS clock so that the hardware amount can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a circuit for sample and hold an output signal from a charge coupled device for one pixel.

[0002]

2. Description of the Related Art Generally, a charge coupled device (Charge) is used.
An output signal from a Coupled Device (hereinafter referred to as a CCD) is correlated double sampling (Correlated Double Sampling) for each pixel.
Sampling; hereinafter referred to as CDS) is performed. Conventionally, in a sample hold circuit for performing the CDS processing, a sampling clock (hereinafter referred to as a CDS clock) is created by a circuit of a system different from that of the output signal from the CCD.

By the way, Japanese Patent Laid-Open No. 62-258570 discloses a system for reproducing a clock from a composite video signal. According to this method, the clock can be regenerated from the received composite video signal.

[0004]

In the above-described conventional sample-hold circuit, the CDS clock whose phase relationship with the output signal from the CCD is strictly fixed must be input from the outside, so that a dedicated circuit must be provided. I won't. Therefore, there is a drawback that the amount of hardware becomes large.

Further, in the system described in the above-mentioned patent publication, the clock must be input in advance on the transmitting side of the composite video signal, and it cannot be applied when the output signal from the CCD is sampled and held. .

The present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide a sample hold circuit which can reduce the amount of hardware.

[0007]

A sample and hold circuit according to the present invention determines a reference level portion, which is a reference of a charge accumulation level portion, of a waveform of an output signal from a charge coupled device for one pixel at a transition timing of a clamp signal. A sample and hold circuit for holding the value of the charge accumulation level by delaying means for delaying the output signal by a predetermined time, and generating the clamp signal according to the phase difference between the delay signal and the output signal. And a clamp signal generating means.

[0008]

In the sample hold circuit for holding the value of the charge storage level by determining the reference level portion, which is the reference of the charge storage level portion, in the output signal waveform from the charge coupled device for one pixel at the transition timing of the clamp signal. , The output signal of the CCD is delayed by the delay line 1 for a predetermined time. The clamp signal is generated by the comparator 2 according to the phase difference between the delay signal and the output signal.

[0009]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a sample hold circuit according to the present invention. In the figure, a sample and hold circuit according to an embodiment of the present invention is
A delay line 1 for delaying an output signal 10 of a CCD (not shown) for a predetermined time, a comparator 2 for comparing the voltage levels of the delayed signal and the output signal 10, and a rising timing of an output signal 20 as a result of the comparison. The clamp hold circuit 3 holds the voltage level value of the output signal 10.

Here, in the sample and hold circuit of this embodiment, the output of the delay line 1 and the comparator 2 are
Level clipper circuits 41 and 42 are inserted between the input and the input. This is to prevent the malfunction of the comparator 2 due to the fluctuation of the voltage level of the output signal 10 from the CCD.

That is, the level clipper circuit 41 is +
It is configured to include a diode D1 connected to a power supply voltage of 0.5 [V]. If the voltage across the diode D1 is 0.6 [V], then 0.5-0.6 = -0.1, so that the level clipper circuit 41 has a negative input of the comparator 2 from -0.1 [V]. Does not decrease (minimum value is -0.1
[V]).

The level clipper circuit 42 is -0.3.
It is configured to include a diode D2 connected to the power supply voltage of [V]. Set the voltage across diode D2 to 0.6
If it is [V], -0.3 + 0.6 = 0.3, so
The positive input of the comparator 2 of the level clipper circuit 42 does not exceed 0.3 [V] (the maximum value is 0.3 [V]).
It works like.

As described above, the level clipper circuits 41 and 42 suppress fluctuations in the voltage levels of the output signal 10 from the CCD and the output signal 11 which is a delayed output, thereby preventing malfunction of the comparator 2.

The operation of the sample and hold circuit of this embodiment having the above structure will be described with reference to FIG. FIG. 2 is a waveform diagram of each part of the sample hold circuit of FIG. 1, showing an output signal 10 of the CCD, an output signal 11 of the delay line 1 and an output signal 20 of the comparator 2.

In the figure, an output signal 10 is an output signal waveform from the CCD for one pixel. This output signal 10
In the waveform of, the part rising from -5 [V] to +5 [V] is called a reset edge, which is caused by the crosstalk of the reset pulse for resetting the charge accumulated in the CCD. Then, after this reset, the output signal 10 becomes 0 [V] and then becomes a voltage level in the negative direction according to the amount of charge accumulated in the CCD. In the figure, it is -5 [V], but the voltage level fluctuates.

Here, the clamp hold circuit 3 determines the 0 [V] portion of the waveform of the output signal 10 as the reference level, and then holds the charge accumulation level. Then, in order to determine the 0 [V] portion of the waveform as the reference level, in the present embodiment, the voltage levels of the output signal 10 and the output signal 11 of the delay line 1 are compared, and the output signal 20 which is the comparison result is compared. Is used as a clamp signal.

That is, the output signal 20 generated according to the phase difference between the output signal 10 and the output signal 11 is input to the clamp hold circuit 3 as a clamp signal, and the output signal 2
The 0 [V] portion of the waveform of the output signal 10 is defined as the reference level at the rising timing of 0 from the low level to the high level.

In order to match the rising timing of the output signal 20 with the 0 [V] portion of the waveform of the output signal 10, a delay line (not shown) has a clamp hold circuit 3.
It shall be provided inside.

According to the above configuration, it is not necessary to externally input the CDS clock whose phase is strictly fixed to the output signal from the CCD. Therefore, it is not necessary to provide an external dedicated circuit for generating the CDS clock.

Although the rising timing of the clamp signal is used in this example, it is clear that the falling timing may be used.

[0022]

As described above, according to the present invention, since the CDS clock is generated from the output signal itself from the CCD, it is not necessary to provide an external dedicated circuit for generating the CDS clock, and the hardware amount is reduced. effective.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a sample hold circuit according to an embodiment of the present invention.

FIG. 2 is a waveform diagram showing the operation of each unit in FIG.

[Explanation of symbols]

 1 Delay line 2 Comparator 3 Clamp and hold circuit 41, 42 Level clipper circuit

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 23, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction content]

In the figure, an output signal 10 is an output signal waveform from the CCD for one pixel. This output signal 10
In the waveform of, the part rising from −0.5 [V] to +0.5 [V] is called the reset edge, and the CCD
This is caused by the crosstalk of the reset pulse for resetting the accumulated charge of. Then, after this reset, the output signal 10 becomes 0 [V], and then CC
The voltage level in the negative direction changes according to the amount of accumulated charge of D. Although it is −0.5 [V] in the figure, the voltage level fluctuates.

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 2

[Correction method] Change

[Correction content]

[Fig. 2]

Claims (3)

[Claims] 1. A sample for holding the value of the charge storage level by defining a reference level portion, which is a reference of the charge storage level portion, in a waveform of an output signal from a charge coupled device for one pixel at a transition timing of a clamp signal. A holding circuit, comprising: delay means for delaying the output signal for a predetermined time; and clamp signal generating means for generating the clamp signal according to a phase difference between the delay signal and the output signal. Sample and hold circuit. 2. The clamp signal generation means includes a comparison means for comparing the voltage levels of the delay signal and the output signal, and outputs a signal that transitions in response to a change in the comparison result as the clamp signal. The sample-hold circuit according to claim 1, wherein 3. The sample hold circuit according to claim 2, further comprising level fluctuation suppressing means for suppressing voltage level fluctuations of the delay signal and the output signal.