JP2507965B2 - Sample-hold circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit that performs sample and hold based on a sampling signal.

[0002]

2. Description of the Related Art Generally, a sample and hold circuit is described in 185 to 18 of Basic theory of control engineering (Maruzen Co., Ltd., Hiroki Fukushima).
As described on page 8, when a sampling pulse is input, it is held until the next input.

A configuration example of a conventional sample and hold circuit will be described with reference to FIG. In FIG. 2, the conventional sample hold circuit includes a comparator 1 for comparing the voltage level of the pulse signal Va input to the terminal a with the level of the reference voltage Vb, a delay circuit 5 for delaying this output for a predetermined time, and this output. In response to the sampling pulse generating circuit 6 for generating a sampling pulse e having a constant pulse width.

Further, the conventional sample hold circuit includes a switch 8 driven by a sampling pulse e, a capacitor 10 for holding the output, and an operational amplifier 1.
0, and the held voltage level is output from the terminal b. The reference voltage Vb is generated by dividing the voltage level of the reference voltage source 4 by the resistors 2 and 3.

In such a configuration, the pulse signal Va to be measured is input to the comparator 1 and the reference voltage V
The level is compared with b. When the voltage level of the signal Va is higher than the reference voltage Vb, the pulse detection signal c is output from the comparator 1.

The pulse detection signal c is delayed by the delay circuit 5 for a fixed time (Td) in order to delay the sampling timing only during the rising time of the pulse signal Va, and then input to the sampling pulse generation circuit 6. The sampling pulse generation circuit 6 generates a sampling pulse e having a pulse width Ts in response to the rise of the pulse detection signal d delayed by the time Td.

When the sampling pulse e is input to the switch 8, the switch 8 is turned on for a time corresponding to the pulse width Ts, and this output causes the capacitor 10 to be turned on.
Is charged. Then, the charging voltage level of the capacitor 10 at the time when the switch 8 is turned off is held and output from the terminal b via the operational amplifier 10.

[0008]

In the above-mentioned conventional sample hold circuit, when the pulse width of the input pulse signal Va is narrower than the time (Td + Ts), the time when there is no pulse, that is, the pulse signal Va is not active. Sometimes sampling was done at that time. That is, when Td + Ts is the minimum detection pulse width and the pulse width of the input pulse signal Va is narrower than this, the switch 8 is turned on in the state of no signal detection and sampling is performed. There was a drawback that the hold circuit did not work properly.

Incidentally, Japanese Patent Laid-Open No. 1-273422 discloses a PLL circuit including a sample hold circuit having a similar structure, but such a circuit cannot prevent malfunction.

The present invention has been made to solve the above-mentioned conventional drawbacks, and an object thereof is to provide a sample hold circuit which does not malfunction even when the pulse width of a pulse signal input as a sampling target is narrow. It is to be.

[0011]

A sample and hold circuit according to the present invention comprises a constant pulse generating means for generating a pulse having a constant pulse width in response to an input of a pulse signal to be sampled, the generated pulse and the pulse. Sampling signal generating means for outputting a sampling signal when the signal is active, and sample-holding the pulse signal based on the sampling signal.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a sample hold circuit according to the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. In such a configuration, the sample hold circuit according to the embodiment of the present invention is different from the conventional one in that an AND circuit 7 is provided.

That is, the logical sum of the pulse detection signal c and the sampling pulse e is calculated, and the switch 8 is driven by the logical sum output f. As a result, the output f is sent out only when the pulse detection signal c and the sampling pulse e are active, and the sample hold is performed based on this, so avoid turning on the switch 8 in a no-signal state. Therefore, the malfunction of the sample and hold circuit can be prevented. Therefore, even if the pulse width of the pulse signal Va is narrower than the minimum detection pulse width, the circuit does not malfunction.

In FIG. 1 and FIG. 2, the delay circuit 5
Is provided and the sampling timing is delayed only during the rise time of the pulse signal Va. However, if the rise time is shorter than the delay time of the line that constitutes the circuit, the delay circuit 5 need not be provided.

[0016]

As described above, according to the present invention, when the pulse signal to be sampled is active, the sampling signal is output and the pulse signal is sampled and held. The effect is that it can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a sample hold circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional sample hold circuit.

[Explanation of symbols]

 1 Comparator 2, 3 Resistance 4 Reference voltage source 5 Delay circuit 6 Sampling pulse generation circuit 7 AND circuit 8 Switch 9 Capacitor 10 Operational amplifier

Claims (2)

(57) [Claims] 1. A constant pulse generating means for generating a pulse having a constant pulse width in response to an input of a pulse signal to be sampled, and the generated pulse and the sampling signal when the pulse signal is active. A sampling and holding circuit for outputting the sampling signal, and sampling and holding the pulse signal based on the sampling signal. 2. The constant pulse generating means includes a delay means for delaying the pulse signal for a constant time, and a means for generating a pulse having the constant pulse width in response to an output from the delay means. The sample hold circuit according to claim 1.