JPS63305678A - Processing circuit for output signal of solid-state image pickup element - Google Patents

Abstract

PURPOSE:To eliminate reset noise of an image pickup device with simple constitution by providing a means to clamp the reference signal part of signals in respective picture element periods, a clamping voltage supplying means, and a means which compares the image signal part of a clamped signal with a clamping voltage, and outputs the result. CONSTITUTION:A DC bias voltage included in an output signal 30 from a CCD image sensor 12 is eliminated by a capacitor 22, and the level of the flat part P of the signal 30 is clamped by a clamping circuit 14 in order to eliminate reset noise of the sensor 12 included in the signal 30. At an A/D converter 18, the A/D conversion is applied while using the voltage generated by clamping the flat part P by the circuit 14 as a reference voltage, therefore, a digital image signal 36 independent of the value of the voltage generated by clamping the flat part P can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output signal processing circuit for a solid-state imaging device, such as a CCD image sensor.

1.1 The output signal of the CCD image sensor is, in addition to the video signal,
Contains reset noise due to DC bias voltage and reset pulse. Therefore, it is required to remove these from the output signal to obtain a noise-free video signal.

For example, the circuit described in JP-A-81-7778 generates a flat part as a reference signal period (feed-through period) in one pixel period by advancing the phase of the reset pulse. Since the original level fluctuates in each pixel period according to the level of the flat part, the level of the image signal is corrected with reference to the level of the flat part to remove reset noise.

That is, signals are input to each of the two AD converters, and the strobe pulse applied to one AD converter is placed at the center of the flat area, and the strobe pulse applied to the other AD converter is placed at the center of the image signal area. make me stand up Then, by inputting the outputs of the two AD converters to a subtracter, the signal of the flat part reference level is subtracted from the image signal of each pixel period, and reset noise is removed from the image signal of each pixel period. . In addition, the removal of DC bias voltage is
This is done using a capacitor.

However, in this circuit, the AD converter is
Since the circuit must be used individually, it has the disadvantage that the circuit becomes complicated and expensive.

Purpose The present invention solves the drawbacks of the prior art, and
It is an object of the present invention to provide an output signal processing circuit that can remove reset noise of a solid-state image sensor with a simple configuration without using a D converter.

According to the present invention, the processing circuit that removes reset noise caused by the reset pulse of the solid-state image sensor from the signal output from the solid-state image sensor in response to the clock pulse is configured to remove the reset pulse from the trailing edge of the clock pulse. Reset pulse generating means that generates a phase-advanced signal, clamping means that clamps a reference signal portion in each pixel period of a signal output from the solid-state imaging device to a clamp voltage, and clamp voltage supplying means that supplies the clamp voltage to the clamping means. and an image signal output means for comparing and outputting an image signal part in each pixel period of the signal clamped by the clamp means with a clamp voltage supplied from the clamp voltage supply means,
The image signal output means corrects the level of the image signal portion in each pixel period according to the clamp voltage to obtain an image signal from which reset noise has been removed.

11 Wataru II Next, embodiments of an output signal processing circuit for a solid-state image sensor according to the present invention will be described in detail with reference to the accompanying drawings.

, FIG. 1 shows an embodiment of an output signal processing circuit according to the present invention.

A pulse generation circuit 20 is connected to the CCD image sensor 12, and the pulse generation circuit 20 converts shifted pulses φS, clock pulses φl, φ2, and reset pulses φRs into CCs.
D image sensor 12 is supplied. As shown in FIG. 2, the high level period of the reset pulse φRs occurs at the third timing from the front, which divides the 1/2 period A of the clock pulses φl and φ2 into four, that is, the first timing from the trailing edge. position, and the phase is advanced by A/4 period from the normal timing. By supplying such a reset pulse φRs, the signal 30 transferred and output from the CCD image sensor 12 always has one reference signal period (feed-through period) in one pixel period, as shown in FIG. A flat portion P is generated, and a pixel signal portion i is output after this flat portion P.

The output signal 30 of the CCD image sensor 12 is input to the clamp circuit 14 via the capacitor 22. Capacitor 22 removes the DC bias voltage from output signal 30 of CCD image sensor 12 . A clamp pulse φC is supplied to the clamp circuit 14. As shown in FIG. 2, the high level period of the clamp pulse φC is located approximately at the center of the flat portion P of the output signal 30 of the CCD image sensor 12. Further, a clamp power source 24 is connected to the clamp circuit 14, and a predetermined clamp voltage is supplied thereto.

The output 32 from the clamp circuit 14 is clamped so that the flat part P of the output signal 3o of the image sensor 12 becomes a predetermined voltage supplied from the power supply 24, as shown in FIG.

Since the output signal 3o from the CCD image sensor 12 includes the reset noise of the image sensor 12, the level of the flat part P, which is the reference signal level, does not fluctuate every pixel period as shown in the figure. are doing. Along with this, the level of the image signal part i following the flat part P also becomes
It fluctuates every pixel period in accordance with the fluctuation of the level of the flat portion P.

The clamp circuit 14 adjusts the level of the flat part P in each pixel period of the output signal 3o from the image sensor 12 to the reference voltage from the t source 24 by means of a clamp pulse φC supplied so as to be located approximately at the center of the flat part P. Match. That is, the flat portion P, which takes a different value for each pixel period, is clamped to a constant reference voltage as shown by the output 32 in FIG. Accordingly, flat F! The image signal section 1 following the BP is also freed from fluctuations from pixel period to pixel period due to reset noise.

Output 32 from clamp circuit 14 is input to sample and hold circuit 16 . A sample and hold pulse φsH is supplied to the sample and hold circuit 16.゛As shown in Fig. 2, the sample and hold pulse φsH is positioned approximately at the center of the image signal portion
The value of the image signal part i of is sampled and held as shown in the figure.

The output 34 of the sample and hold circuit 16 is supplied to the AD converter 1.
8 is input. Also for AD converter 18. The voltage from the power supply 24 that supplies the reference voltage of the clamp circuit 14 is
It is input to the reference potential terminal R. The AD converter 1B is further supplied with an AD conversion pulse φAII. The AD conversion pulse φAD is designed to AD convert the output 34 of the sample and hold circuit 1B, as shown in FIG.

The sample and hold pulse φsH is supplied with a slightly delayed phase.

The AD converter 18 uses the voltage input from the power supply 24 to the reference potential terminal H as a reference, and converts the input 34 from the sample and hold circuit 1B into a digital signal 36 in synchronization with the AD conversion pulse φAn. This AD conversion is performed by the clamp circuit 1
Since the voltage from the voltage source 1A24 that supplies the reference voltage of 4 is used as the reference voltage, the flat part P in the clamp circuit] 4
The voltage level at which the voltage is clamped can be considered.

In this embodiment, as described above, the DC bias voltage included in the output signal 30 from the CCD image sensor 12 is removed by the capacitor 22, and the level of the flat part P of the output signal 30 is clamped by the clamp circuit 14 and output. The reset noise of the CCD image sensor 12 contained in the signal 30 is removed. In the AD converter 18, AD conversion is performed using the voltage obtained by clamping the flat part P by the clamp circuit 14 as a reference voltage.
It is possible to obtain a digital image signal 36 that is independent of the value of the voltage clamped.

Here, in order to clarify the characteristics of this embodiment, a comparison will be made with a circuit described in Japanese Patent Laid-Open No. 81-7778 as a conventional example.

FIG. 3 shows a circuit disclosed in Japanese Patent Application Laid-Open No. 81-7778. In this circuit, a CCD image sensor 1
The output of 22 is input to two AD converters 114 and 11B via a capacitor 122. AD converter 11
The strobe pulse SDP supplied to the AD converter 11B is located approximately at the center of the flat part P of the output signal from the image sensor 112, and the strobe pulse SDP supplied to the AD converter 11B is
Di is located approximately at the center of the image signal portion i of the output signal from the image sensor 112. Therefore, in the AD converter 114, the flat part P of the output signal from the image sensor 112 is converted into a digital signal, and in the An converter 11B, the image signal part i of the output signal from the image sensor 112 is converted into a digital signal. Ru.

The outputs of these AD converters 114 and tte are stored in storage units 118 and 120, respectively, and stored in storage unit 11B.
and 120 pixel by pixel and subtracter 124
is output to. AO converter 114 in subtracter 124
and 11B are subtracted pixel by pixel. Therefore, the output from subtractor 124 is
Since the values of the 0 image signal part i and the flat part P, which are obtained by subtracting the value of the flat part P from the value of the image signal part i of the output signal from , fluctuate by the same amount due to reset noise, By subtracting, the fluctuation due to reset noise can be removed from the signal of the image signal portion i.

Conventionally, reset noise included in the output signal from the image sensor 112 was removed in this way.
Two expensive AD converters had to be used, and the circuit was complicated.

On the other hand, according to this embodiment, one A
The circuit can be configured using only the DR converter, and reset noise can be removed using a simple and inexpensive circuit.

Circle-1 According to the present invention, since a circuit can be configured with one AD converter, reset noise of a solid-state image pickup device can be removed with an inexpensive circuit having N number of configurations.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment in which the present invention is applied to a reset noise removal circuit for a COD image sensor. FIG. 2 is a timing chart showing the operation of the circuit shown in FIG. m1. Figure fJ113 is a circuit diagram showing an example of a reset noise removal circuit for a conventional COD image sensor. 12, COD image sensor 14, clamp circuit 16, sample hold circuit 18, AD converter 20, pulse generation circuit 22, capacitor 24, power supply φR1, Reset pulse φC... Clamp noggle φSR... Sample hold pulse φAD, AD conversion pulse Patent applicant Fuji Photo Film Co., Ltd. Agent Writer Takao Sakiyama Takao Figure 1 Figure 2 Figure 3 So+

Claims (1)

[Claims] 1. In a processing circuit that removes reset noise caused by a reset pulse of the solid-state image sensor from a signal output from the solid-state image sensor in response to a clock pulse, the circuit includes the following steps: a reset pulse generating means that generates a reset pulse with a phase advance from a trailing edge; a clamping means that clamps a reference signal portion in each pixel period of the signal output from the solid-state imaging device to a clamp voltage; a clamp voltage supply means for supplying a voltage; and an image signal output that compares an image signal portion in each pixel period of the signal clamped by the clamp means with the clamp voltage supplied from the clamp voltage supply means. output processing for a solid-state image sensor, characterized in that the image signal output means corrects the level of the image signal portion in each pixel period according to the clamp voltage to obtain reset noise removed. circuit. 2. In the circuit according to claim 1, the image signal output means includes sample and hold means for sampling and holding an image signal portion in each pixel period of the signal clamped by the clamping means; A solid state device comprising an AD converting means for AD converting a signal sampled and held by the holding means, and the AD converting means inputs the clamp voltage supplied from the clamp voltage supply means to a reference potential terminal. Image sensor output signal processing circuit.