JPH0723014A - Time slot signal phase alligner device - Google Patents

Abstract

PURPOSE:To realize the time slot signal phase aligner device which can absorb a frame phase difference between all channels (time slot units), at the time of data multiplex communication, and dispenses with giving control information between each device for executing a communication. CONSTITUTION:A frame synchronizing code is inserted periodically into all time slots of transmitting data in which plural data are multiplexed by a frame/ multi-frame synchronizing code inserting part 11, and also, a multi-frame synchronizing code for specifying the time slot of the frame synchronizing code is inserted into a specific time slot, and from in the time slot of received data containing these synthronizing codes, the multi-frame synchronizing code is detected from a multi-frame synchronization detecting part 19. In a frame detecting part 20, a frame phase of all time slots is detected, based on this multi-frame synchronizing code, and the frame alignment of the received data is executed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time slot signal phase aligner, and more particularly to a digital signal for facsimile etc. in a 0th order group such as a 64 kbps telephone line.
The present invention relates to a time slot signal phase aligner device which is suitable for constructing a facsimile signal demodulation / multiplexing device by establishing inter-frame phase synchronization when multiplexed on a primary group line such as 544 Mbps.

[0002]

2. Description of the Related Art FIG. 7 shows, for example, Japanese Patent Publication No. 2-58940.
FIG. 1 is a block diagram of a conventional time slot signal phase aligner device disclosed in Japanese Patent Publication, particularly showing a configuration of a multi-frame control unit inside a time division multiplexing device having a frame synchronization control function. In the figure, 51 is a transmission data bus for passing transmission data from a terminal side (not shown) to a line interface side (not shown), 52 is a reception data bus for passing reception data from the line interface side to the terminal side, and 1 is transmission Data bus 5
1, a time slot converter connected to the reception data bus 52 for performing a multiplexing process, 2 a call path memory for converting 8 kbps × N data and 0.4 kbps × N data, 3 a call path controller, 4 Multiframe synchronization insertion unit, 5 is a forced signal processing unit that inserts a dummy signal "1" into a bit of an unused channel, and 6 is a selection whether multiframe synchronization is taken or not taken as input data to the channel memory 2. Selector 7 for performing a multi-frame memory 7
1, a multi-frame synchronization detector 72 and a multi-frame memory controller 73.

Next, the operation of the above-described structure will be described.

First, the processing on the transmitting side will be described.

From a plurality of external terminals, for example, 8 kbps
And a plurality of transmission data of different speeds of 0.4 kbps are given via the transmission data bus 51.

The transmission data given in this way is
It is written in the speech path memory 2 for exchanging data in the form of 8 kbps × N and 0.4 kbps × N.

Next, under the control of the speech path control unit 3, a switching operation is performed between frames in a time slot unit (64 kbps signal).

After this, the multi-frame sync bit is inserted by the multi-frame sync inserter 4 into a required location.

Next, the compulsory signal processor 5 sets "1" to all unused bits of each frame, and the transmission data bus 5
1 to the line interface side.

Next, the processing on the receiving side will be described.

The received data from the line interface is input to the multi-frame control section 7 via the received data bus 52 after frame synchronization is established. Data for which multi-frame synchronization is required is once written in the multi-frame memory 71, and the multi-frame synchronization detecting section 72 detects the synchronization.

By performing the above-described processing on a plurality of channels and controlling the writing of the multi-frame synchronization detector 72 based on the results, multi-frame alignment of signals for each channel is performed. By the way, these controls are performed by the multi-frame memory control unit 73.
Done in.

As described above, the data subjected to the multi-frame alignment is selected by the selector 6 from the data not requiring the multi-frame alignment. Next, data is exchanged in the channel memory 2,
After that, the data for each terminal is inversely converted into a time slot and sent to the terminal side interface via the reception data bus 52.

[0014]

Since the conventional time slot signal phase aligner device is configured as described above, when the multiframe synchronization bit is inserted from the multiframe synchronization insertion unit 4 into the transmission data, the insertion is performed. It is necessary to predetermine the position on a channel-by-channel basis by the other device with which it communicates, and it is necessary to hold these pieces of information with each other and operate under this information. There is the complexity of exchanging information.

The present invention has been made in order to solve the above-mentioned problems, and can absorb the frame phase difference between all channels (in units of time slots), and control information can be transmitted between the communicating devices. An object of the present invention is to provide a time slot signal phase aligner device which can be effectively applied to facsimile signal demodulation / multiplexing without the need to provide it.

[0016]

In order to achieve the above object, the present invention provides, as an apparatus according to claim 1, a frame synchronization code is inserted into a time slot of transmission data over each frame and the frame is A multi-frame sync code insertion means for inserting a multi-frame sync code for specifying a time slot of the sync code into a specific time slot, and a frame phase of all time slots based on the multi-frame sync code included in the time slot of the reception data. There is provided a time slot signal phase aligner device comprising: a phase detecting means for detecting the signal, and a buffer means for performing frame alignment based on the output of the phase detecting means.

It is also preferable to insert the frame synchronization code so as to rotate not for all frames but for each multi-frame.

In order to achieve the above object, the present invention further provides, as an apparatus according to claim 3, a facsimile signal demodulating / multiplexing means for demodulating facsimile signals from a plurality of facsimiles and multiplexing them. A signal block generation unit that multiplexes the output of the facsimile signal demodulation / multiplexing unit into a module frame, and a frame synchronization code that is periodically inserted into all time slots of the transmission data from the signal block generation unit and the frame. A multi-frame sync code insertion means for inserting a multi-frame sync code for specifying a time slot of the sync code into a specific time slot, and a frame phase of all time slots based on the multi-frame sync code included in the time slot of the reception data. And phase detection means for detecting Time slot signal including buffer means for performing frame alignment based on the output, and facsimile signal separating / modulating means for separating a facsimile signal from the output signal of the buffer means, modulating the modulated facsimile signal and sending the modulated signal to a plurality of facsimile devices. A phase aligner device is provided.

In order to achieve the above object, the present invention further provides a time slot signal phase aligner apparatus according to claim 1 as the apparatus according to claim 4, wherein the phase detecting means is a multi-frame synchronization code. A multiframe synchronization detection unit that detects and identifies a time slot including a frame synchronization code, a selector that extracts the time slot identified by the multiframe synchronization detection unit, and a time slot extracted by the selector The present invention provides a time slot signal phase aligner device including: a frame detection unit that detects and outputs the frame phases of all time slots based on a frame synchronization code.

In order to achieve the above object, the present invention further provides a time slot signal phase aligner device according to claim 3 as the device according to claim 5, wherein the frame detecting section is configured to detect the detected frame phase. By including a frame phase storage memory for holding a predetermined number of, by simultaneously supplying a plurality of frame phases to the buffer means,
The present invention provides a time slot signal phase aligner device characterized in that the buffer means simultaneously performs frame alignment of a plurality of time slots.

[0021]

In the above means, the time slot signal phase aligner apparatus according to claim 1 of the present invention is arranged such that a frame is spread over each frame through a sync code inserting means in a time slot of transmission data in which a plurality of data are multiplexed. Insert a synchronization code and insert a multi-frame synchronization code for specifying the time slot of the frame synchronization code in a specific time slot, and from among the time slots of the reception data including these synchronization codes,
Through the phase detection means, the multi-frame synchronization code is detected, the frame phases of all the time slots are detected based on this multi-frame synchronization code, and the buffer means performs the frame alignment of the received data based on the output of the phase detection means. To do.

The frame synchronization code can be inserted so as to rotate every multi-frame.

In the above means, the time slot signal phase aligner apparatus according to the third aspect of the present invention demodulates the multiplexed facsimile signal by the facsimile signal demodulating / multiplexing means and the module frame by the signal block generating means. A multi-frame synchronization code for generating transmission data by multiplexing the transmission data into the transmission data, periodically inserting the frame synchronization code into all the time slots of this transmission data through the synchronization code inserting means, and specifying the time slot of the frame synchronization code. Is inserted in a specific time slot, the multi-frame sync code is detected from the time slot of the reception data including these sync codes by the phase detection means, and all the time is detected based on this multi-frame sync code. Detect frame phase of slot In the buffer means, the received data is frame-aligned based on the output of the phase detecting means, and the facsimile signal separating / modulating means separates the facsimile signal from the output signal of the buffer means, and modulates the facsimile signal to obtain a plurality of facsimile devices. Send to.

According to the fourth aspect of the present invention, the multi-frame synchronization detector detects the multi-frame synchronization code, and the selector extracts the time slot containing the frame synchronization code. Therefore, it is possible to efficiently perform frame alignment.

According to the fifth aspect of the invention, the frame phase storage memory holds a plurality of frame phases. Therefore, the buffer means can efficiently perform frame alignment.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

Example 1. 1 is a block diagram of a time slot signal phase aligner apparatus according to a first embodiment of the present invention. In the figure, 11 is a frame / multi-frame sync code inserting section for inserting a frame sync code into each multiplexed time slot, 12 is a frame / multi-frame counter for generating a frame phase of the frame sync code, and 13 is a frame / multi-frame counter. Frame counter 12
Sync code insertion control section for deciding the timing of inserting the frame sync code according to the movement of the frame, 14 is a line frame signal addition section included in the digital primary group frame format, and 15 is a data reception buffer for temporarily storing received data. , 16 is a line frame synchronization detecting unit for detecting a line frame code, 17 is a time slot frame alignment buffer for storing received data in line frame synchronization, 18 is a selector for extracting a time slot required to extract a sync code, Reference numeral 19 is a multi-frame synchronization detection unit that detects a multi-frame synchronization code included in a reference time slot, 20 is a frame detection unit that extracts the synchronization code from the least significant bit of the data of the time slot and performs frame synchronization, and 21 is a frame From the detection unit 20 A frame phase memory for storing the frame phase information of each time slot, 100 is a digital primary group transmission signal line having a transmission rate of 2.048 Mbps, and 101 is a digital primary group having a transmission rate of 2.048 Mbps. It is a reception signal line.

The operation of the above arrangement will be described.

FIG. 2 is an explanatory diagram showing an example of a transmission format in which a frame synchronization code is inserted in the configuration of FIG. In the figure, 31 is a time slot (TS0) of a frame signal of a 2.048 Mbps digital primary group signal, and 32 is a first time slot (TS1).
Then, a reference time slot including a multi-frame synchronization code that serves as a reference for frame phase adjustment of the subsequent time slots, 33a to 33i are 29 time slots (TS
2 to TS15, TS17 to TS31), and 34 are signaling signal time slots (TS16) for transmitting signaling information of the digital primary group.

In the transmission frame format shown in FIG. 2, one multiframe indicates 2 msec,
Meanwhile, 16 PCM frames are transmitted.

FIG. 3 shows the structure of the frame sync code 40 and the multi-frame sync code 41 used in the format of FIG.

As shown in FIG. 3, the frame synchronization code 40 is made up of 16 bits, and 16 bits per bit.
It is inserted into the least significant bit of the same time slot in sequence over a number of times, that is, for 2 msec. The frame / multi-frame counter 12 in the configuration of FIG.
Then, each timing of the frame of the 2 msec cycle indicated by the frame synchronization code 40 and the multi-frame of 128 msec indicating that the frame is repeated 64 times is generated.

On the other hand, as can be seen from FIG. 2, the frame structure is made up of 32 time slots including the frame signal time slot 31 and the signaling signal time slot 34 of the line, and multi-frame synchronization of 128 msec corresponds to the time slot. The time of 4 msec divided by "32" corresponding to the total number can be applied to the insertion of the frame synchronization code in each time slot.

Under the control of the synchronization code insertion controller 13 in the configuration of FIG. 1, the frame signal time slot 31
The frame synchronization code 40 for each frame is inserted into each time slot from (TS0) to time slot 33i (TS31) through the frame / multi-frame synchronization code insertion unit 11 for 4 msec. However,
With respect to the reference time slot 32 (TS1), the frame synchronization code 40 is inserted over all the multiframes (128 msec), and the multiframe synchronization code 41 is inserted every 128 msec to set the frame alignment reference timing.

On the other hand, the frame signal time slot 31
(TS0) and signaling signal time slot 34
(TS16) is transmitted from the circuit frame signal adding unit 14 having the configuration of FIG. Since frame information and signaling information conforming to 703 are added, the frame synchronization code 40 is not inserted.

The transmission data generated as described above is sent to the digital primary group transmission signal line 100.

Received data from the digital primary group reception signal line 101 is temporarily stored in the data reception buffer 15 and, at the same time, in the line frame synchronization detection unit 16.
CCITT Recommendation G.3 included in the frame signal time slot 31 (TS1). 703-compliant frame synchronization is established. The line frame synchronization detecting unit 16 outputs the reception data stored in the data reception buffer 15 in the order of time slot numbers based on the established frame synchronization.

The signals of the respective time slots 33a to 33i arranged in the order of time slot numbers are stored in the time slot frame alignment buffer 17. Among them, the signal of the reference time slot 32 (TS1) is also sent to the multi-frame synchronization detecting section 19 and the multi-frame synchronization code 41 is detected to establish the multi-frame synchronization as shown in FIG. Used for.

On the other hand, each of the other time slots 33a to 33
The signal of i is also sent to the selector 18, but here,
Under the control of the multi-frame sync detector 19, a time slot signal in which a frame sync code 40 is inserted,
That is, only one of the time slots 33a to 33i is selected.

For example, if the received data is the data corresponding to the multi-frame 4 or the multi-frame 5 of the transmission format shown in FIG. 2, the time slot 3
Frame synchronization code 4 in the least significant bit of 3a (TS2)
Contains 0. This is detected by the frame detection unit 20 to establish frame synchronization. This frame phase is matched with the frame phase detected from the frame synchronization code 40 included in the reference time slot 32 (TS1) as a reference, and what is represented by these phase differences is stored in the frame phase storage memory 21. .

Therefore, the frame phase storage memory 21
Stores frame phase information for 30 time slots.

By writing the signals of the respective time slots 33a to 33i in the time slot frame alignment buffer 17 based on the respective frame phase information, the frame phases of all the time slots 33a to 33i can be aligned.

Example 2. FIG. 4 is a block diagram of a time slot signal phase aligner device according to a second embodiment of the present invention, and particularly illustrates a case where it is applied to facsimile signal demodulation and multiplexing. In the figure, reference numeral 200 denotes a facsimile signal demodulating / multiplexing apparatus. In addition to the configuration of FIG. 1, a facsimile signal demodulating / multiplexing section 201 and a signal block generating section 202 are added to the transmitting side, and a facsimile signal separating / modulating section is provided. The unit 203 is added to the receiving side.
The facsimile signal demodulating / multiplexing unit 201 includes a plurality of facsimile signal demodulators. Also, the signal block generation unit 202 outputs the multiplexed facsimile signal to 1
Divide into blocks of 6 kbps signal. On the other hand, the facsimile signal separation / modulation unit 203 has a function of separating the facsimile signal stored in the signal block and modulating it.

The operation of the configuration described above will be described below.

9.6 kbps, 7.2 kbp transmitted from a facsimile terminal connected to a plurality of telephone lines
A facsimile signal having a transmission rate of s or 4.8 kbps is transmitted by the facsimile signal demodulating / multiplexing unit 20.
1 and a facsimile signal demodulator of the multi-frame memory 71 to demodulate into a source signal corresponding to each transmission rate,
The facsimile signal module frame 211 as shown in the explanatory view of FIG. 5 is multiplexed.

Further, as shown in the explanatory view of FIG. 6, the facsimile signal module frame 211 is divided into 32-bit unit signal blocks 212 and placed in each time slot.

Here, the block 1 of the signal block 213 (TS1) includes a frame synchronization code 40 and a multi-frame synchronization code 41 which are reference frames. Further, as in the case of the configuration of FIG. 1, the sync code insertion unit 13 controls the signal block 212 so as not to be placed on the block 4 of the time slot in which the frame sync code 40 is inserted in the least significant bit. It

Further, the facsimile signal separation / modulation unit 20
3, in the same manner as the configuration of FIG. 1, the signal block 212 included in each time slot signal subjected to frame alignment of each time slot is controlled under the control of the multi-frame sync detecting unit 19 and the time including the frame sync code 40 is set. While discarding the information in the block 4 of the slot, the module frame 211 is reconstructed to separate the facsimile signal /
The modulation unit 203 modulates the signal so that it can be transmitted to each facsimile terminal through the telephone line.

As described above, since the frame synchronization code is periodically inserted into all the time slots so as to establish the frame synchronization, the signal phase between the time slots is time-divided by the time division multiplexer installed in the transmission line. Even if the deviation occurs, signal transmission of, for example, 63.75 kbps × N becomes possible.

On the other hand, by applying the time slot signal phase aligner function to the facsimile signal demodulating / multiplexing apparatus, the phase between the time slots generated there even through the time division multiplexing apparatus which does not guarantee the signal transmission of 64 kbps × N. A facsimile signal can be correctly transmitted without being affected by the shift.

[0051]

As described above, according to the present invention, the frame synchronization code is periodically inserted in all the time slots of the signals to be multiplexed. It is not necessary to decide the position to insert the multi-frame sync bit on a channel-by-channel basis.
In the transmission path handling the next group of signals, there is an effect that the signal phase shift for each time slot generated by time division multiplexing processing or the like can be effectively absorbed and a high transmission speed can be supported.

[Brief description of drawings]

FIG. 1 is a block diagram of a time slot signal phase aligner device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of a transmission format applied to the configuration of FIG.

FIG. 3 is an explanatory diagram of a frame synchronization code and a multi-frame synchronization code.

FIG. 4 is a block diagram of a time slot signal phase aligner device according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a facsimile signal module frame.

FIG. 6 is an explanatory diagram of a transmission format including a facsimile signal.

FIG. 7 is an explanatory diagram of a conventional time slot signal phase aligner device.

[Explanation of symbols]

 1 time slot conversion unit 2 speech path memory 3 speech path control unit 4 multiframe synchronization insertion unit 5 forced signal processing unit 6 selector 7 multiframe control unit 11 frame / multiframe synchronization code insertion unit 12 frame / multiframe counter 13 synchronization code Insertion control unit 14 Line frame signal addition unit 15 Data reception buffer 16 Line frame synchronization detection unit 17 Time slot frame alignment buffer 18 Selector 19 Multi frame synchronization detection unit 20 Frame detection unit 21 Frame phase storage memory 51 Transmission data bus 52 Reception data bus 71 multi-frame memory 72 multi-frame synchronization detection unit 73 multi-frame memory control unit 200 facsimile signal demodulating / multiplexing device 201 facsimile signal demodulating / multiplexing unit 202 signal Block generating unit 203 facsimile signal separation / modulation unit

Claims (5)

[Claims] 1. A sync code insertion for inserting a frame sync code over each frame in a time slot of transmission data and a multi-frame sync code for specifying a time slot of the frame sync code in a specific time slot. Means, phase detecting means for detecting frame phases of all time slots based on a multi-frame synchronization code included in the time slot of the received data, and buffer means for performing frame alignment based on the output of the phase detecting means, A time slot signal phase aligner device comprising: 2. A frame synchronization code is inserted into a time slot of transmission data so as to rotate every multiframe, and a multiframe synchronization code for specifying the time slot of the frame synchronization code is inserted into a specific time slot. Synchronization code insertion means, phase detection means for detecting the frame phase of all time slots based on the multi-frame synchronization code included in the time slot of the received data, and frame alignment based on the output of the phase detection means. Buffer means and a time slot signal phase aligner device. 3. Facsimile signal demodulation / multiplexing means for demodulating facsimile signals from a plurality of facsimiles and multiplexing them, and signal block generation for multiplexing the output of said facsimile signal demodulation / multiplexing means into a module frame. And a multi-frame synchronization code for specifying a time slot of the frame synchronization code in a specific time slot, while periodically inserting a frame synchronization code in all time slots of the transmission data from the signal block generation means. Sync code insertion means for inserting, phase detection means for detecting the frame phase of all time slots based on the multi-frame synchronization code included in the time slot of the received data, and frame alignment based on the output of the phase detection means. The buffer means for performing the And a facsimile signal separating / modulating means for separating a facsimile signal from the output signal of the delay means, modulating the modulated signal, and sending the modulated signal to a plurality of facsimile apparatuses. 4. The time slot signal phase aligner device according to claim 1, wherein the phase detecting means detects a multiframe synchronization code and identifies a time slot including the frame synchronization code, A selector for extracting the time slot specified by the multi-frame synchronization detection unit, and a frame for detecting and outputting the frame phase of all time slots based on the frame synchronization code included in the extracted time slot by the selector. A time slot signal phase aligner device comprising: a detector. 5. The time slot signal phase aligner apparatus according to claim 3, wherein the frame detection unit includes a frame phase storage memory that holds a predetermined number of the detected frame phases, and the plurality of frame phases are simultaneously buffered by the buffer. A time slot signal phase aligner device, wherein said buffer means simultaneously performs frame alignment of a plurality of time slots by supplying the time slot signal to said means.