JPH05236055A - Isdn terminal adaptor - Google Patents

Abstract

PURPOSE:To conduct bulk transfer without revision of a communication protocol at a data terminal equipment and a protocol at an ISDN line network without need of an excess connection wait time by clarifying a data start timing when plural B channels are simultaneously in use. CONSTITUTION:An accommodated data terminal equipment is connected to an ISDN line network via a line interface 6 and plural information channels are transferred altogether. Data of the data terminal equipment are multiplexed/ demultiplexed by a multiplexer circuit 7 and a demultiplexer 1 respectively, and a data arrival time due to a difference from B-channel connection line routes is corrected, then, specific training pattern data whose transmission frame number is a predetermined fixed value are generated by pattern coders 3, 4. Pattern decoders 9, 10 detect the B-channel connection delay based on the specific training pattern data. The data connection delay is corrected by control processing of a control processor 13 or the like based on the detected delay.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to two or more 64 Kb /
The present invention relates to an ISDN terminal adapter device used for bulk transfer in which each line route delay of an information channel is compensated and bundled into one.

[0002]

2. Description of the Related Art A conventional ISDN terminal adapter device of this type includes a separation circuit for separating transmission data from a data terminal, a pattern encoder for repeatedly transmitting pattern data in which a specific pattern is assigned to a multiframe, and a pattern. It has a switching circuit for switching between data and normal data.

Further, a line interface for performing demultiplexing and speed conversion (hereinafter referred to as a line I / F as necessary), a switching circuit for switching a received information channel between pattern data and normal data, and a B1 channel Alternatively, a variable delay circuit that inserts a shift register having an arbitrary length into either of the B2 channels and a multiplexed circuit that sends two delayed 64 Kb / s signals as received data of 128 Kb / s to a data terminal It is provided with a circuit and a pattern decoder that decodes and decodes pattern data to detect multiframe synchronization and extract a frame number and notify the control processor and the like. Further, it has a LAPD processing unit of Layer 2 for extracting or inserting an information message to the signal channel D, a control processor for operating according to a predetermined sequence, and the like.

Next, the operation of such a configuration will be described. For the sake of convenience, the two 64 Kb / s are changed to 128 Kb / s.
The case of bundling in s will be described.

FIG. 4 shows a sequence of operations on the transmitting side and the receiving side. In FIG. 4, first, the transmitting side will be described. When a data transmission instruction of 128 Kb / s is received from a data terminal (not shown), two consecutive call setup messages are transmitted to the ISDN line network based on the ISDN call setup procedure. When the confirmation of the response to each call setup message is received, it is determined that the two lines have been secured. The transmitting side starts transmitting the training pattern data according to the frame configuration example of FIG. 5 in order to compensate the delay of the B channel on the receiving side. That is, 1 bit of the training pattern data is put on the 8th FA bit of each frame (8 bits). Therefore, 1
Combine the FA bits of 28 (= 8 × 16) frames to 1
It becomes a multi-frame cycle (= 16 msec).

On the other hand, since training pattern data for B channel delay compensation is also sent from the receiving side, when this received signal is detected, pattern decoding is started,
When the complete multi-frame pattern is received, a sync detect signal is sent to the control processor. That is, as shown in the frame configuration example of FIG. 5, it is considered that the synchronization is detected by detecting the horizontal synchronization pattern for each sub-multiframe and detecting the vertical synchronization pattern extending over each multi-subframe.

Next, the control processor that has received the notification calculates the relative frame difference between the two B channels by taking the difference between the frame counter values obtained from the decoders for each channel, and switches in the variable delay circuit. The delay correction is completed by setting the value in the switching and variable shift register.

When the delay correction is completed in this way, the transmission side inverts the A bit shown in FIG. 5 from 0 to 1 as a notification of the transmission preparation completion to the reception side. Here, the A-bit is inverted and transmitted from the receiving side as a delay correction completion notification. By detecting this A bit, the completion of delay correction on the receiving side can be determined, and the transmitting side enters the data communication phase and starts transmitting the transmission data. When the transmission of the transmission data is completed, the transmission side ends the transmission, and the reception side also ends the reception.

Next, the receiving side will be described. When receiving two consecutive call setup messages from the ISDN line network, an incoming call instruction is sent to a data terminal (not shown). When receiving the incoming call from the data terminal, the receiving side sends a response to the ISDN line network, and when both channels receive confirmation of the response from the network, it is confirmed that two B channels are secured. Send training pattern data to the channel. On the other hand, when the training pattern data is received from the transmitting side, the pattern decoding is started, and the synchronization is established and the delay is corrected as in the transmitting side. After the delay correction is completed, the A bit is inverted from 0 to 1. When the inversion of the A bit from the transmitting side is detected, the receiving side enters the data transfer phase and waits for received data. Here, the delay correction operation will be described on the received signal timing with reference to FIG.

For example, consider the case where the B2 channel is delayed as compared with the B1 channel as shown in FIG. In FIG. 6, the B1 channel is synchronized with the multiframe number (hereinafter, referred to as MF if necessary) 4, and the B2 channel is M.
It is assumed that synchronization is achieved in F1.

Sync detection is performed twice on the B1 channel,
After that, MF6 is extracted on the B1 channel and MF3 is extracted on the B2 channel, and the MF and the frame number (hereinafter, referred to as FR if necessary) are extracted. The relative delay amount (the number of frames) is found by subtracting them.

Although only one direction of data transmission has been described above, the same applies to the opposite direction.

[0013]

Therefore, in the ISDN terminal adapter device of the conventional example, a part of the data may be lost due to the deviation of the connection timing of the data between the transmitting side and the receiving side. Therefore, after confirming the delay correction, there is an inconvenience that the data transfer is started with a sufficient time by a timer or the like, or an end-to-end data transfer confirmation procedure between the data terminals is required.

The present invention solves such a conventional problem by clarifying the data start timing when using a plurality of B channels at the same time, requiring no extra connection waiting time, and An object is to provide an excellent ISDN terminal adapter device capable of bulk transfer without changing the communication protocol on the terminal side or the protocol on the network side.

[0015]

In order to achieve this object, the ISDN terminal adapter device of the present invention has a line interface for connecting the accommodated data terminal device to the ISDN line network and bundles a plurality of information channels. Transfer I
An SDN terminal adapter device for demultiplexing and demultiplexing data with the data terminal device, and B
When correcting the data arrival time due to the difference in channel connection line routes, pattern code generating means for generating specific training pattern data in which the number of transmission frames is a predetermined fixed value, and B channel of the specific training pattern data by the specific training pattern data. It is characterized by comprising pattern decoding means for detecting the connection delay amount and data delay correction means for correcting the connection delay of the data with the detected delay amount.

[0016]

Therefore, in the ISDN terminal adapter device of the present invention, the number of transmission frames of training pattern data for synchronization detection and delay correction is set to a predetermined fixed value, so that data transmission is started on both the transmitting side and the receiving side. The timing is clear, no extra connection waiting time is required, and bulk transfer is possible without changing the communication protocol on the data terminal side or the protocol on the network side.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the ISDN terminal adapter device of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of the embodiment. In addition,
For convenience, a case where two 64 Kb / s are bundled into 128 Kb / s will be described.

In FIG. 1, 1 is a separation circuit for separating transmission data from a data terminal (not shown), which is 128K.
The b / s transmission data is separated into two 64 Kb / s signals.

Reference numerals 3 and 4 denote pattern encoders, which repeatedly transmit pattern data in which a specific pattern is assigned to a multi-frame having 1 cycle of 8 bits and 1 frame of 128 frames. Here, 1 frame = 125 μsec, and 1 multiframe = 16
It becomes msec. Here, the line route delay time is 325 msec at maximum in consideration of satellite communication, and therefore 32 multiframes are set to one cycle for convenience.

Reference numeral 5 is a switching circuit for switching between pattern data and normal data, and 6 is an ISDN in which signals are multiplexed.
It is a line interface that performs demultiplexing and speed conversion between the line and the transmission information channels B1 and B2, the reception information channels B1 and B2, and the signal channel D. Reference numeral 8 denotes a variable delay circuit which inserts a shift register having an arbitrary length according to the delay amount into either the B1 channel or the B2 channel under the control of the control processor 13. This internal variable shift register can transmit a 64 Kb / s signal at a maximum of 325 mse.
It requires a capacity of 20.8 kbit for delaying c.

The two 64 Kb / s signals output from the variable delay circuit 8 are 128 Kb / s by the multiplexing circuit 7.
The received data is multiplexed and sent to the data terminal.

Reference numerals 9 and 10 denote pattern decoders which decode and decode pattern data to detect multiframe synchronization and extract frame numbers, and notify the control processor. 1
Reference numeral 1 is a switching circuit for switching a received information channel between pattern data and normal data, and 12 is a layer 2 LAPD process for extracting or inserting an information message into a signal channel D separated by a line I / F 6. The LAPD processing unit. 13 controls each block,
A control processor that operates according to a defined sequence.

Next, the operation of this configuration will be described.
FIG. 3 shows an operation sequence. In FIG. 3, first, the transmission side will be described. From a data terminal (not shown) 1
When a data transmission instruction of 28 Kb / s arrives, two consecutive call setup messages are sent to the ISDN line network based on the ISDN call setup procedure. When the confirmation of the response to each call setup message is received, it is determined that the two lines have been secured.

In order to compensate the delay of the B channel on the receiving side, the transmitting side starts transmitting the training pattern data according to the frame structure example of FIG. 5 described above. In this case, the time taken for each to reach the other party will differ depending on the connected line route. When one uses the satellite line and the other uses the terrestrial line, a maximum arrival delay of 325 msec occurs between the respective lines. If one multi-frame of the training pattern data is set to 16 msec, it is necessary to transmit at least 22 multi-frame training pattern data. That is, 16 msec × 22 = 352 ms
ec> 325 msec, and at least 325 mse
After c, the training pattern data has reached both channels, and the delayed channel is 16 ms after that.
Since synchronization is established after ec, as a result, the delay amounts of both channels can be determined. 325msec + 16msec =
341 msec is necessary and sufficient for delay correction.

Here, for convenience of explanation, the number of frames is 22 multiframes, and the transmitting side starts transmitting the transmission data immediately after the transmission of 22 multiframes is completed. When the transmission of the transmission data is completed, the transmission side ends the transmission.

On the other hand, immediately after receiving the training pattern data from the receiving side, the timer T1 is started and the delay correction is started. If the A bit 1 from the receiving side cannot be received before the T1 time-out, it is considered that the delay correction cannot be performed on the receiving side, and the recovery procedure is immediately performed.

Next, the receiving side will be described. When receiving two consecutive call setup messages from the ISDN line network, an incoming call instruction is sent to a connected data terminal (not shown). When receiving the incoming call acceptance from the data terminal, the receiving side receives I
When a response is sent to the SDN line network and both channels receive confirmation of a response from the network, it is confirmed that two B channels are secured, and training pattern data is sent to each B channel. On the other hand, when the training pattern data is received from the transmitting side, the pattern decoding is started, and the synchronization is established and the delay is corrected as in the transmitting side. After the delay correction is completed, the A bit is inverted from 0 to 1, and if the transmission training pattern data in this case is within 22 frames, up to 22 frames are transmitted, and if it is 22 frames or more, the transmission of the training pattern data is immediately stopped. .. Immediately after receiving 22 frames of the received training pattern data, the system waits for data reception and receives the received data. However, if synchronization cannot be established and delay correction cannot be performed on both channels within 22 frames, the recovery procedure is immediately entered and the B channel is released.

[0029]

As is clear from the above description, since the ISDN terminal adapter device of the present invention sets the number of training pattern data transmission frames for synchronization detection and delay correction to a predetermined fixed value, The start timing of data transfer is clear on both the receiving side and the receiving side,
There is an effect that bulk transfer can be performed without requiring an extra connection waiting time and without changing the communication protocol on the data terminal side or the protocol on the network side.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration in an embodiment of an ISDN terminal adapter device of the present invention.

FIG. 2 is an explanatory diagram showing a bit configuration in each frame, which is used for explaining the operation of the embodiment.

FIG. 3 is a sequence diagram on the transmitting side and the receiving side used for explaining the operation of the embodiment.

FIG. 4 is an operation sequence diagram of a transmitting side and a receiving side in a conventional ISDN terminal adapter device.

FIG. 5 is an explanatory diagram showing a configuration of a multi-frame or the like used for explaining the operation of a conventional example.

FIG. 6 is an explanatory diagram for explaining the operation of the conventional example and for explaining the operation of delay correction.

[Explanation of symbols]

 1 Separation Circuit 3, 4 Pattern Encoder 5, 11 Switching Circuit 6 Line Interface 7 Multiplexing Circuit 8 Variable Delay Circuit 9, 10 Pattern Decoder 13 Control Processor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H04M 11/00 303 8627-5K

Claims (1)

[Claims] 1. An ISDN terminal adapter device which has a line interface for connecting the accommodated data terminal device to an ISDN line network, and which transfers a plurality of information channels in a bundle, wherein data is multiplexed with the data terminal device. Demultiplexing means for demultiplexing, and pattern code generating means for generating specific training pattern data in which the number of transmission frames is a predetermined fixed value when correcting the data arrival time due to the difference in connection channel route of B channel An ISDN terminal adapter comprising: a pattern decoding means for detecting a connection delay amount of B channel based on the specific training pattern data; and a data delay correction means for correcting a data connection delay by the detected delay amount. apparatus.