JP2002111619A - Carrier relay signal transmitting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a carrier relay signal transmitting system the delay time of which becomes an allowable value or smaller and can accommodate many channels for carrier relay signals. SOLUTION: The carrier relay signal transmitting system is provided with a reception memory, a first writing means which writes the carrier relay signals in the reception memory, and a first clock generating means which generates a second clock which is equal to the transmitting speed of frames. The device is also provided with a second clock generating means which generates a third clock, a staff pulse generating means which generates a staff pulse based on the third clock, and a reading-out means which reads out the carrier relay signals from the reception memory based on the third clock. In addition, the transmitting device is also provided with a frame header generating means which inserts a frame pulse and a staff designating pulse into a frame header, and a multiplexing means which accommodates the carrier relay signal or staff pulse relevant to a channel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a carrier relay signal transmission device for transmitting a carrier relay signal.

[0002]

2. Description of the Related Art A carrier relay system is used for the purpose of protecting a power transmission system. Information such as transmission line current at both ends of a transmission line at the same time is used as a carrier relay signal.
By transmitting and comparing using a communication carrier such as a micro wireless line or an optical fiber line, an abnormality in the power transmission system is detected and necessary processing such as power transmission stop is performed.
Therefore, in the carrier relay system, strict conditions are required for the delay time (for example, within 4 ms) of the signal on the transmission path, and the delay time may fluctuate.
Even if there is a delay time difference between the uplink and the downlink, an error exceeding the allowable level is not allowed.

On the other hand, in a power transmission system, multimedia information such as voice information, image information, and data information other than a carrier relay signal is transmitted between substations using a transmission device. Therefore, it is necessary to construct a wideband ISDN system. In order to construct this broadband ISDN system using a corporate network, the SDH (S
Synchronous Digital Hierarchy) is required,
The carrier relay signal is also transmitted through the SDH transmission path.
It is desired to be able to transmit.

FIG. 17 is a configuration diagram of a carrier relay signal transmission system using a conventional SDH transmission system (prior art 1). As shown in FIG. 17, in the carrier relay signal transmission system 2, a carrier relay signal is transmitted from each of the carrier relay systems 3 # 1i (i = 1 to 7) at a transmission rate of 54 kbps. 1.5MCRM
The UX4 samples a carrier relay signal by multipoint sampling, for example, a three-point sampling method, and stuffs seven carrier relay signals into an asynchronous primary group signal of 1.5 Mbps (54 kbps × 7 × 3). -Multiplex. Multi-point sampling is performed by multiplexing a carrier relay signal in synchronization with a clock at a transmission speed of 50 Mbps on the transmission side. This is to eliminate a timing error due to a phase shift when the carrier relay signal is sampled by the clock on the transmission side.

[0005] The 50M ASM6 # 1 has a 1.5 MCRM
1.5Mbps transmitted from UX4 # 1 or other system
Are multiplexed into a 50 Mbps STM-0 frame. The reason why the information is multiplexed in the STM-0 frame is that information such as voice information, image information, or data information is simultaneously accommodated in the payload of the STM-0 frame together with the carrier relay signal. SDH transmission system 8 #
1 accommodates the STM-0 frame in the payload of the synchronization frame and transmits it to a transmission path such as an optical fiber. The opposite SDH transmission system 8 # 2 separates the synchronization frame from the payload of the synchronization frame into STM-0.

[0006] The 50M ASM6 # 2 separates the STM-0 frame into a 1.5 Mbps asynchronous primary group signal.
1.5MCRMUX4 # 2 is 5 bits from the asynchronous primary group signal.
The signal is separated into 4 kbps carrier relay signals. And
The corresponding carrier relay system 3 # 2i (i = 1 to
Transmit to 7). Carrier relay system 3 # 2i (i
= 1 to 7) receive the carrier relay signal and compare it with the carrier relay signal of the own system to detect an abnormality in the power transmission system and perform necessary processing such as power transmission stop.

FIG. 18 is a configuration diagram of a carrier relay signal transmission system using a conventional SDH transmission system (prior art 2). As shown in FIG. 18, a carrier relay signal is transmitted at a transmission rate of 54 kbps from each carrier relay system 3 # 1i (i = 1 to 3). The multipoint sampling synchronizer 22 # i (i = 1 to 3) samples a carrier relay signal by multipoint sampling, for example, a three-point sampling method, and stores the sampled signal in a 192 kbps frame. Multipoint sampling multiplexes the carrier relay signal in synchronization with the clock on the transmitting side, but since the clock on the transmitting side and the clock on the receiving side are independent, the carrier relay signal synchronized with the clock on the receiving side This is to eliminate a timing error due to a phase shift when the signal is sampled by the clock on the transmission side.
The multiplexing unit 24 converts the 192 kbps multipoint sampled carrier relay signal into 576 kbps (192
k × 3), and transmits to the SDH transmission system as a data communication channel (SDH DCC) during section overhead in the SDH transmission system.

[0008] The SDH transmission system uses the SDH DCC as the section overhead D4 to D12 of the synchronization frame.
(DCC) and the opposite SDH with the payload
Transmit to the transmission system. The opposite SDH transmission system receives the synchronization frame and transmits the 576 kbps SDH.
Transmit DCC. The multiplexing unit receives the SDH DCC, separates it into a carrier relay signal of 54 kbps, and transmits it to the carrier relay system. The carrier relay system receives the carrier relay signal and compares it with the carrier relay signal of its own system, thereby detecting an abnormality in the power transmission system and performing necessary processing such as stopping power transmission.

[0009]

However, the conventional carrier relay system has the following problems.

In the prior art 1, since the payload of the SDH transmission system is used, it is necessary to multiplex to 1.5 Mbps and multiplex to 50 Mbps and to include a plurality of devices before it is accommodated in the SDH transmission system. Therefore, S
An increase in delay time and a decrease in reliability occur before being accommodated in the DH transmission system, and it may be difficult to construct a highly reliable system with a small delay time required in a carrier relay system.

In the prior art 2, the transmission rate when the SDH section overhead D4 to D12 is used is:
Since it is 576 kbps, when SDH synchronization / accommodation by the three-point sampling method is used, only three channels of a 54 kbps Curie relay signal can be accommodated. However, a carrier relay line usually has one transmission line.
The system requires at least two channels (for 1L and 2L transmission) and is not practical because it is difficult to cope with relay lines, multiple terminal lines, multiple power transmission systems and multiple circuits (+ 3L, 4L, etc.). Was.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and has no delay fluctuation between upstream and downstream, has a delay time within an allowable value, and can accommodate a large number of channels of a carrier relay signal. An object of the present invention is to provide a carrier relay signal transmission system.

[0013]

FIG. 1 is a diagram illustrating the principle of the present invention. As shown in FIG. 1, a plurality of reception memories 30 # i
(I = 1 to n), a plurality of first writing units 31 # i (i = 1
To n), a first clock generation unit 32, a second clock generation unit 34, and a plurality of stuff pulse generation units 36 # i (i
= 1 to n), a plurality of first reading means 38 # i (i = 1 to
n), a frame pulse generating means 40, a frame header generating means 42 and a multiplexing means 44. A carrier relay signal is input to the transmission device. The plurality of first writing units 31 # i (i = 1 to n) receive the reception memories 30 # i (i = i = n) in accordance with the first clock synchronized with the carrier relay signal.
1 to n) are written with carrier relay signals.

The first clock generating means 32 generates a second clock equal to the transmission rate of a frame composed of a time slot of a plurality of channels accommodating a frame header and a plurality of carrier relay signals. The second clock generating means 34 generates a third clock having a frequency higher than the frequency of the first clock and equal to the transmission speed of each channel based on the second clock. The plurality of stuff pulse generation means 36 # i (i = 1 to n) generate stuff pulses having a cycle equal to the frequency difference between the first clock and the third clock based on the third clock.

A plurality of first reading means 38 # i (i = 1 to 1)
n) represents a plurality of reception memories 3 based on the third clock.
A plurality of carrier relay signals are read from 0 # i (i = 1 to n). The frame pulse generating means 40 generates a frame pulse indicating the head of the frame based on the second clock. Based on the frame pulse and the second clock, the frame header generating means 42 inserts a pulse indicating the head of the frame and a stuff designation pulse indicating the presence or absence of a stuff pulse accommodated in the channel into the frame header. The multiplexing unit 44 receives the plurality of carrier relay signals and the stuff pulses read from the plurality of reception memories 30 # i (i = 1 to n) based on the third clock.

At this time, the carrier relay signal is written into the reception memory 30 # i (i = 1 to n) in synchronization with the first clock and then read out in synchronization with the third clock. Receiving the carrier relay signal and the stuff pulse, and accommodating the carrier relay signal or the stuff pulse in a plurality of channels based on the second clock and the frame pulse to which the third clock is synchronized, so that the phase shift of the carrier relay signal and the stuff pulse There is no. Therefore, there is no need to perform multipoint sampling of the carrier relay signal, and many carrier relay signals can be accommodated in the frame. Furthermore, there is almost no delay in writing the carrier relay signal to the reception memory 30 # i (i = 1 to n) and reading from the reception memory 30 # i (i = 1 to n). Since there is almost no delay in accommodating, the transmission delay of the carrier relay signal is reduced.

[0017]

FIG. 2 is a configuration diagram of a carrier relay signal transmission system according to an embodiment of the present invention. As shown in FIG. 2, the carrier relay signal transmission system includes a circuit breaker 50 # ij (i = 1, 2, j = 1 to 1).
9), carrier relay system 52 # ij (i = 1,
2, j = 1 to 9), DCC multiplexing / demultiplexing unit 54 # i (i
= 1, 2) and SDH transmission system 56 # i (i = 1, 2)
2) is provided. Circuit breaker 50 # 1i (i =
1 and 2) are provided in a substation, measure transmission line current and output to the carrier relay system 52 # ij, and stop transmission when the carrier relay system 52 # ij detects an abnormality in the transmission line system. And other necessary processing.

When the carrier relay system 52 # ij receives the transmission line current value and the like from the circuit breaker 50 # 1i, the carrier relay system 52 # ij has a constant bit rate and a predetermined interface, for example, 54 kbps and a bipolar signal format.
Transmit a carrier relay signal. Here, the carrier relay transmission system can accommodate a maximum of nine carrier relay systems 52 # ij (j = 1 to 9), and the carrier relay signals are transmitted at a transmission rate of 54 kbps. This is because the carrier relay signal is contained in the DCC of D4 to D12 of 576 kps in the section overhead of the SDH synchronization frame, and control information other than the carrier relay signal is contained in the DCC. The control information includes synchronization control of frames constituting the DCC, control of a stuff bit insertion position inserted to adjust the difference between the transmission speed of the carrier relay signal and the transmission speed of the carrier relay signal accommodated in the DCC (stuffing position). Information such as a designated pulse).

The DCC multiplexing / demultiplexing section 54 # i has the following functions.

(1) Carrier relay system 52 # ij
The clock is extracted from the carrier relay signal transmitted from (j = 1 to 9). The carrier relay signal is written into the reception memory according to the clock.

(2) In synchronization with the transmission reference clock, the carrier relay signal is read from the reception memory according to a transmission timing clock faster than the transmission speed of the carrier relay signal from the carrier relay system 52 # ij. The frequency of the transmission timing clock matches the transmission speed of the carrier relay signal contained in the DCC. The transmission speed of the carrier relay signal accommodated in the DCC is
Of the control information contained in the DCC, the number of channels accommodating the carry relay signal (9 channels), and the like.

(3) Each carrier relay system 52 # i
A stuff pulse is generated at a bit rate corresponding to the difference between the transmission speed of the carrier relay signal transmitted from j and the frequency of the transmission timing clock.

(4) DCC according to the transmission reference clock
Insert control information into the frame header of the frame.

(5) A carrier relay signal or a stuff pulse is multiplexed on each channel of the DCC frame.

(6) Scramble the DCC frame.

(7) Transmission line interface, for example,
The DCC frame is transmitted to the SDH transmission system 56 # i according to the optical interface.

(8) D from SDH transmission system 56 # i
The CC frame is received and descrambled.

(9) The carrier relay signal or the stuff pulse contained in each channel of the DCC frame is separated.

(10) The received DCC frame is destuffed, and a carrier relay signal is written into the transmission memory at the transmission speed of the channel in which the carrier signal is accommodated.

(11) The carrier relay signal is read out from the transmission memory with a clock equal to the transmission speed of the carrier relay signal, and the carrier relay signal is transmitted to each carrier relay system 52 # ij.

FIG. 3 shows the DCC multiplexing / demultiplexing unit 5 in FIG.
FIG. 4 is a configuration diagram of 4 # i. As shown in FIG. 3, the DCC multiplexing / demultiplexing unit 54 # i includes a stuff synchronization unit 70 # ij (j
= 1 to 9), bit synchronization circuit 72 # i, transmission reference clock generation unit 74 # i, transmission timing clock generation unit 76
#I, MUX unit 78 # i, frame pulse generation unit 80 #
i, scrambler 82 # i, IF section 84 # i, IF section 9
0 # i, reception timing clock generator 92 # i, frame synchronization circuit 94 # i, descrambler 96 # i, DM
UX unit 98 # i, destuff synchronization unit 100 # ij (j =
1 to 9) and VCO 100 # i.

The stuff synchronizer 70 # ij has the following functions.

(1) Each carrier relay system 52 # i
j, and receives the carrier relay signal CRTij transmitted from j to extract a reception clock.

(2) The carrier relay signal CRTij is written into the reception memory according to the reception clock.

(3) Transmission timing clock generator 76
The transmission timing clock CLK3i output from #i
, The carrier relay signal is read from the reception memory.

(4) Transmission timing clock CLK3i
And a stuff pulse STFij is generated according to the difference between the clock frequency of the received clock and the received clock.

FIG. 4 shows a stuff synchronizer 70 # i in FIG.
FIG. 7 is a configuration diagram of j. The staff synchronizer 70 # ij receives the B-
U conversion section 110 # ij, clock extraction section 112 # ij,
It has a writing unit 114 # ij, a receiving memory 116 # ij, a reading unit 118 # ij, and a stuff control unit 120 # ij. The BU conversion unit 110 # ij converts a 54 kbps bipolar carrier relay signal CRTij into a unipolar carrier relay signal CRWij.
Clock extraction section 112 # ij performs carrier relay signal C
A 54 kbps clock CLK6ij is extracted from RWij.

Writing section 114 # ij receives clock CLK3
ij, the carrier relay signal is stored in the reception memory 11
Write to 6 # ij. The reception memory 116 # ij is a dual-port memory for writing / reading the carrier relay signal CRWij. The dual port memory is used to perform writing and reading at the same time. Reading section 118 # ij reads carrier relay signal CRRij from reception memory 116 # ij in synchronization with transmission timing clock CLK3i. The stuff control unit 120 # ij transmits the transmission timing clock CLK3
According to the difference between i and the clock frequency of the clock CLK6ij, for example, when the reception memory 116 # ij becomes empty, a stuff pulse STFij is generated.

The bit synchronization circuit 72 # i is connected to the SDH DC
It generates a 576 kbps synchronous clock CLK1i in bit synchronization with the 576 kbps clock TCLK transmitted from the C unit 58 # i. The transmission reference clock generation unit 74 # i generates a transmission reference clock CLK2i of 576 kbps in synchronization with the clock CLK1i generated by the bit synchronization circuit 72 # i. The transmission timing clock generator 76 # i transmits the transmission reference clock CLK2i
Is divided to be greater than 54 kbps and 64 kbp
The transmission timing clock CLK3i having a clock frequency smaller than s (576 kpbs / 9) is generated. The transmission timing clock CLK3i has a frequency equal to the transmission speed of the channel in which the carrier relay signal is accommodated in the DCC frame. Since the transmission speed can be changed by a frame configuration described later, for example, frequency division is easy. It can be determined from the viewpoint of things. For example, the transmission reference clock CLK2i is frequency-divided by 1/10, and
6 kbps.

The MUX unit 78 # i has the following functions.

(1) Transmission timing clock CLK3i
, The carrier relay signal CR2ij (j = 1 to
9) or a stuff pulse STFij (j = 1 to 9)
For example, the data is held in nine shift registers.

(2) FIG. 5 is a diagram showing a DCC frame configuration. As shown in FIG. 5, the DCC frame is G
It has a hierarchical structure of units, G frames, and multiframes. The G unit is composed of, for example, 9 bits. 9
The bit G unit includes a carrier relay signal CRTi
j (j = 1 to 9) or a stuff pulse is accommodated. Hereinafter, each bit is referred to as a carrier relay channel.

The G frame is composed of a G frame header (G) and n G units. The G frame header is used for frame synchronization and multi-frame synchronization.
As well as for controlling stuff pulses. For example, the G frame header is composed of one bit. A frame synchronization pulse, a multi-frame synchronization pulse, and a stuff designation pulse are represented by a bit pattern of a continuous G pulse configured by a value (G pulse) set in a G frame header of the G frame.

For example, “01” is a frame synchronization pulse, “011” is a multi-frame synchronization pulse, and “11”.
1 'is a stuff designated pulse (when stuff is inserted),' 00 '
0 'indicates a stuff designation pulse (when no stuff is inserted). The insertion position of the stuff pulse (hereinafter, stuff channel) that can be accommodated in the channel in which each carrier relay signal is accommodated is specified in advance. The position of the G frame to which the stuff channel is allocated may be common for the nine carrier relay signals, or may be different for each carrier relay signal. For example, as shown in FIG. 5, for the carrier relay signals # 1, # 2,..., # 9, stuff channels may be allocated to different units such as Ga, Gb,. The presence / absence of a stuff pulse is determined based on the bit pattern of the corresponding stuff designation pulse in the multiframe. The number n of the G units constituting the G frame is determined according to the transmission speed of the carrier relay signal (54 kbps), the transmission speed of the frame (576 kbps), and the number of channels of the carry relay signal (9).

A multi-frame is composed of m G frames. The multi-frame configuration is used in order to use the G pulse efficiently by deciding how to use the G pulse of the G frame. Number of G frames m
Is that 9 stuff channels can be allocated in one multiframe, the transmission speed of the stuff channel is a value larger than (the transmission speed of the carrier relay channel−the transmission speed of the carrier relay signal (54 kbps)), and the like. Is determined from the viewpoint of The positions of the multi-frame synchronization, the frame synchronization, and the G pulse containing the stuff designation pulse are fixed in advance in the multi-frame.

MUX unit 78 # i generates the G frame shown in FIG. 3 as follows.

(1) The carrier relay signal CRRij and the stuff pulse STFij read from the reception memory 116 # ij are received in synchronization with the transmission timing clock CLK3i.

(2) The G frame pulse is counted according to the G frame pulse GPi and the transmission reference clock CLK2i, and a pulse corresponding to the multi-frame synchronization and frame synchronization bit pattern is inserted into the G frame header.

(3) When stuff pulse SFTij is output (i) G frame pulse GP1i and transmission reference clock C
In synchronization with LK2i, the corresponding carrier relay signal is accommodated in the corresponding carrier relay channel until the stuff channel corresponding to the stuff pulse STFij. The stuff pulse STFij is stored in the reception memory 116 #
When ij becomes empty, if it is output, it is necessary to accommodate the carrier relay signal at the time T from when the stuff pulse is output until it is accommodated in the stuff channel. For this purpose, a predetermined bit time, for example, one bit, is delayed after the carrier relay signal is read from the reception memory 116 # ij.
One bit delay time is good, the number of bits to be delayed is
(The stuff pulse STFij is output from the stuff control unit 120 # ij that outputs the stuff pulse STFij within the time T.
+1), but the stuff pulse ST
This is because Fij is not output.

(Ii) The stuff pulse is accommodated in the stuff channel corresponding to the stuff pulse.

(Iii) A stuff pulse is set as the stuff designated pulse corresponding to the stuff pulse.

(4) No stuff pulse is output (i) G frame pulse GP1i and transmission reference clock C
In synchronization with LK2i, no stuff pulse is set to the stuff designation pulse corresponding to the carrier relay signal.

(Ii) The carrier relay signal is accommodated in the corresponding carrier relay channel.

The frame pulse generator 80 # i generates a G frame pulse GP1i at a G frame cycle according to the transmission reference clock CLK1i. Scrambler 82 #
i is the MUX unit 7 according to the G frame pulse GP1i.
8 # i, scramble the G frame output from #i.
The IF unit 84 # i converts the scrambled G frame into a transmission path interface according to the transmission reference clock CLK2i and transmits the G frame to the transmission path.

The IF unit 90 # i receives the SDH D
The CC frame is received and converted into an interface in the device. The reception timing clock generation unit 92 # i outputs the clock CLK1 output from the bit synchronization circuit 72 # i.
From i, a reception reference clock CLK4i having a clock frequency equal to the transmission speed of the carrier relay channel is generated. The frame synchronization circuit 94 # i receives the clock CLK1i
To synchronize the G frame. The G frame pulse GP2i is output to the DMUX unit 98 # i. A stuff designation pulse is output to destuff synchronizer 100 # ij. The descrambler 96 # i receives the G frame pulse GP
Synchronize with 2i and descramble. DMUX unit 98
#I receives a frame in synchronization with the G frame pulse and the clock CLK1i. Receive reference clock CLK3
In synchronization with i, a carrier relay signal / stuff pulse inserted in the G unit is separated and output to the corresponding destuff synchronization unit 100 # ij.

The destuff synchronizer 100 # ij has the following functions.

(1) The carrier relay signal output from the DMUX unit 98 # i is written in the memory.

(2) The stuff pulse is detected from the stuff designation pulse, and control is performed so that the stuff pulse is not written into the memory.

(3) The carrier relay signal is read from the memory according to the clock CLK4i output from the VCO 100 # i.

(4) Convert the carrier relay signal from a unipolar format to a bipolar format.

FIG. 6 shows a destuff synchronizer 100 # i in the figure.
FIG. 7 is a configuration diagram of j. As shown in FIG. 6, the destuff synchronization unit 100 # ij includes a destuff control unit 130 # i, a writing unit 132 # i, a reading unit 136 # i, and a transmission memory 134 #.
ij and a UB converter 138 # ij. The destuff controller 130 # i detects a stuff pulse from the stuff designation pulse. The stuff pulse is DMUX part 9
When output from 8 # i, it instructs transmission memory 134 # ij not to write a stuff pulse. Writing section 132 # i writes a carrier relay signal to transmission memory 134 # ij according to reception reference clock CLK4i and an instruction signal output from destuff control section 130 # i.

The transmission memory 134 # ij is a dual port memory for writing / reading a carrier relay signal. The reading unit 136 # ij transmits the transmission memory 13 according to the clock CLK5i output from the VCO 100 # i.
Read the carrier relay signal from 4 # ij. The UB converter 138 # ij converts the carrier relay signal read from the transmission memory 134 # ij from a unipolar signal format to a bipolar signal format.

The operation of the carrier relay transmission system shown in FIG. 2 will be described below. In this example, a case will be described in which transmission is performed from the carrier relay system 52 # 1j (j = 1 to 9) to the carrier relay system 52 # 2j (j = 1 to 9).

(1) Transmission of Carrier Relay Signal Each carrier relay system 52 # 1j (j = 1 to 9)
Receives a transmission line current value and the like from the circuit breaker 50 # 1j, and transmits a carrier relay signal in a bipolar signal format at a transmission speed of 54 kbps.

(2) Multiplexing of Carrier Relay Signal FIG. 7 is a time chart related to transmission of a carrier relay signal.

(2-1) Writing of Carrier Relay Signal FIG. 8 is a flowchart of receiving a carrier relay signal. BU conversion section 110 # ij receives the carrier relay signal in step S2 in FIG. In step S4, the carrier relay signal is converted from the bipolar signal format to the unipolar signal format. In step S6, the clock extraction unit 112 # ij converts the clock CLK6ij from the carrier relay signal as shown in FIG.
Is extracted. The writing unit 114 # 1j, in step S8, according to the clock CLK6ij,
6 Write a carrier relay signal into # 1j.

(2-2) Transmission Reference Clock, Transmission Timing Clock Generation, and G Frame Pulse Generation The bit synchronization circuit 72 # 1 is provided with an SDH DCC unit 58 # 1.
In synchronization with the transmitted 576 kbps clock TCLK, a 576 kbps synchronous clock CLK1i is generated. The transmission reference clock generation unit 74 # 1 generates the clock CLK11 generated by the bit synchronization circuit 72 # 1.
, A transmission reference clock CLK21 of 576 kbps is generated as shown in FIG. The transmission timing clock generator 76 # 1 receives the transmission reference clock CLK21
Is divided to generate a transmission timing clock CLK31. The frame pulse generator 80 # 1 counts the transmission reference clock CLK21 and generates a frame pulse GP11 at regular intervals.

(2-3) Reading Carrier Relay Signal FIG. 9 is a flowchart of reading a carrier relay signal. The reading unit 118 # 1j performs the processing in step S in FIG.
At 20, a transmission timing clock CLK31 is received. In step S22, as shown in FIG.
The carrier relay signal CRR1 is transmitted from the transmission / reception memory 116 # 1j in synchronization with the transmission timing clock CLK31.
Read j. At this time, since the carrier relay signal is read immediately after being written into the reception memory 116 # 1j, there is almost no delay time.

(2-4) Generation of Stuff Pulse FIG. 10 is a flowchart of stuff pulse generation. The stuff control unit 120 # 1j (j = 1 to 9) receives the transmission timing clock CLK31 in step S30 in FIG. In step S32,
In synchronization with the transmission timing clock CLK31, it is determined whether or not the carrier relay signal is empty in the reception memory 116 # 1j. If the reception memory 116 # 1j is empty, the process proceeds to step S34. If the carrier relay signal stored in the reception memory 116 # 1j is not empty, the process returns to step S30. In step S34, a stuff pulse STF1j is generated in synchronization with the transmission timing clock CLK31, as shown in FIG.

(2-5) Generation of Frame FIG. 11 is a flowchart of multiplexing of a carrier relay signal. The MUX unit 78 # i performs step S
At 40, a transmission timing clock CLK31 is received. In step S42, the carrier relay signal CRR is synchronized with the transmission timing clock CLK31.
1j / stuff pulse STF1j is received. In step S44, the G frame pulse GP11 is received. In step S46, the G frame pulse GP1
Count one. In step S48, it is determined whether or not to generate a multi-frame synchronization pulse / frame synchronization pulse based on the counter value of the G frame pulse GP11. If a multi-frame sync pulse / frame sync pulse is to be created, the process proceeds to step S50. When the multi-frame synchronization pulse / frame synchronization pulse is not created, the process proceeds to step S52.

In step S50, a multi-frame synchronization pulse / frame synchronization pulse is set in the G frame header. In step S60, a stuff designation pulse (no stuff pulse) is inserted. Step S62
, The Curie relay signal is accommodated in the corresponding channel. At this time, the carrier relay signal is transmitted to the reception memory 11
There is almost no delay time from reading from 6 # 1j to being accommodated in the channel. In step S52,
It is determined whether a stuff pulse has been received. If a stuff pulse has been received, the process proceeds to step S58. If the stuff pulse has not been received, the process proceeds to step S54.

In step S54, until the stuff channel is assigned, the carrier relay signal is accommodated in the carrier relay channel, and a stuff designation pulse (with stuff) is inserted. In step S56, the stuff pulse is stored in the stuff channel corresponding to the stuff pulse, and the process returns to step S40.
In step S60, a stuff designation pulse (no stuff) is inserted. In step S62, the carrier relay signal is accommodated in the corresponding carrier channel, and the process returns to step S40.

(2-6) Transmission of Frame The scrambler 82 # 1 receives the G frame and performs scrambling according to the G frame pulse GP11.
The IF unit 84 # 1 converts the G frame to a transmission path interface in synchronization with the transmission reference clock CLK21, and transmits the G frame to the transmission path as a 576 kbps SDH DCC.

(3) The SDH transmission system 56 # 1
SDH transmitted by DCC multiplexing / demultiplexing section 54 # 1
When DCC is received, the section overhead DC
Stored in C bytes. And SDH with payload
The data is transmitted to the transmission system 56 # 2. When receiving the SDH frame from the SDH transmission system 56 # 1, the SDH transmission system 56 # 2 separates the SDH DCC. DCC multiplexing / demultiplexing unit 54 # 2 together with transmission clock TCLK
Send to

(4) Separation of Carrier Relay Signal (4-1) Reception of Frame The bit synchronizing circuit 72 # 2 has the SDH DCC unit 58 # 2
Bit synchronization with the 576 kbps clock TCLK transmitted from the
12 is generated. The IF unit 90 # 2 receives the clock CLK1
In synchronization with 2, the interface is converted from the transmission line interface to the device interface.

(4-2) Frame Synchronization FIG. 12 is a flowchart of frame synchronization. The frame synchronization circuit 94 # 2 receives the clock CLK12 in step S70 in FIG. Step S7
In 2, the multi-frame synchronization is obtained by checking each bit of the received SDH DCC multi-frame with the multi-frame synchronization pulse. Then, a G-frame pulse GP22 indicating the head of the multi-frame is created. In step S74, frame synchronization is achieved by checking each bit of the multi-frame with the frame synchronization pulse. Then, a frame pulse indicating the head of each G frame is created. In step S76, according to the multi-frame pulse and the G-frame pulse, G
The frame is counted, and a stuff designation pulse corresponding to the count value is output to destuff synchronizer 100 # 2j.

(4-3) DMUX FIG. 13 is a flowchart for separating a carrier relay signal. The DMUX unit 98 # 2 performs step S in FIG.
At 90, a G frame pulse GP22 is received.
In step S92, the clock CLK12 is received. In step S94, the G frame pulse GP2
According to 2, the clock CLK12 is counted to determine whether or not the G unit has been input. If the G unit has not been input, the process returns to step S92. If the G unit has been input, the process proceeds to step S94. Step S
At 94, a carrier relay signal / stuff pulse contained in a carrier channel in the G unit is separated. In synchronization with the reception timing clock CLK42, the separated carrier relay signal / stuff pulse is output to the corresponding destuff synchronization section 100 # 2j, and step S
Return to 92.

(4-4) Destuffing FIG. 14 is a flowchart of destuffing control. Each destuff synchronizer 100 # 2j receives the stuff designation pulse in step S100 in FIG. In step S100, it is determined whether there is a stuff pulse based on the bit pattern of the stuff designation pulse. If there is a stuff pulse, the process proceeds to step S102. If there is no stuff pulse, the process returns to step S100. In step S102, the write prohibition is set to the write unit 1
32 # 2j.

FIG. 15 is a flowchart for writing a carrier relay signal. The writing unit 132 # 2j is configured as shown in FIG.
In step S110, the reception timing clock CLK42 is received. In step S112,
It is determined whether write prohibition is instructed. If write-protection has been instructed, the process returns to step S110. If the write prohibition is not instructed, step S
Proceed to 114. In step S114, the carrier relay signal is written into the transmission memory 134 # 2j according to the reception timing clock CLK42.

(4-5) Transmission of Carrier Relay Signal FIG. 16 is a flowchart of transmission of a carrier relay signal. The VCO 100 # 2 generates a clock CLK52 of 54 kbps. The reading unit 136 # 2j is configured as shown in FIG.
In step S120, the clock CLK52 is received from the VCO 100 # 2. In step S122, the transmission memory 13 is synchronized with the clock CLK52.
4 Read the carrier relay signal from # 2j. In step S124, the UB conversion unit 138 # 2j converts the carrier relay signal from the unipolar format to the bipolar format and transmits the signal to the carrier relay system 52 # 2j.

(5) Each carrier relay system 52 #
2j receives the carrier relay signal, compares it with the carrier relay signal of its own system, detects an abnormality in the power transmission system, and performs necessary processing such as power transmission stop.

[0082]

According to the present invention described above, it is possible to transmit a carrier relay signal with no delay time fluctuation, to transmit a carrier relay signal without a delay time difference between upstream and downstream, and to transmit a carrier relay signal with a small delay time. The effect is that transmission is possible, that a highly reliable system required for a carrier relay signal transmission system can be constructed, and that multiplexing efficiency can be improved as compared with the multipoint sampling method at the same transmission speed. .

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of a carrier relay signal transmission system according to an embodiment of the present invention.

FIG. 3 is a configuration diagram of a DCC multiplexing / demultiplexing unit in FIG. 2;

FIG. 4 is a configuration diagram of a stuff synchronizer in FIG. 3;

FIG. 5 is a diagram showing a frame configuration.

FIG. 6 is a configuration diagram of a destuff synchronization unit in FIG. 3;

FIG. 7 is a time chart of a staff synchronization unit in FIG. 3;

FIG. 8 is a flowchart of receiving a carrier relay signal.

FIG. 9 is a flowchart of reading a carrier relay signal.

FIG. 10 is a flowchart of stuff pulse generation.

FIG. 11 is a flowchart of multiplexing of a carrier relay signal.

FIG. 12 is a flowchart of frame synchronization.

FIG. 13 is a flowchart of separation of a carrier relay signal.

FIG. 14 is a flowchart of destuff control.

FIG. 15 is a flowchart of writing a carrier relay signal.

FIG. 16 is a flowchart of transmission of a carrier relay signal.

FIG. 17 is a configuration diagram of a conventional carrier relay signal transmission system.

FIG. 18 is a configuration diagram of a conventional carrier relay signal transmission system.

[Explanation of symbols]

 30 # i (i = 1 to n) Reception memory 31 # i (i = 1 to n) First writing unit 32 First clock generation unit 34 Second clock generation unit 36 # i (i = 1 to n) Staff Pulse generating means 38 # i (i = 1 to n) First reading means 40 Frame pulse generating means 42 Frame header generating means 44 Multiplexing means

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5G047 AA01 BB01 CA06 5K028 KK01 KK12 LL11 MM05 NN02 RR03 SS02 SS12 SS24

Claims (3)

[Claims] 1. A carrier relay signal transmitting apparatus for transmitting a plurality of carrier relay signals, comprising: a plurality of receiving memories; and a first clock synchronized with the plurality of carrier relay signals transmitted from a plurality of transmission paths. A plurality of first writing means for writing the plurality of carrier relay signals into the plurality of reception memories; and a second equal to a transmission rate of a frame composed of a frame header and a plurality of channels accommodating the plurality of carrier relay signals. First clock generation means for generating a clock; and second clock generation means for generating a third clock having a frequency higher than the frequency of the first clock and equal to the transmission speed of the channel based on the second clock. A frequency equal to a frequency difference between the first clock and the third clock based on the third clock; Of a plurality of stuff pulse generating means for generating a stuff pulse, based on the third clock, the first from the plurality of receive memory a plurality of reading out the plurality of carrier relay signal
Reading means; frame pulse generating means for generating a first frame pulse indicating the head of the frame based on the second clock; and reading the frame header based on the first frame pulse and the second clock. Frame header generating means for inserting a pulse indicating a head of a frame and a stuff designation pulse for controlling a stuff pulse accommodated in each of the channels; and a plurality of read-out memories from the plurality of reception memories based on the third clock Multiplexing means for receiving a carrier relay signal and the stuff pulse, and accommodating the carrier relay signal or the stuff pulse corresponding to the plurality of channels based on the second clock and the first frame pulse. A carrier relay signal transmission device characterized in that: 2. A frame synchronizing means for synchronizing a frame received from a transmission line based on a fourth clock synchronized with a frame transmitted from the transmission line and generating a second frame pulse indicating a predetermined position of the frame. And the second
Stuff designation pulse detection means for detecting a stuff designation pulse contained in a frame header based on a frame pulse; and third clock generation means for generating a fifth clock equal to the transmission rate of each channel based on the fourth clock. Separation means for separating a plurality of carrier relay signals or stuff pulses contained in a plurality of channels of the frame based on the four clocks and the second frame pulse, and detection of a stuff designation pulse by the stuff detection means A plurality of destuff control means for detecting a stuff pulse based on the result, a plurality of transmission memories, and a signal outputted from the separation means based on a stuff pulse detection result by the fifth clock and the plurality of destuff control means. In a carrier relay signal or stuff pulse A plurality of second writing means for writing only a carrier relay signal into the plurality of transmission memories, a clock generation means for generating a sixth clock, and the carrier relay signal from the plurality of transmission memories based on the sixth clock. 2. The carrier relay signal transmission device according to claim 1, further comprising: a plurality of first reading means for reading. 3. The carrier relay signal transmission device according to claim 1, wherein the frame is accommodated in a data communication channel during section overhead in an SDH transmission system.