JPH07193126A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a smooth tapered opening shape even with a large aspect ratio and form a contact hole with excellent wiring coating by anisotropically etching an insulating film formed on a semiconductor substrate so as to leave the stepped side wall film on the opening wall plane after etching back the whole plane of the insulating film. CONSTITUTION:An insulating SiO2 film is formed on a substrate 1 and anisotropical dry etching is performed using the first resist of a contact hole pattern as a mask. Then, a contact hole pattern is formed by second resist 4 using a stepper and anisotropical dry etching is performed using the second resist 4 as a mask. Then, the second resist 4 is removed and an SiO film 5 is formed. The whole plane is etched back by anisotropical etching by the RIE method. As a result, on the corner and the wall plane of the opening of the insulating film 2, the stepped first side wall plane 3 and the second side wall film 5 are left and the SiO2 film is formed in a smooth circular arc.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having an improved contact hole.

[0002]

2. Description of the Related Art Since semiconductor integrated circuit devices and compound semiconductor devices represented by VLSI are in the direction of higher performance and higher integration, formation of fine patterns is becoming an increasingly important factor.

With the increase in performance and integration, electrode wiring is required in integrated circuit elements and the like, and RIE (Re
The active Ion Etching) method has been put to practical use. However, the wall surface of the contact hole formed by this RIE method has a shape almost close to vertical, and a disconnection is likely to occur on the wall surface of the wiring metal layer deposited in the contact hole, so that the coverage of the wiring metal layer is improved. In addition, the wall surface of the contact hole is designed to be tapered.

FIG. 3 shows a conventional technique for obtaining a tapered shape by isotropic etching and anisotropic etching (Japanese Patent Laid-Open No. 63-258021).

As shown in FIG. 3A, a photoresist contact hole pattern 24 is provided at a position corresponding to a first conductive metal layer (hereinafter referred to as a wiring layer) 25,
Using this as a mask, wet etching is performed with an ammonium fluoride solution up to about 1/3 of the thickness of the interlayer insulating film 23.

Next, as shown in FIG. 1B, anisotropic etching is performed by the RIE method using the photoresist 24 as a mask. In this RIE, a normal parallel plate electrode type device is applied, and CF ₄ 20SCCM, O ₂ 10SC are used as conditions.
CM, pressure 1.2 Pa, RF power 350 W are used.

After this opening, the photoresist 24 is removed by ashing, as shown in FIG. As a result, the through hole 28 has a concave portion 29 forming the vicinity of the opening surface thereof and the first wiring layer 25.
A vertical portion 30 which is connected to and has a diameter smaller than that of the concave portion is obtained, and the depth of the bowl-shaped portion 29 is within about 1/3 of the whole. A corner portion 31 is formed at the boundary of the vertical portion 30 of the bowl-shaped portion 29, and a corner portion 32 is also formed on the opening surface of the concave portion 29. However, as shown in FIG. By completely etching back the interlayer insulating film 23, the corners 31 and 32 are removed and the taper 33 is obtained.

[0008]

In the conventional contact hole forming method as described above, the corner portions 31 and 32, which are apt to cause step breakage, are always generated, and it is necessary to perform the entire etch back to remove the corner portions. Since this etch back amount is anisotropic etching, etching must be continued until the vertical portion 30 disappears. Therefore, as shown in FIG. 3D, the thickness of the interlayer insulating film is reduced to about 60% of the film thickness at the time of formation. This causes a large change in wiring capacitance, resulting in deterioration of characteristics. further,
When the vertical portion 30 is eliminated, the opening diameter of the contact hole changes in a direction in which it becomes wider with respect to slight overetching of the etchback, which makes it difficult to miniaturize the wiring pattern. For this reason, it is necessary to form the interlayer insulating film with a large film thickness and reduce the opening size of the photoresist for contact holes, but this leads to a decrease in processing accuracy.
There is a problem that the wiring yield is deteriorated.

[0009]

According to the present invention, a step of forming an interlayer insulating film on a substrate and performing anisotropic dry etching using the first resist as a mask to form a step in the interlayer insulating film, A step of etching the first sidewall film and the interlayer insulating film by anisotropic etching using the first resist as a mask; a step of removing the second resist and then forming a second sidewall film; Etching back the entire surface by etching to open the interlayer insulating film. Thus,
A tapered opening shape can be obtained by leaving a side wall film in a step shape on the wall surface of the contact hole.

[0010]

The present invention will be described below with reference to the drawings. 1A to 1D are process sectional views of a semiconductor device according to an embodiment of the present invention. First, as shown in FIG. 1A, a CV is formed on the substrate 1.
The SiO ₂ film 2 which is an insulating film having a thickness of 7500 angstroms is formed by the D method, and the first resist (not shown) which is a contact hole pattern is used as a mask to perform RIE.
Anisotropic dry etching is performed by the method. As conditions for this time, CF ₄ or CHF ₃ gas, a pressure of 1 Pa, and a microwave power of 300 to 500 W are suitable. After that, the first resist is removed, and the SiO ₂ film 3 having a thickness of 2500 Å is formed on the first side wall film by the CVD method.

Next, as shown in FIG. 1B, a contact hole pattern is formed on the second resist 4 by using a stepper or an electron beam exposure machine, and the second resist 4 is used as a mask for RIE. Anisotropic dry etching is performed by the method. The conditions at this time may be almost the same as in the case of FIG. The etching amount at this time is stopped when the first side wall film 3 is etched and the insulating film 2 is further etched by about 2500 Å. Then, the second resist 4 is removed, and as shown in FIG. 1C, the SiO 2 film 5 is formed on the second sidewall film by the CVD method to a thickness of 2500 Å.

Thereafter, as shown in FIG. 1D, the RIE method or the ECR (Electron Cyclotron) is used.
Resonance) The entire surface is etched back by anisotropic etching by the plasma method.

The condition at this time is that the gas is S in the case of the RIE method.
F ₆ gas pressure is 1 Pa, microwave power is 100 to 30
0W is suitable. In the case of the ECR method, the gas is SF ₆
Gas pressure is 0.1 Pa, microwave power is 100-2
00W is suitable. This condition is for reducing the dry etching damage to the substrate 1 at the time of opening while maintaining the anisotropic etching. At this time, the etching back etching amount is the second sidewall film 5 (thickness 2500 angstrom).
Then, a slight over-etching (usually about 20 to 50% increase) is performed to 5000 Å which is a total of 2500 Å of the remaining film thickness of the insulating film 2.

As a result, the first side wall film 3 and the second side wall film 5 are left in a stepped manner on the corners and wall surfaces of the opening of the insulating film 2. Further, as can be seen from FIGS. 1A to 1D, since the shape of the SiO ₂ film formed by the CVD method at the step portion is a smooth arc shape, the SiO ₂ film which is the sidewall film remaining at the step portion after the entire surface is etched back. _{Since the two} films 3 and 5 also have a smooth circular arc shape, a smooth tapered opening shape can be obtained as shown in FIG. 1 (d).

Next, a second embodiment of the present invention will be described with reference to the drawings. 2A to 2D are process cross-sectional views of a semiconductor device of one embodiment. First, as shown in FIG. 2A, the substrate 1
The insulating film 2 to form a SiO ₂ film having a thickness of about 12500 Å by the CVD method above, the SiO ₂ film 2 by RIE with the first resist (not shown) as a mask
Is etched to 2500 angstroms. The conditions at this time are the same as in the case of FIG. Then, the first resist is removed to form a first sidewall film with a thickness of 2500 by the CVD method.
An Angstrom SiO ₂ film 3 is formed.

Next, as shown in FIG. 2B, the first sidewall film 3 is etched by the RIE method using the second resist 4 as a mask, and the insulating film 2 is further etched by 2500 Å. Then, the second resist 4 is removed. Next, as shown in FIG. 2C, as the second sidewall film, SiO 2 having a thickness of 2500 Å is formed by the CVD method.
₂ film 5 is formed, and the second sidewall film 5 is etched by RIE using the third resist 14 having a pattern for a contact hole formed by using a stepper or an electron beam exposure machine as a mask. Is etched to 2500 angstroms. Then, the third resist 14
To remove.

Next, as shown in FIG. 2 (d), a SiO ₂ film 6 having a thickness of 1500 Å is formed as a third side wall film by the CVD method, and is anisotropically etched by the RIE method or the ECR method. Perform full etch back. The conditions at this time are the same as those in FIG.

As a result, the first side wall film 3, the second side wall film 5 and the third side wall film 6 remain in a stepwise manner on the corners and the wall surface of the opening of the insulating film 2, and the first embodiment For the same reason as above, since the first to third side wall films have a smooth arc shape, the opening shape of the contact hole can also have a smooth tapered opening shape. In the case of the second embodiment, it is possible to form an opening shape having a large aspect ratio (thick film of the insulating film with respect to the contact hole diameter) without impairing the wiring coverage, and to improve the performance by reducing the wiring capacitance and the contact hole diameter. There is an advantage that miniaturization can be achieved by reducing

[0019]

As described above, according to the present invention, a step is formed in the insulating film by anisotropic etching, a side wall film is formed on the step, and the entire surface is etched back by anisotropic etching. Even if the thickness of the insulating film with respect to the hole diameter) is large, a smooth tapered opening shape can be obtained, so that there is an advantage that fine contact holes with good wiring coverage can be formed with high yield. Further, since anisotropic etching is used for all dimensional variation, there is an advantage that the dimensional variation is small as compared with the case where isotropic etching is used as in the past. Although the size varies depending on the thickness variation of the side wall film, the thickness variation is usually ± 1.
The dimensional variation in this case is about 0.01 to 0.03 μm, which is smaller than the dimensional variation in other steps.

[Brief description of drawings]

FIG. 1 is a process sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a process cross-sectional view of a semiconductor device of a conventional example.

[Explanation of symbols]

 1, 21 Substrate 2, 22, 23 Oxide film 3, 5, 6 Sidewall oxide film 4, 14, 24 Resist 25 First wiring layer 26 Opening pattern 28 Through hole 29 Bowl-shaped part 30 Vertical part 31, 32 Acute angle part 33 Tapered part

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/3205 H01L 21/88 F

Claims (2)

[Claims] 1. A structure in which a sidewall film remains in a graded manner on a wall surface of an opening after etching back the entire surface of the insulating film by anisotropic etching of an insulating film formed on a semiconductor substrate. Semiconductor device. 2. A step of forming an insulating film on a semiconductor substrate, performing anisotropic dry etching using the first resist as a mask to form a step in the insulating film, and after removing the first resist, The step of forming the first side wall film, the step of etching the first side wall film and the insulating film by anisotropic dry etching using the second resist as a mask, and the step of removing the second resist and then the second step. A method of manufacturing a semiconductor device, comprising: a step of forming a sidewall film; and a step of etching back the entire surface of the semiconductor substrate by anisotropic dry etching to open the insulating film.