JPH0689163A - Random number generator - Google Patents

Abstract

PURPOSE:To generate random numbers at a high speed by selecting whether to take an upper half inside the output bits of a mantissa part arithmetic circuit on to take a low-order half. CONSTITUTION:In normal floating point multiplication, the output 4 of upper N bits is outputted as the output of the mantissa part arithmetic circuit 3. However, in random number generation, it is required to select the output 5 of low-order N bits as a multiplied result from a prescribed formula. The selection is performed using a selection signal 8 and a selection circuit 6. That is, the selection signal 8 is generated by the instruction of a program or an user, the upper N bits are selected at the time of operation as the normal floating point multiplier and the low-order N bits are selected at the time of generating the random number. Since the output 7 of the selection circuit 6 is not necessarily normalized, it is normalized at a normalization circuit 9 so as to be utilized in a floating point operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for generating random numbers.

[0002]

2. Description of the Related Art There are various known methods for generating random numbers, one of which is the method using the congruential multiplication method (see Tomio Hayashi, "Knowledge of Random Numbers", Morikita Publishing). . Conventionally, when a random number is generated at high speed by using the congruential multiplication method, a multiplier capable of integer type arithmetic as described in JP-A-57-8846 is required. However, some digital processing devices have only a floating point multiplier and some do not. In such a case, it is extremely uneconomical to newly provide a multiplier capable of performing an integer operation only for generating a random number and another generating circuit.

Therefore, it may be considered to generate a random number by using a floating point multiplier. FIG. 2 shows a conventional floating point multiplier, where 1 is the first input of the mantissa arithmetic circuit of the floating point multiplier, 2 is the second input of the mantissa arithmetic circuit of the floating point multiplier, and 3 is the floating point. The mantissa arithmetic circuit of the decimal point multiplier, 4 is the upper half of the output of the mantissa arithmetic circuit of the floating point multiplier, and 5 is the lower half of the output of the mantissa arithmetic circuit of the floating point multiplier.

In FIG. 2, since only the upper N bits 4 of the mantissa part multiplication result are normally output as the output of the mantissa part arithmetic circuit 3 of the floating point multiplier, it is not possible to use the floating point multiplier for random number generation. could not.

[0005]

Therefore, an object of the present invention is to generate a random number at high speed by using a floating point multiplier.

[0006]

SUMMARY OF THE INVENTION A random number generator according to the present invention is a floating point multiplier capable of separately outputting to upper half and lower half of output bits of a mantissa arithmetic circuit, and the mantissa arithmetic circuit. And a selection circuit for selecting whether to take the upper half or the lower half of the output bits.

[0007]

When the upper half of the output bits of the mantissa arithmetic circuit is selected, the floating-point multiplier outputs the multiplication result of the floating-point multiplication, and the output bits of the mantissa arithmetic circuit are output. The floating point multiplier generates a random number when the lower half is selected.

[0008]

EXAMPLES Examples of the present invention will be described.

FIG. 1 is a block diagram of a random number generator of the embodiment. 1 is the first mantissa arithmetic circuit of the floating point multiplier
Input 2 is the second input of the mantissa arithmetic circuit of the floating point multiplier, and 3 is the mantissa arithmetic circuit of the floating point arithmetic unit that can output the upper half and the lower half of the output bits separately. The upper half of the output of the mantissa arithmetic circuit 3 of the decimal point multiplier, 5 is the lower half of the output of the mantissa arithmetic circuit of the floating point multiplier 3, 6 is the selection circuit, 7 is the output of the selection circuit, 8 is the selection signal, Reference numeral 9 is a normalization circuit, and 10 is an output of the normalization circuit.

The operation of the random number generator of FIG. 1 will be described. First, the congruential multiplication method will be described. Random numbers are generated by the congruential multiplication method according to the following formula (see Tomoki Hayashi, "Knowledge of Random Numbers", Morikita Publishing).

X _{n + 1} ≡a × X _n (modulo 2 ^p ). ． ． (1) X ₀ = b (a = 3, 5 (modulo 8), b = odd number) Here, X _n is a binary p-digit random number sequence, and a is its initial value. Also, modulo 2 ^p is an arbitrary integer 2 ^p
It means the remainder when divided by.

When a random number is generated by using the random number generator of FIG. 1, a number corresponding to the symbol a in the above formula (1) is set to an integer in the first input 1 of the mantissa arithmetic circuit 3 of the floating point multiplier. Give in format. In addition, the second input 2 of the mantissa arithmetic circuit 3 of the floating point multiplier is given the number corresponding to the symbol X _n in the above formula (1), that is, the random number generated immediately before, in the form of integer.
That is, they may not always be normalized for floating point arithmetic. Both of these are N-bit long, 2
It is a decimal number. Therefore, the mantissa arithmetic circuit 3 outputs the multiplication result of 2 * N bits. This upper N bit is output 4
And the lower N bits are output 5.

In normal floating point multiplication, the output 4 of the upper N bits is output as the output of the mantissa arithmetic circuit 3. However, in the random number generation, it is necessary to select the output N of the lower N bits as the multiplication result from the equation (1).
This selection is performed using the selection signal 8 and the selection circuit 6. That is, the selection signal 8 is generated based on the instruction of the user or the program, and the upper N bits are selected when operating as a normal floating point multiplier, and the lower N bits are selected when generating a random number. Since the output 7 of the selection circuit 6 is not necessarily normalized, it is normalized by the normalization circuit 9 in order to use it in the floating point arithmetic. However, since the output 7 of the selection circuit 6 is used for the next random number generation from the equation (1), it needs to be stored as it is. This is the output signal 7 '.

[0014]

As described above, according to the present invention,
It is possible to generate random numbers at high speed by using the congruential multiplication method by using the existing floating-point multiplier by adding the minimum hardware.

[Brief description of drawings]

FIG. 1 is a block diagram of a random number generator using a floating point multiplier according to the present invention.

FIG. 2 is a block diagram of a conventional floating point multiplier.

[Explanation of symbols]

1 ... First input of mantissa arithmetic circuit, 2 ... Second input of mantissa arithmetic circuit, 3 ... Mantissa arithmetic circuit, 4 ... Upper half of output of mantissa arithmetic circuit, 5 ... Output of mantissa arithmetic circuit Lower half, 6 ... Selection circuit, 7 ... Selection circuit output, 8 ... Selection signal, 9 ... Normalization circuit, 10 ... Normalization circuit output

Claims (1)

[Claims] 1. A floating point multiplier capable of separately outputting the upper half and the lower half of the output bits of the mantissa arithmetic circuit, and taking the upper half of the output bits of the mantissa arithmetic circuit or taking the lower half. A random number generator comprising: a selection circuit for selecting whether to take half.