JP3722821B2 - Calculation method - Google Patents

Description

  The present invention relates to an arithmetic method for performing arithmetic processing of data in which the bit width of one word is not a standard 2 n bit.

  Some devices that output or process images, sounds, etc. have a standard 1-bit bit width to improve the quality of images and sounds, or to attach additional information to images and sounds. There are some which use data that is not 2 n bits. Examples of such a device include a so-called third generation mobile phone and an information processing device that generates image data of multiple gradations. Such a device is equipped with a digital signal processor (hereinafter referred to as a DSP) and other arithmetic devices, thereby converting the bit width of one word into a standard 2 n-bit bit and performing various arithmetic processing. I do.

  A conventional arithmetic device will be described below by taking a DSP mounted on a third generation mobile phone as an example.

  The third generation mobile phone uses a DSP to extract several specific band signals from a wide frequency band so that good communication can always be performed. Then, communication is performed by selecting a frequency band having particularly high reception sensitivity from among them. At this time, the DSP usually emphasizes the path strength of a signal in a specific band using a technique called a digital matched filter (hereinafter referred to as DMF) algorithm, which will be described later, thereby extracting the signal in the specific band. .

  19 is a diagram showing the configuration of a conventional arithmetic unit, FIGS. 20 and 21 are diagrams showing the arrangement of data stored in two memory blocks, FIGS. 22 and 23 are diagrams showing an outline of the DMF algorithm, and FIG. FIG. 27 is a chart showing arithmetic expressions of the DMF algorithm. In the following description, it is assumed that data transmission processing between blocks and arithmetic processing by arithmetic means are performed in units of 32 bits.

In FIG. 19, the shifter 11 adjusts the phase by shifting a bit transmitted from an accumulator 15 or a memory 17 described later by a predetermined bit in order to facilitate arithmetic processing. An arithmetic logic unit (hereinafter referred to as ALU) 13 executes an operation by a DMF algorithm described later based on data transmitted from the shifter 11 and data transmitted from an accumulator 15 described later. The accumulator 15 is a register for storing the calculation result by the ALU 13 and is composed of two blocks Acc ₀ and Acc ₁ . Note that the calculation result stored in the accumulator 15 is output to the memory 17 along the first route 23. Further, based on the control of a control unit (not shown), the data is transmitted to the ALU 13 along the second route 25 at the time of predetermined calculation processing, and is used for subsequent calculation processing there.

  The memory 17 includes a first memory block 19 and a second memory block 21 each having a predetermined bit width (16 bits in the conventional example shown in FIG. 19), and stores the calculation result by the ALU 13 transmitted from the accumulator 15.

  20 shows a rough arrangement of data stored in the memory 17, and FIG. 21 shows a detailed arrangement of data stored in the memory 17. The memory 17 stores the I part data in the first memory block 19 and the R part data in the second memory block 21 among the calculation results based on the combination of the I part data and the R part data. The memory 17 stores unused data for an insufficient bit width when each word of the operation result is less than a predetermined bit (16 bits) width. For example, in the example shown in FIGS. 20 and 21, since the I part data and the R part data are each 10 bits wide, the memory 17 converts unused data of 6 bits wide to the first memory block 19 and the second memory. Stored in each of the blocks 21. In FIG. 21, "[-In-]" is an area storing I part data, "[-Rn-]" is an area storing R part data, and "*" is unused data. The storage area is shown.

  The reason why the ALU 13 having a 32-bit width is connected to the memory 17 having a 16-bit width is to cope with the case where the calculation width is increased by a multiplication operation. However, the memory 17 is not limited to the 16-bit width and may be 4 or 32. It is also possible to set the bit width to 2 to the nth power. However, at the present time, 16-bit width memories are widespread and the cost is low, so a 16-bit width memory is desirable to reduce the DSP cost.

  The DMF algorithm will be described below. 22 and 23 are diagrams showing an outline of the DMF algorithm, and FIGS. 24 to 27 are tables showing arithmetic expressions of the DMF algorithm.

  In FIG. 22, “+” indicates an addition operation, and “*” indicates a multiplication operation. However, since the multiplication operation * has a multiplier of 1 or −1 in the DMF algorithm, in actuality, the sign does not change or is merely inverted. Note that the configuration of the adder circuit and the multiplier circuit is not particularly limited, and a description thereof will be omitted here.

D ₁ ... ₈ indicates a delay value of data, output data of D ₁ is input data before 128 cycles, output data of D ₂ is input data before 64 cycles, and output data of D ₃ is input data before 16 cycles. , output data 32 cycles before the input data D _4, the output data is 8 cycles before the input data D _5, the output data is one cycle before the input data D _6, the output data of the D ₇ is 4 cycles before input data, output data of the D ₈ is two cycles before the input data. W ₁ ... ₈ indicates a multiplication coefficient to be multiplied by the delay value D. W ₁ is 1, W ₂ is −1, W ₃ is 1, W ₄ is 1, W ₅ is 1, W ₆ is 1, W ₇ Is 1 and W ₈ is 1. The values of the delay values D ₁ ... ₈ and the multiplication coefficients W ₁ ... ₈ are fixed so that the calculation result becomes a value that emphasizes the path strength of a signal with a specific delay value (that is, a signal in a specific band). Is set. The ALU 13 can emphasize a signal in a specific band by performing an operation using the DMF algorithm, and can thereby extract a signal in a specific band.

FIG. 23 shows the input / output of each calculation process in FIG. 22, and FIGS. 24-27 show the relationship of each input / output in FIG. As shown in FIG. 23, the inputs / outputs A _{1 to} A ₈ , B _{1 to} B ₈ , C _{1 to} C ₈ , C ₁ ′ to C ₃ ′, C ₅ ′, and C ₇ ′ start from the input A ₀ . It is said. FIG. 24 shows an arithmetic expression representing the relationship between the inputs and outputs, FIG. 25 shows the values of B _{1 to} B ₈ , and FIG. 26 shows the values of C _{1 to} C ₈ , C ₁ ′ to C ₃ ′, C _5. The values of 'and C ₇ ' are shown in FIG.

Each output A ₁ to A ₈ delay value D ₁ to D _8, since the value of the delay value D ₁ to D ₈ is respectively 128,64,16,32,8,1,4,2 cycle, Starting from the value of A ₀ , 128, 128 + 64 = 192, 192 + 16 = 208, 208 + 32 = 240, 240 + 8 = 248, 248 + 1 = 249, 249 + 4 = 253, 253 + 2 = 255 cycles, respectively. For example, when the value of the input A ₀ is x ₀ , the value of the output A ₁ of D ₁ is x ₁₂₈ , the value of the output A ₂ of D ₂ is x ₁₉₂ , the value of the output A ₃ of D ₃ is x ₂₀₈ , output a ₇ value x ₂₅₃ values of the output a ₄ of the D ₄ is x _240, the value x ₂₄₉ output a ₆ of the value of the output a ₅ of the D ₅ is _{x 248, D 6, D 7} , D 8 The value of the output A ₈ is x ₂₅₅ .

As for the calculation result by the DMF algorithm, the calculation result by the upper stage of the DMF algorithm (for example, values of C _{1 to} C ₈ ) is stored in Acc ₁ of the accumulator 15, and the calculation result by the lower stage (for example, C ₁ ′ to C _3). 'And the values of C ₅ ' and C ₇ 'are stored in Acc ₀ of the accumulator 15.

  The conventional DSP outputs 16-bit data from the memory 17 to the ALU 13 at a time. However, the data used for the arithmetic processing is only 10 bits. Therefore, the conventional arithmetic unit outputs 6-bit data to the ALU 13 wastefully at a time.

  The ALU 13 incorporates a 32-bit wide computing unit (not shown), but the ALU 13 uses only the 10-bit width. For this reason, the conventional arithmetic unit wasted the arithmetic unit for 22 bits.

  As described above, when the arithmetic unit performs processing using data whose one word is not a standard bit width, an unused part is arranged between the I part data and the R part data. The use of the built-in arithmetic unit and the memory 17 is wasted, and there has been a problem that the arithmetic capability and the memory cannot be effectively utilized particularly when performing arithmetic processing by the DMF algorithm.

In order to solve such a problem, the calculation method according to the present invention reads the first and second data strings stored in the area specified by the first address of the memory and uses the second address of the memory. The third and fourth data strings stored in the designated area are read, the fourth data string in the read data string is temporarily stored in the register, and the read data string The second and third data strings are shifted, the first data string in the read data string and the shifted second and third data strings are operated, and temporarily stored in the register to stored mixing the obtained data string by the fourth data string and arithmetic, the region data string obtained by the calculation in the mixed data sequence specified by the first address of the memory 4th data in the mixed data stored in The stored in the area specified by the second address memory.

The calculation method according to the present invention has the effect that the amount of memory used in DMF processing can be reduced.
In the calculation method according to the present invention, for example, the portion of the read data that is not used for calculation is set as the fourth data string, thereby requiring time for calculating the portion that is not used for calculation. In addition, there is an effect that output data can be easily generated, and an effect that unused data can be written as it is at the time of overwriting.

  In the present embodiment, a 16-bit width register and a mixing circuit are provided, and the control unit performs special control, thereby reducing the amount of memory used (particularly, the amount of memory used during arithmetic processing based on the DMF algorithm). The purpose is to reduce to / 3.

  FIG. 1 is a diagram showing a configuration of an arithmetic unit according to the present invention.

  The arithmetic device according to the present invention is configured so that one word can be operated at a high speed and with a small amount of memory with a data not having a standard 2 n bit width.

  The embodiment of the present invention will be described below by taking a DSP installed in a third generation mobile phone as an example. Each figure is only shown schematically to the extent that the present invention can be understood. Moreover, in each figure, about the common element, the same code | symbol is attached | subjected and description is abbreviate | omitted.

  The DSP according to the present embodiment includes a register 27 and a mixing circuit 29 as shown in FIG. The register 27 is provided for temporarily storing data output from the memory 17. The mixing circuit 29 is provided to replace a part of the data output from the memory 17 (that is, data temporarily stored in the register 27) with data output from the ALU 13 '. The register 27 and the mixing circuit 29 are also controlled by a control unit (not shown) in the same manner as other elements. Further, as will be described later, the ALU 13 ′ according to the present embodiment has a function of dividing the carry signal at an arbitrary position when the divided signal K is input.

  By the way, the present embodiment is intended to make it possible to use a general-purpose memory that is already widely used as the memory 17. Therefore, in the present embodiment, the data stored in the memory 17 is arranged as shown in FIGS. 2 to 12, and the control unit (not shown) specializes the memory 17 so that the ALU 13 ′ can easily calculate. Control is in progress.

  2 to 12 are diagrams showing the arrangement of data stored in two memory blocks. FIG. 2 shows a rough arrangement of data stored in the memory 17, and FIGS. The detailed arrangement of the data stored in 17 is shown. 3 to 12, “[-In-]” is an area storing I part data, “[−Rn−]” is an area storing R part data, and “*” is not yet stored. It shows the area where usage data is stored.

  As shown in FIGS. 2 to 12, the memory 17 adds 24-bit wide data by adding unused data of 4-bit width to data based on a combination of I-part data of 10-bit width and R-part data of 10-bit width. These are continuously stored in the first and second memory blocks 19 and 21 each having a 16-bit width. In the present embodiment, by storing data in this way, the unused area of the memory 17 is reduced from the conventional 12/32 = 37.5% to 4/32 = 12.5%.

  The bit width of unused data is desirably set so that the head of subsequent data starts from the 0th bit or the 8th bit for reasons described later. For example, in the example shown in FIG. 2, the bit width of the I part data is 10 bits and the bit width of the R part data is 10 bits, so the bit width of the unused data is 4 bits. If the bit width of the I part data or the R part data changes, it is desirable to change the bit width of the unused data so that the head of the subsequent data starts from the 0th bit or the 8th bit accordingly.

  In the present embodiment, a control unit (not shown) performs the following control on the memory 17.

  That is, for example, it is assumed that the memory 17 stores data as shown in FIGS.

A control unit (not shown) supplies the input A ₀ to the ALU 13 ′ based on the DMF algorithm shown in FIGS. Here, the input A ₀ is I0 part data and R0 part data. The I0 part data and the R0 part data are stored at addresses 0 and 1 of the memory 17. Therefore, a control unit (not shown) supplies the data stored in the addresses 0 and 1 of the memory 17 to the ALU 13 ′ via the shifter 11 and also supplies the data to the register 27 for temporary storage therein. Next, a control unit (not shown) causes the ALU 13 ′ to execute one calculation process and temporarily stores the calculation result in an accumulator (hereinafter referred to as Acc) 15. Next, the data temporarily stored in the register 27 is output to the mixing circuit 29, and the operation result temporarily stored in the Acc 15 is output to the mixing circuit 29. Next, the mixing circuit 29 is made to mix both by control described later, and the mixing result is output to the memory 17. Next, the mixed result is stored in the memory 17 at addresses 0 and 1, which are the original addresses.

The control unit (not shown) supplies an output A ₁ of the delay values D ₁ to ALU 13 'based on the DMF algorithm. Here, since the value of the delay value D ₁ is 128 cycles, the output A ₁ is stored data with a delay of 0 + 128 = 128 cycles. That is, I128 part data and R128 part data. The I128 part data and R128 part data are stored at addresses 192 and 193 of the memory 17. Therefore, a control unit (not shown) supplies the data stored at the addresses 192 and 193 of the memory 17 to the ALU 13 ′ via the shifter 11 and also supplies the data to the register 27 for temporary storage therein. Next, a control unit (not shown) causes the ALU 13 ′ to execute one calculation process, and temporarily stores the calculation result in the Acc 15. Next, the data temporarily stored in the register 27 is output to the mixing circuit 29, and the operation result temporarily stored in the Acc 15 is output to the mixing circuit 29. Next, the mixing circuit 29 is made to mix both by control described later, and the mixing result is output to the memory 17. Next, the mixed result is stored in the memory 17 at addresses 192 and 193 which are the original addresses.

The control unit (not shown) supplies an output A ₂ of the delay value D ₂ to ALU 13 'based on the DMF algorithm. Here, the output A ₂ is stored data with a delay of 128 + 64 = 192 cycles since the value of the delay value D ₂ is 64 cycles. That is, I192 part data and R192 part data. The I192 part data and R192 part data are stored at addresses 288 and 289 of the memory 17. Therefore, a control unit (not shown) supplies the data stored at the addresses 288 and 289 of the memory 17 to the ALU 13 ′ via the shifter 11 and also supplies the data to the register 27 for temporary storage therein. Next, a control unit (not shown) causes the ALU 13 ′ to execute one calculation process, and temporarily stores the calculation result in the Acc 15. Next, the data temporarily stored in the register 27 is output to the mixing circuit 29, and the operation result temporarily stored in the Acc 15 is output to the mixing circuit 29. Next, the mixing circuit 29 is made to mix both by control described later, and the mixing result is output to the memory 17. Next, the mixed result is stored in the memory 17 at addresses 288 and 289 which are the original addresses.

The control unit (not shown) supplies an output A ₃ of the delay value D ₃ to ALU 13 'based on the DMF algorithm. Here, the output A ₃ is stored data with a delay of 192 + 16 = 208 cycles since the value of the delay value D ₃ is 16 cycles. That is, I208 part data and R208 part data. The I208 part data and R208 part data are stored at addresses 312 and 313 of the memory 17. Therefore, a control unit (not shown) supplies the data stored in the addresses 312 and 313 of the memory 17 to the ALU 13 ′ via the shifter 11 and also supplies the data to the register 27 for temporary storage therein. Next, a control unit (not shown) causes the ALU 13 ′ to execute one calculation process, and temporarily stores the calculation result in the Acc 15. Next, the data temporarily stored in the register 27 is output to the mixing circuit 29, and the operation result temporarily stored in the Acc 15 is output to the mixing circuit 29. Next, the mixing circuit 29 is made to mix both by control described later, and the mixing result is output to the memory 17. Next, the mixed result is stored in the memory 17 at addresses 312 and 313 which are the original addresses.

The control unit (not shown) supplies an output A ₄ of the delay values D ₄ to ALU 13 'based on the DMF algorithm. Here, the output A ₄ is the data stored with a delay of 208 + 32 = 240 cycles because the value of the delay value D ₄ is 32 cycles. That is, it becomes I240 part data and R240 part data. The I240 part data and R240 part data are stored at addresses 360 and 361 of the memory 17. Therefore, a control unit (not shown) supplies the data stored in the addresses 360 and 361 of the memory 17 to the ALU 13 ′ via the shifter 11 and also supplies the data to the register 27 for temporary storage therein. Next, a control unit (not shown) causes the ALU 13 ′ to execute one calculation process, and temporarily stores the calculation result in the Acc 15. Next, the data temporarily stored in the register 27 is output to the mixing circuit 29, and the operation result temporarily stored in the Acc 15 is output to the mixing circuit 29. Next, the mixing circuit 29 is made to mix both by control described later, and the mixing result is output to the memory 17. Next, the mixed result is stored in the memory 17 at addresses 360 and 361 which are the original addresses.

The control unit (not shown) supplies an output A ₅ of the delay values D ₅ to ALU 13 'based on the DMF algorithm. Here, the output A ₅ is the data stored with a delay of 240 + 8 = 248 cycles because the value of the delay value D ₅ is 8 cycles. That is, I248 part data and R248 part data. The I248 part data and R248 part data are stored at addresses 372 and 373 of the memory 17. Therefore, a control unit (not shown) supplies the data stored at the addresses 372 and 373 of the memory 17 to the ALU 13 ′ via the shifter 11 and also supplies the data to the register 27 for temporary storage therein. Next, a control unit (not shown) causes the ALU 13 ′ to execute one calculation process, and temporarily stores the calculation result in the Acc 15. Next, the data temporarily stored in the register 27 is output to the mixing circuit 29, and the operation result temporarily stored in the Acc 15 is output to the mixing circuit 29. Next, the mixing circuit 29 is made to mix both by control described later, and the mixing result is output to the memory 17. Next, the mixed result is stored in the memory 17 at addresses 372 and 373 which are the original addresses.

The control unit (not shown) supplies an output A ₆ of the delay values D ₆ to ALU 13 'based on the DMF algorithm. Here, the output A ₆ is stored data with a delay of 248 + 1 = 249 cycles since the value of the delay value D ₆ is one cycle. That is, it becomes I249 part data and R249 part data. The I249 part data and the R249 part data are stored at addresses 373 and 374 of the memory 17. Therefore, a control unit (not shown) supplies the data stored at the addresses 373 and 374 of the memory 17 to the ALU 13 ′ via the shifter 11 and also supplies the data to the register 27 for temporary storage therein. Next, a control unit (not shown) causes the ALU 13 ′ to execute one calculation process, and temporarily stores the calculation result in the Acc 15. Next, the data temporarily stored in the register 27 is output to the mixing circuit 29, and the operation result temporarily stored in the Acc 15 is output to the mixing circuit 29. Next, the mixing circuit 29 is made to mix both by control described later, and the mixing result is output to the memory 17. Next, the mixed result is stored in the memory 17 at addresses 373 and 374 which are the original addresses.

The control unit (not shown) supplies an output A ₇ of the delay value D ₇ to ALU 13 'based on the DMF algorithm. Here, the output A ₇ is stored data with a delay of 249 + 4 = 253 cycles since the value of the delay value D ₇ is 4 cycles. That is, I253 part data and R253 part data. The I253 part data and R253 part data are stored at addresses 379 and 380 of the memory 17. Therefore, a control unit (not shown) supplies the data stored at the addresses 379 and 380 of the memory 17 to the ALU 13 ′ via the shifter 11 and also supplies the data to the register 27 for temporary storage therein. Next, a control unit (not shown) causes the ALU 13 ′ to execute one calculation process, and temporarily stores the calculation result in the Acc 15. Next, the data temporarily stored in the register 27 is output to the mixing circuit 29, and the operation result temporarily stored in the Acc 15 is output to the mixing circuit 29. Next, the mixing circuit 29 is made to mix both by control described later, and the mixing result is output to the memory 17. Next, the mixed result is stored in the memory 17 at addresses 379 and 380 which are the original addresses.

The control unit (not shown) supplies an output A ₈ delay value D ₈ to ALU 13 'based on the DMF algorithm. Here, the output A ₈ is stored data with a delay of 253 + 2 = 255 cycles because the value of the delay value D ₈ is 2 cycles. That is, I255 part data and R255 part data. The I255 part data and R255 part data are stored at addresses 382 and 383 of the memory 17. Therefore, a control unit (not shown) supplies the data stored at the addresses 382 and 383 of the memory 17 to the ALU 13 ′ via the shifter 11 and also supplies the data to the register 27 for temporary storage therein. Next, a control unit (not shown) causes the ALU 13 ′ to execute one calculation process, and temporarily stores the calculation result in the Acc 15. Next, the data temporarily stored in the register 27 is output to the mixing circuit 29, and the operation result temporarily stored in the Acc 15 is output to the mixing circuit 29. Next, the mixing circuit 29 is made to mix both by control described later, and the mixing result is output to the memory 17. Next, the mixed result is stored in the memory 17 at addresses 382 and 383 which are the original addresses.

Thereafter, the input A ₀ of the next delay value D ₁ is arranged in the I255 part data and the R255 part data at the address 383. In the next arithmetic processing, a control unit (not shown) regards the address 383 as a new address 0 and performs the same operation as described above.

  In the above-described operation, there are three patterns of data transition, which are shown in FIGS. FIG. 13 is a diagram showing a transition process of data stored in two memory blocks. In FIG. 13, a plain area indicates a portion where data is updated, and a hatched area indicates a portion where data is not updated.

  In the transition process of each pattern shown in FIGS. 13A to 13C, each configuration of the DSP operates as follows.

  In the pattern 1 shown in FIG. 13A, a control unit (not shown) first reads data stored at the address n from the first memory block 19 and also stores data stored at the address n + 1 from the second memory block 21. Is output to the shifter 11 and the register 27. The data stored at address n is part of the I0 part data and R0 part data. The data stored at the address n + 1 is a part of R0 part data, unused data, and I1 part data.

  The shifter 11 adjusts the phase by shifting the data transmitted from the accumulator 15 and the memory 17 by a predetermined bit. Then, the result is output to the ALU 13 '.

  FIG. 14 is a diagram showing an internal configuration of the ALU 13 'according to the present embodiment. In FIG. 14, A and B are data transmitted from the first and second memory blocks 19 and 21 via the shifter 11, C is a carry signal, K is a divided signal, X is an output signal, and FA is an addition operation circuit. It is.

  The ALU 13 'is a combination of I0 part data and R0 part data (hereinafter referred to as data used for calculation) based on a divided signal K transmitted from a control unit (not shown) with respect to data transmitted from the shifter 11. The data is divided into other data (hereinafter referred to as data that is not used for calculation), and data used for calculation is acquired. Note that the division is performed when the division signal K is zero. The data used for the calculation corresponds to the output signal X shown in FIG.

  Next, the ALU 13 ′ acquires from the accumulator 15 the operation result in the same cycle as the previous operation processing cycle (hereinafter referred to as the operation result of the previous cycle). The calculation result of the previous cycle is data based on a combination of I part data and R part data. Then, the ALU 13 ′ uses the data obtained for the calculation acquired from the shifter 11 and the calculation result of the previous cycle acquired from the accumulator 15 to execute the calculation using the DMF algorithm described above. In FIG. 13A, the calculation result at this time is shown as data by a combination of the I0 ′ part data and the R0 ′ part data.

  The ALU 13 ′ outputs the calculation result to the accumulator 15. The accumulator 15 stores the calculation result by the ALU 13 ′ and outputs the calculation result to the mixing circuit 29 along the first route 23. In addition, the calculation result is output to the ALU 13 ′ along the second route 25 at a predetermined timing based on control of a control unit (not shown).

  On the other hand, the register 27 outputs the data transmitted from the memory 17 at a predetermined timing to the mixing circuit 29 along the third route 23 'based on the control of a control unit (not shown).

  The mixing circuit 29 divides the data transmitted from the register 27 along the third route 23 ′ every 8 bits based on the control of the control unit (not shown), and is a part (that is, the first portion) used for the calculation. The lower 8 bits and the upper 8 bits stored in the first memory block 19 and the lower 8 bits stored in the second memory block 21) along the first route 23. Replace with data transmitted from. Then, a portion that is not used for calculation (that is, upper 8 bits of data stored in the second memory block 21) is added to generate output data, which are output to the memory 17.

  The memory 17 stores the output data transmitted from the mixing circuit 29 at the original address. That is, the lower 16 bits of the output data are stored at the address n of the first memory block 19 and the upper 16 bits are stored at the address n + 1 of the second memory block 21.

  As a result, according to pattern 1, the data stored in the first and second memory blocks 19 and 21 is the original value only in the upper 8 bits stored in the second memory block 21. Is updated to a new value.

  In the pattern 2 shown in FIG. 13B, a control unit (not shown) first reads data stored in the address n + 1 from the second memory block 21 and data stored in the address n + 2 from the first memory block 19. Is output to the shifter 11 and the register 27. The data stored at address n + 1 is a part of R0 'part data, unused data, and part of I1 part data. The data stored at the address n + 2 is a part of I1 part data, a part of R1 part data, and unused data.

  The shifter 11 adjusts the phase by shifting the data transmitted from the accumulator 15 and the memory 17 by a predetermined bit. Then, the result is output to the ALU 13 '.

  The ALU 13 ′ divides the data transmitted from the shifter 11 into data used for calculation and data not used for calculation based on the division signal K, and acquires data used for calculation.

  Next, the ALU 13 ′ acquires the calculation result of the previous cycle from the accumulator 15. Then, the ALU 13 ′ uses the data provided for the calculation acquired from the shifter 11 and the calculation result of the previous cycle acquired from the accumulator 15 to execute the calculation by the DMF algorithm. In FIG. 13B, the calculation result at this time is shown as data by a combination of the I1 ′ part data and the R1 ′ part data.

  The ALU 13 ′ outputs the calculation result to the accumulator 15. The accumulator 15 stores the calculation result by the ALU 13 ′ and outputs the calculation result to the mixing circuit 29 along the first route 23. In addition, the calculation result is output to the ALU 13 ′ along the second route 25 at a predetermined timing based on control of a control unit (not shown).

  On the other hand, the register 27 outputs the data transmitted from the memory 17 at a predetermined timing to the mixing circuit 29 along the third route 23 'based on the control of a control unit (not shown).

  The mixing circuit 29 divides the data transmitted from the register 27 along the third route 23 ′ every 8 bits based on the control of the control unit (not shown), and is a part (that is, the first portion) used for the calculation. The upper 8 bits stored in the second memory block 21 and the upper 8 bits and the lower 8 bits stored in the first memory block 19) are transmitted from the ALU 13 ′ along the first route 23. Replace with the data to be processed. Then, a portion not subjected to the operation (that is, lower 8 bits data stored in the second memory block 21) is added to generate output data, which are output to the memory 17.

  The memory 17 stores the output data transmitted from the mixing circuit 29 at the original address. That is, the lower 16 bits of the output data are stored at the address n + 1 of the second memory block 21, and the upper 16 bits are stored at the address n + 2 of the first memory block 19.

  As a result, the data stored in the first and second memory blocks 19 and 21 according to the pattern 2 is the original value only in the lower 8 bits stored in the second memory block 21. Is updated to a new value.

  In the pattern 3 shown in FIG. 13C, first, a control unit (not shown) reads data stored at the address n + 3 from the second memory block 21 and data stored at the address n + 4 from the first memory block 19. Is output to the shifter 11 and the register 27. The data stored at the address n + 3 is a part of the I2 part data and the R2 part data. The data stored at the address n + 4 is a part of R2 part data, unused data, and I3 part data.

  The shifter 11 adjusts the phase by shifting the data transmitted from the accumulator 15 and the memory 17 by a predetermined bit. Then, the result is output to the ALU 13 '.

  The ALU 13 ′ divides the data transmitted from the shifter 11 into data used for calculation and data not used for calculation based on the division signal K, and acquires data used for calculation.

  Next, the ALU 13 ′ acquires the calculation result of the previous cycle from the accumulator 15. Then, the ALU 13 ′ uses the data provided for the calculation acquired from the shifter 11 and the calculation result of the previous cycle acquired from the accumulator 15 to execute the calculation by the DMF algorithm. In FIG. 13C, the calculation result at this time is shown as data by a combination of the I2 ′ part data and the R2 ′ part data.

  The ALU 13 ′ outputs the calculation result to the accumulator 15. The accumulator 15 stores the calculation result by the ALU 13 ′ and outputs the calculation result to the mixing circuit 29 along the first route 23. In addition, the calculation result is output to the ALU 13 ′ along the second route 25 at a predetermined timing based on control of a control unit (not shown).

  On the other hand, the register 27 outputs the data transmitted from the memory 17 at a predetermined timing to the mixing circuit 29 along the third route 23 'based on the control of a control unit (not shown).

  The mixing circuit 29 divides the data transmitted from the register 27 along the third route 23 ′ every 8 bits based on the control of the control unit (not shown), and is a part (that is, the first portion) used for the calculation. 2, lower 8 bits and upper 8 bits stored in the memory block 21, and lower 8 bits data stored in the first memory block 19) are transmitted from the ALU 13 ′ along the first route 23. Replace with the data to be processed. Then, a portion not subjected to calculation (that is, upper 8 bits of data stored in the first memory block 19) is added to generate output data, which are output to the memory 17.

  The memory 17 stores the output data transmitted from the mixing circuit 29 at the original address. That is, the lower 16 bits of the output data are stored at the address n + 3 of the second memory block 21, and the upper 16 bits are stored at the address n + 4 of the first memory block 19.

  As a result, according to the pattern 3, the data stored in the first and second memory blocks 19 and 21 is only the upper 8 bits stored in the first memory block 19 with the original value. Is updated to a new value.

  FIG. 15 is a diagram showing transition of output data in the mixing circuit 29. In FIG. 15, the upper Acc [23: 0] and Reg [7: 0] on the left side and the lower [Reg [15: 8] and Acc [23: 0] on the left side indicate that the mixing circuit 29 is connected to the Acc 15 and the register 27. The data generated by mixing the outputs of. Also, Out [31: 0] on the right side is Acc [23: 0], Reg [7: 0] on the upper left side or the left side according to the original address of the data read from the memory 17 by the mixing circuit 29. This is output data to be output to the memory 17 by selecting either Reg [15: 8] or Acc [23: 0] in the lower stage.

  Here, Acc [x: y] represents output data from the xth bit to the yth bit from the accumulator 15, and Reg [x: y] represents an output from the xth bit to the yth bit from the register 27. It represents data. For example, Acc [23: 0] and Reg [7: 0] are 24 bits wide output data from the 0th bit to the 23rd bit from the accumulator 15, and 8 bits from the 0th bit to the 7th bit from the register 27. Represents bit width output data combinations. Out [x: y] represents output data from the x-th bit to the y-th bit from the mixing circuit 29. For example, Out [31: 0] expresses output data having a 32-bit width from the 0th bit to the 31st bit from the mixing circuit 29.

Note that a control unit (not shown) arranges the input A ₀ of the next delay value D ₁ in the I255 part data and R255 part data at the address 383 for each calculation process, and sets the address 383 at the next calculation process. The processing is executed assuming that the new address is 0. This is the same as processing by moving the reference point one step to the left when assuming that the address 0 and the address 383 of the memory 17 are connected in a ring shape. Therefore, the DSP can suitably output data used for calculation with simple control.

  Such control will be described in detail below with reference to FIG. FIG. 16 is a diagram showing the arrangement of cyclic data. In FIG. 16, hatched areas indicate data input locations.

A control unit (not shown) outputs the data stored at a predetermined address determined by the DMF algorithm in the memory 17 as outputs of delay values D ₁ , D ₂ , D ₃ , D ₄ , D ₅ , D ₆ , D ₇ , D ₈ . Use cyclically as data. Then, for each calculation process, these data are updated to the calculation results calculated by the above-described patterns 1 to 3 as output data of the delay values D _{1 to} D ₈ . Note that the output data of the final delay value D ₈ becomes input data of the first delay value D _{0 in} the next arithmetic processing. In this way, the calculation process of one cycle of the DMF algorithm shown in FIGS. 22 and 23 is executed. Then, the control unit (not shown) moves the position of the reference point shown in FIG. 16 counterclockwise by a predetermined amount (here, one), and executes the next calculation process. The arithmetic processing at this time is the same as the above-described operation. In this manner, a control unit (not shown) can easily read out the input / output corresponding to each delay value from the memory 17 one after another. Such a function can be easily realized by using the modulo addressing provided as standard in the DSP.

  The operation of each component inside the DSP will be described below. The ALU 13 'can cut the carry signal C at an arbitrary bit position based on the division signal K and the register value. In this embodiment, the ALU 13 'is cut with a 10-bit width.

  When the configuration of data stored in the memory 17 is pattern 1 shown in FIG. 13A, each configuration in the DSP operates as follows.

  First, a control unit (not shown) reads data having a total width of 32 bits from predetermined addresses of the first memory block 19 and the second memory block 21 and outputs the data to the shifter 11 and the register 27. The shifter 11 outputs the data as it is to the ALU 13 'without shifting the data. The register 27 temporarily stores data read from predetermined addresses of the first memory block 19 and the second memory block 21.

Thereafter, the ALU 13 ′ executes the arithmetic processing and outputs the arithmetic result to Acc ₀ and Acc ₁ .

Acc ₀ and Acc ₁ temporarily store the calculation result and then output it to the shifter 11. The shifter 11 outputs the calculation result as it is to Acc ₀ and Acc ₁ via the ALU 13 ′. Acc ₀ and Acc ₁ temporarily store the operation result again.

Thereafter, the register 27 outputs the stored data to the mixing circuit 29, and Acc ₀ and Acc ₁ output the calculation result by the ALU 13 ′ to the mixing circuit 29.

Next, the mixing circuit 29 stores the data stored in the register 27, Acc _0, and Acc ₁ so that the 8 bits on the least significant bit (LSB) side become the data stored in the register 27. Then, the calculation result by the ALU 13 ′ is mixed and the mixed result is output to the memory 17. The memory 17 stores the mixed result at the original addresses of the first memory block 19 and the second memory block 21.

  When the configuration of data stored in the memory 17 is pattern 2 shown in FIG. 13B, each configuration in the DSP operates as follows.

  First, a control unit (not shown) reads data having a total width of 32 bits from predetermined addresses of the second memory block 21 and the first memory block 19 and outputs the data to the shifter 11 and the register 27. The shifter 11 shifts the data to the right by 8 bits and outputs it to the ALU 13 '. The register 27 temporarily stores data read from predetermined addresses of the second memory block 21 and the first memory block 19.

Thereafter, the ALU 13 ′ executes the arithmetic processing and outputs the arithmetic result to Acc ₀ and Acc ₁ . Acc ₀ and Acc ₁ temporarily store the calculation result and then output it to the shifter 11. The shifter 11 shifts the operation result to the left by 8 bits and outputs the result to Acc ₀ and Acc ₁ via the ALU 13 ′. Acc ₀ and Acc ₁ temporarily store the calculation result by the ALU 13 ′ shifted 8 bits to the left.

Thereafter, the register 27 outputs the stored data to the mixing circuit 29, and Acc ₀ and Acc ₁ output the calculation result by the ALU 13 ′ shifted to the left by 8 bits to the mixing circuit 29.

Next, the mixing circuit 29 stores the data stored in the register 27, Acc _0, and Acc ₁ so that the 8 bits on the most significant bit (MSB) side become the data stored in the register 27. Then, the calculation result by the ALU 13 ′ is mixed and the mixed result is output to the memory 17. The memory 17 stores the mixed result at the original addresses of the second memory block 21 and the first memory block 19.

  When the configuration of data stored in the memory 17 is pattern 3 shown in FIG. 13C, each configuration in the DSP operates as follows.

  First, a control unit (not shown) reads data having a total width of 32 bits from predetermined addresses of the second memory block 21 and the first memory block 19 and outputs the data to the shifter 11 and the register 27. The shifter 11 outputs the data as it is to the ALU 13 'without shifting the data. The register 27 temporarily stores data read from predetermined addresses of the second memory block 21 and the first memory block 19.

Thereafter, the ALU 13 ′ executes the arithmetic processing and outputs the arithmetic result to Acc ₀ and Acc ₁ . Acc ₀ and Acc ₁ temporarily store the calculation result and then output it to the shifter 11. The shifter 11 outputs the calculation result as it is to Acc ₀ and Acc ₁ via the ALU 13 ′. Acc ₀ and Acc ₁ temporarily store the operation result again.

Thereafter, the register 27 outputs the stored data to the mixing circuit 29, and Acc ₀ and Acc ₁ output the calculation result by the ALU 13 ′ to the mixing circuit 29.

Next, the mixing circuit 29 stores the data stored in the register 27, Acc _0, and Acc ₁ so that the 8 bits on the least significant bit (LSB) side become the data stored in the register 27. Then, the calculation result by the ALU 13 ′ is mixed and the mixed result is output to the memory 17. The memory 17 stores the mixed result at the original addresses of the second memory block 21 and the first memory block 19.

  Hereinafter, a calculation process in the ALU 13 'will be described. 17 and 18 are diagrams showing an outline of the DMF algorithm. The calculation process of the part enclosed in parentheses in FIGS. 17 and 18 will be described in detail as an example.

  First, a control unit (not shown) reads data having a total width of 32 bits from addresses 0 and 1 of the first memory block 19 and the second memory block 21 and outputs the data to the shifter 11 and the register 27. The shifter 11 outputs the data as it is to the ALU 13 'without shifting the data. The register 27 temporarily stores data read from the addresses 0 and 1 of the first memory block 19 and the second memory block 21. Thereafter, the ALU 13 'executes an arithmetic process.

At that time, first, a control unit (not shown) generates a divided signal K based on the data configuration, and the ALU 13 ′ determines the addresses 0 of the first memory block 19 and the second memory block 21 based on the divided signal K. The data read from 1 is divided to obtain the input A ₀ . Next, the ALU 13 ′ calculates A ₁ , B ₁ , C ₁ , C ₁ ′ as shown in FIG. These values are as shown in FIGS. The calculation result calculated in this way is stored in Acc ₁ of the accumulator 15 by the upper stage (for example, C ₁ ) in the diagram showing the outline of the DMF algorithm shown in FIG. B ₁ , C ₁ ′) is stored in Acc ₀ of the accumulator 15. In this way, the calculation result is stored in Acc ₀ and Acc ₁ of the accumulator 15.

In particular, the calculation result C ₁ is overwritten at the end of the data corresponding to the delay value D ₁ stored in Acc ₀ and Acc ₁ of the accumulator 15. The calculation result C ₁ is input data of the next delay value D ₂ because the data D ₁ and the data D ₂ are continuous.

  Of the data read from the addresses 0 and 1 of the first memory block 19 and the second memory block 21, the portion not used for calculation is stored in the register 27. This part is mixed with the calculation result by the mixing circuit 29. The mixing circuit 29 outputs the mixing result to the memory 17 and stores it in the addresses 0 and 1 of the first memory block 19 and the second memory block 21. Therefore, the present embodiment can easily generate output data without requiring time for calculating a portion not subjected to calculation. Also, unused data can be written as it is when overwritten.

Next, the ALU 13 ′ calculates A ₂ , B ₂ , C ₂ , and C ₂ ′ as shown in FIG. These values are as shown in FIGS. The calculation result calculated in this way is stored in Acc ₁ of the accumulator 15 by the upper stage (for example, C ₂ ) in the diagram showing the outline of the DMF algorithm shown in FIG. B ₂ , C ₂ ′) is stored in Acc ₀ of the accumulator 15. In this way, the calculation result is stored in Acc ₀ and Acc ₁ of the accumulator 15.

In particular, the calculation result C ₂ is overwritten at the end of the data corresponding to the delay value D ₂ stored in Acc ₀ and Acc ₁ of the accumulator 15. The calculation result C ₂ becomes the input data of the next delay value D ₃ because the data D ₂ and the data D ₃ are continuous.

  In this way, the ALU 13 'continuously executes the same calculation and obtains a final calculation result.

  Thereafter, the control unit (not shown) moves the position of the reference point shown in FIG. 16 counterclockwise by one, and cyclically advances the data stored in the memory 17 by one, and performs the next calculation process. Execute.

  As described above in detail, the present invention has an effect that the amount of memory used in the DMF processing can be reduced only by providing the register 27 and the mixing circuit 29 having a predetermined bit width. Therefore, for example, when applied to a DSP used in a third generation mobile phone, the amount of memory can be reduced from 510 words to 384 words, that is, 126 words.

  Moreover, since the present invention does not significantly increase the circuit, such an effect can be achieved at a very low cost.

  The present invention is not limited to the above-described embodiments, and various applications and modifications can be considered without departing from the gist of the present invention. For example, in the present embodiment, the memory 17 may be configured by a 32-bit width memory. Further, the present invention can be applied not only to a DSP but also to a device that processes data having a 9 to 12 bit width.

It is a figure which shows the structure of the arithmetic unit which concerns on this invention. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows the transition process of the data stored in two memory blocks. It is a figure which shows the internal structure of ALU which concerns on this Embodiment. It is a figure which shows the transition of the output in a mixing circuit. It is a figure which shows arrangement | positioning of cyclic data. It is a figure which shows the outline | summary of a DMF algorithm. It is a figure which shows the outline | summary of a DMF algorithm. It is a figure which shows the structure of the conventional arithmetic unit. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows arrangement | positioning of the data stored in two memory blocks. It is a figure which shows the outline | summary of a DMF algorithm. It is a figure which shows the outline | summary of a DMF algorithm. It is a chart which shows the arithmetic expression of a DMF algorithm. It is a chart which shows the arithmetic expression of a DMF algorithm. It is a chart which shows the arithmetic expression of a DMF algorithm. It is a chart which shows the arithmetic expression of a DMF algorithm.

Explanation of symbols

11 Shifter 13 'ALU
15 Accumulator 17 Memory 19 First Memory Block 21 Second Memory Block 23 First Route 23 ′ Third Route 25 Second Route 27 Register 29 Mixing Circuit

Claims (5)

Read the first and second data strings stored in the area specified by the first address of the memory,
Read the third and fourth data strings stored in the area specified by the second address of the memory,
Temporarily storing the fourth data string in the read data string in a register ;
Shifting the second and third data strings in the read data string;
Calculated by using the second and third data string in which the first data row to have been the shift in the read data sequence,
Mixing the fourth data string temporarily stored in the register and the data string obtained by the operation;
Storing the data string obtained by the calculation in the mixed data string in an area specified by the first address of the memory;
Calculation method characterized by storing the fourth data columns in the data the mixed area specified by the second address of the memory. The fourth data string calculation method according to claim 1, unused data, characterized in containing Mukoto. The length of the first data sequence, the calculation method according to claim 1 or 2, wherein the second and third are the same as the combined length of the length of the data sequence. The calculation method according to any one of claims 1 to 3, wherein the first, second, third, and fourth data strings are constituted by bit strings. The calculation method according to claim 4 , wherein the second and third data strings in the read data string are shifted by a predetermined number of bits.

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