JP2008287462A - Emulator and emulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an emulator and an emulation method in which a correct amount of delay can be set even if there is one or more cycles of delay. <P>SOLUTION: The emulator 310 has a table block 314 in which delay values predetermined according to a user voltage are stored as set values; a skew-adjustment block 311 for creating delay clocks by referring to the table block 314 and setting delays with respect to a source clock 400 according to a skew adjustment value; a CPU emulation chip 318 that operates at constant voltage; and a peripheral emulation chip 313 that operates at the user voltage to perform a program along with the CPU emulation chip 318. Using the skew-adjustment block 311, a CPU core clock 401 and a peripheral emulation clock 402 each with a delay corresponding to the user voltage are supplied respectively to the CPU emulation chip 318 and the peripheral emulation chip 313, whereby emulation is performed while synchronizing them. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an in-circuit emulator for a microcomputer and an emulation method, and more particularly, to an emulator and an emulation method that achieve synchronization adjustment by voltage fluctuation.

  A high-function emulator has many functions necessary for debugging software in a CPU (Central Processing Unit). Many functions include, for example, a break function that stops a program at an arbitrary location, a trace function that traces the locus of program execution, and a real-time RAM (Random Access Memory) monitor function that monitors the memory contents being executed. These are realized by connecting many additional circuits to the original CPU (hereinafter, a CPU having such a function is referred to as a CPU core).

  For this reason, a high-function emulator cannot mount a CPU core and peripheral functions such as a timer, a clock, and an interrupt function on a single LSI chip, and an LSI having a CPU core (hereinafter referred to as a CPU evaluation chip). .), An emulator is realized by dividing the LSI into peripheral LSIs (hereinafter referred to as peripheral evaluation chips) and wiring the two with a printed circuit board or the like.

  In recent years, it has been required to change the power supply voltage and the operating frequency during operation due to the increase in the operating speed of the product (microcomputer) to be emulated and the expansion of the operating power supply voltage range. In an actual device, an interface such as a CPU core and a memory operates with a fixed voltage of the regulator, and an IO buffer varies depending on a user voltage. Even in the emulator, it is necessary to operate the interface between the CPU evaluation chip, the memory, and the host machine at a fixed voltage.

  Peripheral evaluation chips connected to the user system are required to follow the specified power supply voltage of the user system in the same way as the IO buffer of the actual device in order to emulate the power supply voltage, operation speed, and input / output timing. ing. Therefore, the operating voltage of the CPU evaluation chip and the peripheral evaluation chip are different from each other, and the operation of the two chips is shifted due to the delay in the substrate. Therefore, the skew (delay) of the operation clock of the CPU evaluation chip and the peripheral evaluation chip is adjusted. Need to work properly.

  Therefore, Patent Document 1 discloses a method for adjusting the skew between the CPU core and the peripheral EVA chip. FIG. 13A shows an emulation circuit described in Patent Document 1. As shown in FIG. 13A, the emulation chip 620 is a chip that interfaces a microcomputer 610 and a host machine 630 that is an emulator. Here, an emulation chip (hereinafter referred to as a CPU evaluation chip) 620 shown in FIG. 13A corresponds to the above-described CPU core. The microcomputer 610 corresponds to the peripheral evaluation chip described above.

  The emulation chip (CPU evaluation chip) 620 includes an oscillation circuit 621, a timing generator 622, a data bus latch 623, and a comparison circuit 624. The host machine 630 is connected to the CPU evaluation chip 620. The microcomputer (peripheral evaluation chip) 610 includes a timing generator 611 and an output circuit 612.

  The output of the oscillation circuit 621 of the CPU evaluation chip 620 is connected to the timing generator 611 of the microcomputer 610 and the delay circuit 660 via the voltage level conversion circuit 650. The output of the delay circuit 660 is connected to the input of the timing generator 622 of the CPU evaluation chip 620. The output of the timing generator 611 of the microcomputer 610 is connected to the input of the output circuit 612 of the microcomputer 610. The output of the output circuit 612 of the microcomputer 610 is connected to the bus of the data bus latch 623 of the CPU evaluation chip 620 via the voltage level conversion circuit 650. The data bus latch 623 of the CPU evaluation chip 620 receives the clock from the clock generator 622 of the CPU evaluation chip 620 and outputs data to the memory 640.

  The comparison circuit 624 of the CPU evaluation chip 620 has one input connected to the output of the timing generator 622 of the CPU evaluation chip 620 and the other input connected to the output of the timing generator 611 of the microcomputer 610 via the voltage level conversion circuit 650. ing. The output of the comparison circuit 624 is monitored externally, and the delay amount of the delay circuit 660 is set based on the monitoring result.

  Next, the operation of the emulation circuit described in Patent Document 1 will be described. The comparison circuit 624 compares the clock 804 and the clock 805. The clock 804 is a clock generated by delaying the clock 800, which is the output of the oscillation circuit 621, in the delay circuit 660 and using it as an input to the timing generator 622. As the clock 805, the signal 801 delayed by the clock 800 of the oscillation circuit 621 passing through the voltage level conversion circuit 650 is input to the timing generator 611 of the microcomputer 610, and the generated clock is sent to the CPU via the voltage conversion circuit 650. This is a signal input to the evaluation chip 620. By setting the delay amount of the delay circuit 660 based on the comparison output signal 806 of the comparison circuit 624, the strobe signal 803 output from the timing generator 622 of the CPU evaluation chip 620 to the data bus latch 623 and the data bus signal 700 are set to voltage. It can be synchronized with the data bus signal 701 input to the data bus latch 623 through the level conversion circuit 650.

  FIG. 13B is a timing chart showing the operation of the emulation circuit shown in FIG. A clock 800 is a clock signal generated from the oscillation circuit 621. The clock 801 generates a delay t1 caused by receiving the clock 800 and passing through the voltage level conversion circuit 650 with respect to the clock 800 and a wiring delay.

  In the microcomputer 610, the clock 801 is used and the timing generator 611 generates the clock 805 and the strobe signal 802. In the CPU evaluation chip 620, in the data bus latch 623, the data bus signal 700 output from the microcomputer 610 latches the data bus signal 701 that has passed through the voltage level conversion circuit 650 by the strobe signal 803, and writes it to the memory 640.

  At this time, the data bus signal 701 obtained by the CPU evaluation chip 620 is delayed from the data bus signal 700 by t3 due to the delay of the voltage level conversion circuit 650 and the wiring delay. On the other hand, in the CPU evaluation chip 620, the basic clock 804 and the strobe signal 803 are generated by the timing generator 622 from the signal delayed from the clock 800 by the delay circuit 660. Here, in order for the CPU evaluation chip 620 to reliably capture the data bus signal 701 from the microcomputer 610, the clock 801 is delayed from passing through the voltage level conversion circuit 650 from the clock 800 generated from the oscillation circuit, The delay circuit 660 causes the oscillation circuit 621 by the total time of the delay t1 due to the wiring delay and the delay due to the data bus signal 701 passing through the voltage level conversion circuit 650 and the delay t3 with respect to the data bus signal 700 due to the wiring delay. This is made possible by delaying the strobe signal 803 from the clock 800 generated from the above.

In order to determine the delay amount of the delay circuit 660, the clock 805 of the microcomputer 610 and the clock 804 passed through the delay circuit 660 are compared by the comparison circuit 624, and the high level time of the output signal 806 is delayed with the delay amount t1. Since the difference between the total time of the quantity t3 and the time delayed by the delay circuit 660 is considered (this is the delay quantity t2), the signal 806 is monitored so that the high level period is eliminated, that is, the delay quantity t2 is zero. By adjusting so as to become, it is possible to set the correct delay amount. As a result, the strobe signal 803 output from the timing generator 622 of the CPU evaluation chip 620 to the data bus latch 623 and the data bus signal 700 output from the output strobe signal 802 of the timing generator 611 of the microcomputer 610 via the output circuit 612 are generated. The data bus signal 701 that passes through the voltage level conversion circuit 650 and is input to the data bus latch 623 can be synchronized.
Japanese Patent Laid-Open No. 06-161808

  However, in the method of Patent Document 1, since the delay amount is set by comparing the phases by the comparison circuit 624, the range of normal operation is within one cycle. For this reason, when the voltage changes greatly and the fluctuation range of the clock skew becomes one period or more, there is a problem that it is impossible to detect the fluctuation of one period or more.

  The example shown in FIG. 14A shows a case in which the clock 805 actually has a delay T4 with respect to the clock 804, resulting in a delay of one cycle or more of the clock 804. In this case, in the method described in Patent Document 1, a delay amount of delay T5 different from the actual delay is set. If the correct delay T4 is set, the data bus 701 is latched at the timing of the latch A and the correct Data A is latched, but the data bus 701 is latched at the timing of the latch B at the wrong delay T5. The correct data cannot be latched.

  Further, when there is a delay of one cycle or more in this way, when the operating frequency is changed by switching the mode, as shown in FIG. 14B, when the frequency is high, a delay amount T6 different from the actual is set. If it is set and the frequency is switched to a low frequency, the delay amount greatly increases to the delay amount T7, which may cause further malfunctions due to the time required for adjustment.

  Further, in this Patent Document 1, the output comparison signal 806 of the comparison circuit 624 is monitored and adjusted in order to synchronize the timing of the operation clock. However, the original synchronization with the path on the clock delay adjustment board is desired. Since the path to the input of the data bus latch 623 is not completely the same, there is a problem that the delay on the board cannot be adjusted.

  An emulator according to the present invention is an emulator that realizes the operation of the microcomputer including a CPU core part that realizes a CPU function of the microcomputer and a peripheral part that realizes peripheral functions, and which is a source output from a clock generator A skew adjustment unit that inputs a clock and generates a first operation clock supplied to the CPU core unit and a second operation clock supplied to the peripheral unit, and a user voltage supplied to the peripheral unit And a setting value table in which setting values for determining a delay amount to be added to the first or second operation clock are stored, and the skew adjustment unit includes the setting values. Is used to adjust the skew between the first operation clock and the second operation clock.

  An emulation method according to the present invention is obtained in advance according to a CPU core unit that implements a CPU function of a microcomputer and a peripheral unit that implements peripheral functions, and a user voltage supplied to the peripheral unit, and is supplied to the CPU core unit. The microcomputer operation is emulated by a setting value table storing a setting value for determining a delay amount added to the first operation clock to be supplied or the second operation clock supplied to the peripheral portion. An emulation method for measuring the user voltage, selecting a predetermined setting value from the setting value table based on the measurement result, and selecting the first setting based on the selected predetermined setting value. The skew between the operation clock and the second operation clock is adjusted.

  In the present invention, the delay value obtained in advance according to the user voltage is stored as a set value, and the first and second operation clocks are generated with reference to the set value table. The first and second operation clocks having the correct delay amount can be generated to synchronize the CPU core unit and the peripheral unit.

  In the present invention, it is possible to provide an emulator and an emulation method capable of setting and emulating a correct delay amount even when there is a delay of one cycle or more.

Embodiment 1 FIG.
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. FIG. 1 is a diagram showing the entire system of an in-circuit emulator. As shown in FIG. 1, the in-circuit emulator 310 is for the purpose of developing the target system of the user and debugging the software embedded in the microcomputer. The in-circuit emulator 310 operates in the same manner as an actual microcomputer placed on the user target. It is a device that enables debugging functions such as tracing.

  The emulator 310 according to the present embodiment is an emulator that realizes the operation of a microcomputer that includes a CPU core 312 that realizes the CPU function of the microcomputer and a peripheral evaluation chip 313 that realizes peripheral functions, and is output from the clock generator 317. Input to the CPU core 312, a skew adjustment block 311 that generates a first operation clock 401 supplied to the CPU core 312 and a second operation clock 402 supplied to the peripheral evaluation chip 313, and the peripheral evaluation chip 313. And a table block in which setting values for determining a delay amount to be added to the CPU core clock 401 or the peripheral evaluation clock 402 are obtained according to the voltage value (user voltage) of the supplied user power supply. Then, the skew adjustment block 311 adjusts the skew between the CPU core clock 401 and the peripheral evaluation clock 402 based on the set value.

  Specifically, it is configured as follows. That is, the emulator 310 includes an LSI CPU evaluation chip 318 having a CPU core 312 in which a debugging function is added to an actual microcomputer CPU function, a peripheral evaluation chip 313 having an actual microcomputer peripheral function, other host control MCU 2, and emulation memory. 3, a level shifter 4, a clock generator 317, a target I / F 6, and a host interface (not shown).

  User power is supplied from the user target board 5 via the target I / F 6. The peripheral evaluation chip 313 directly connected to the user target board 5 operates following the user power supplied from the user target board 5, and the emulation memory 3, the host control MCU 2, the clock generator 317, and the CPU evaluation chip 318 are external. It operates with 3.3V fixed supplied from AC power supply. The level shifter 4 uses a 3.3V power supply as a driving power supply for the input / output terminals of the level shifter on the CPU evaluation chip 318 side, and uses a user power supply as a driving power supply for the input / output terminals of the level shifter on the peripheral evaluation chip 313 side.

  The emulation memory 3 stores a user program executed by the CPU evaluation chip 318, an execution result, and the like. The clock generator 317 generates the source clock 400. The CPU evaluation chip 318 has a CPU core 312 and a skew adjustment block 311, and the host control MCU has a user voltage measurement block 315 and a table block 314.

  The table block 314 functions as a set value table in which delay values obtained in advance according to the user voltage are stored as set values. The skew adjustment block 311 refers to the table block 314 and sets the delay with respect to the source clock 400 generated by the clock generator 317 by using the skew adjustment value (setting value) stored in the table block 314 for the first operation. It functions as a skew adjustment unit that generates a CPU core clock 401 and a peripheral evaluation clock 402 as a clock and a second operation clock.

  The CPU evaluation chip 318 is a chip that operates at a constant voltage. The CPU core 312 is necessary for the CPU to debug software, for example, a break function for stopping a program at an arbitrary position, and for tracing a program execution trajectory. Many functions such as a trace function and a real-time RAM monitor function for monitoring the contents of the memory being executed are added. The user voltage measurement block 315 decodes the user voltage based on the user voltage 405, and the skew adjustment block 311 reads a set value from the table block 314 in accordance with the decoded value. The peripheral evaluation chip 313 is a chip that operates with a user voltage and executes a program together with the CPU evaluation chip 318. The CPU core 312 and the peripheral evaluation chip 313 are connected to each other via a bus 320.

  In the present embodiment, an optimum skew adjustment value table is created and recorded in the table block 314, and the skew adjustment value is set from the table block 314. Since the skew setting value written to the table block 314 can be a value of one cycle or more, a delay amount different from the actual delay amount is not set. Note that the table block 314 here refers to all non-volatile memories including FLASH, EEPROM, and the like, but is also referred to as a ROM representatively below. The timing for setting the skew adjustment value from the table block 314 is selected and set from the table block 314 by monitoring the user's use voltage and following the change in the user's use voltage. That is, the emulator 310 synchronizes the two by supplying the CPU core clock 401 and the peripheral evaluation clock 402 with delay values corresponding to the respective operating voltages to the CPU evaluation chip 318 and / or the peripheral evaluation chip 313 by the skew adjustment block 311. Execute emulation while capturing.

  FIG. 2 is a block diagram showing each function of the emulator 310 according to the first embodiment. The emulator 310 that operates in response to the operating voltage from the user power supply voltage supply unit 316 measures the voltage of the clock generator 317, the skew adjustment block 311 that receives the source clock 400 generated by the clock generator 317, and the user voltage 405. A user voltage measurement block 315, a decoder 362 that decodes the measured voltage value into an address value, a table block 314 to which the address output 404 is supplied, a CPU core clock 401 generated by the skew adjustment block 311 and peripherals It has a CPU core 312 and a peripheral evaluation chip 313 to which an evaluation clock 402 is supplied.

  Next, the operation of the emulator 310 will be described. The user voltage measurement block 315 measures the voltage of the user power supply voltage supply unit 316. The user voltage measurement block 315 outputs the address decoded by the decoder 362 to the table block 314 when the voltage value changes. The table block 314 outputs a skew setting value corresponding to the address output to the skew adjustment block 311.

  Based on the source clock 400 from the clock generator 317 and the skew adjustment value setting signal 403 from the table block 314, the skew adjustment block 311 generates a clock that gives an appropriate delay value to the source clock 400, and sends it to the CPU core 312. Supplies the CPU core clock 401 to the peripheral evaluation chip 313 and the peripheral evaluation clock 402. As a result, the CPU core and the peripheral evaluation chip can perform a synchronized operation corresponding to the user voltage.

  Here, the skew adjustment value (setting value) is a delay added to the operation clock of the CPU core 312 or the operation clock of the peripheral evaluation chip 313 in order to correct a malfunction caused by the operation difference between the CPU core 312 and the peripheral evaluation chip 313. That is.

  FIG. 3 is a diagram showing a general circuit configuration from the user voltage measurement block 315 to the output of an address from the decoder 362. In this example, the user voltage measurement block 315 supplies the voltage measurement result to the decoder 362 with 8-bit accuracy. In the decoder 362, an address corresponding to the voltage range is output from the comparison result between the comparison value of each voltage range and the user voltage measurement result. In this example, four comparison circuits 511 to 514 are provided, and the comparison voltage ranges are 5V or more, 4V <voltage <5V, 3V <voltage <4V, 2.5V <voltage <3V, 2.5V or less, respectively. The voltage range is divided. For example, when 3.54V is supplied as the voltage measurement result, the comparison circuit 511 that detects 5V or more, the comparator 512 that detects 4-5V outputs "1", and the comparison circuit 513 that detects 3-4V, The comparison circuit 514 that detects less than 2.5 V outputs “0”. The conversion unit 511 that receives these inputs, converts them into address values, and outputs them outputs “0002H” as the address output 404.

  Next, a method for creating a skew adjustment table will be described. In the present embodiment, the delay value is changed in a voltage within an arbitrary operation range to test whether or not the CPU core 312 (CPU evaluation chip 318) and the peripheral evaluation chip 313 operate normally. A skew adjustment value for each user voltage is obtained by using a value having the largest margin among delay values as a skew adjustment value, and a skew adjustment table is created.

  FIG. 4 is a flowchart showing a method for creating a skew adjustment table. The skew adjustment table is stored in the table block 314. First, an initial voltage value is set (step S1). For example, when the voltage to be tested first is 5V when the voltage is changed to 5V, 4V, 3V, 2V, the initial voltage value here is 5V.

  Step S2 and subsequent steps are steps performed in the shipping inspection step for each emulator product, and the skew adjustment value unique to the product can be adjusted thereby. First, an initial skew adjustment value is set (step S2). The initial skew adjustment value in step S2 is the minimum value that can be set for the first one. For the second and subsequent units, the test results in step S3 of the first unit are used as a reference, and the test is performed as a limited range in which an optimum value is likely to be obtained without changing the skew width in all ranges and checking. be able to.

  For example, when testing by changing the skew from −12 ns to +16 ns, the first unit needs to be tested by changing the skew from −12 ns to +16 ns, but the range that passed the first test is shown in FIG. As shown, the initial skew adjustment value for the second and subsequent units can be set to, for example, -5 ns without starting from -12 ns.

  Next, a test is performed at the set voltage value and skew adjustment value. The test object here is the emulator 310 itself, tests whether the CPU evaluation chip 318 and the peripheral evaluation chip 313 operate normally (OK or NG) for each voltage value and skew adjustment value, and records the result. (Step S3). For recording, a temporary file of test results for recording the results may be created and recorded in the host machine 1 in the test program.

  In the test, for example, a program for operating the bus 320 between the two chips of the CPU core 312 and the peripheral evaluation chip 313 is moved and compared with an expected value. Also, check whether there is any problem in operation by actually moving functions such as interrupts and memory access.

  Next, it is determined whether or not a test has been executed for all skew adjustment values (step S4). Note that all skew adjustment values are all skew setting values in a limited range for the second and subsequent units. When all the skew adjustment values have not been tested, the skew adjustment values are changed (step S5), and the process returns to step S3.

  When all the skew adjustment values have been tested, the median value of the skew setting values that have passed the test is obtained as the skew adjustment value with the largest margin from the file in which the test results are recorded. As in the example of the results shown in FIGS. 5A and 5B, the median value of the passed skew adjustment values is obtained as the skew adjustment value having the most margin in each voltage range. Then, a temporary file is separately created and recorded in the host machine using the skew adjustment value as the skew adjustment value at the measured voltage value. (Step S6).

  Then, it is determined whether or not the test has been performed for all measured voltage values (step S7). If not, the voltage value is changed (step S8), and the process returns to step S2. If all voltage values have been tested, a skew adjustment value that optimizes the skew for each voltage is written from the host machine 1 to the table block on the emulator 310 (step S9), and the process ends. In this way, the delay value is changed in a voltage within an arbitrary operation range, the CPU evaluation chip 318 and the peripheral evaluation chip 313 are tested to determine whether they operate normally, and a setting value table is generated, and this setting value table is referred to. Therefore, emulation can be executed with a clock having a correct delay value.

  FIG. 5A and FIG. 5B show examples of results when there are variations due to individual differences. FIG. 5A is a first example measured at 100 MHz. As for the skew adjustment value, the coefficient can be changed in consideration of the accuracy of the actual skew adjustment value required in the data storage range of the table and the emulator 310 according to the present embodiment.

  In this example, the skew setting value +1 corresponds to the actual skew adjustment value +1 ns. In FIG. 5A, for example, at 5.0-5.5V, the skew adjustment value to be passed is between -3 ns and +6 ns, so the +1 ns skew adjustment value with the largest margin is the optimum value. In addition, at 1.5-2.0 V, +7 ns is the optimum value. Since the measurement is performed at 100 MHz, one period is 10 ns. In this first example, there is no delay of one period or more, and the above-described phase comparison circuit of Patent Document 1 can also be operated.

  FIG. 5B is a second example similarly measured at 100 MHz. This example is a result example when the variation due to the individual difference is large, and since the delay amount is one cycle or more, it cannot be adjusted by the method described in Patent Document 1 described above. In the second example, for example, the optimum value of 5.0 to 5.5 V is −4 ns, and the optimum value of 1.5 to 2.0 V is +11 ns. That is, the difference is 15 ns, which is 10 ns (one cycle) or more. However, in this embodiment, the skew optimum value is stored in the table block 314, so that one cycle or more can be set. Therefore, as described above, it is possible to solve a shift in access timing due to the fact that setting of one period or more cannot be performed. Further, even when there is an individual difference as in the examples of FIGS. 5A and 5B, it is possible to improve according to each individual difference.

  FIG. 6 is a diagram showing an example of a table stored in the table block 314 of FIG. FIG. 6A shows a list of skew adjustment value results of FIG. That is, FIG. 6A is a correspondence table between the user voltage range and the optimum setting value of the skew at that time in the result for creating the skew adjustment table of FIG. Here, the skew setting value +1 corresponds to the actual skew adjustment value +1 ns.

  FIG. 6A shows a skew adjustment value table actually placed on the table block 314 shown in FIG. 2, corresponding to the second example described above. As for the table format, as shown in FIG. 6B, when the user's voltage range is 5.0 V or more, the data of the address “0000H” of the table block (ROM) is set as the skew setting value. The associated setting table is used. As for the set value, 16 bits are stored with a negative value in the upper 8 bits and a positive value in the lower 8 bits. Since the process of reading the skew setting value corresponds to the direct address of the table block (ROM), there is also an effect that it can be accessed quickly and easily.

  Next, details of the skew adjustment block will be described. FIG. 7 is a block diagram showing details of the skew adjustment block. The skew adjustment block 311 includes a skew setting value separation circuit 350, a skew setting value selection circuit 351, a first CPU core register 332, a second CPU core register 333, a CPU core clock switching circuit 336, a CPU core clock switching signal generation circuit 334, and a CPU. It has a core register clear circuit 335, a first CPU core clock selection circuit 330, and a second CPU core clock selection circuit 331. Further, the first peripheral evaluation chip register 342, the second peripheral evaluation chip register 343, the peripheral evaluation clock switching circuit 346, the peripheral evaluation clock switching signal generation circuit 344, the peripheral evaluation chip register clear circuit 345, and the first peripheral evaluation clock selection circuit 340. , A second peripheral evaluation clock selection circuit 341, and delay gates 321 to 324.

  Here, in the present embodiment, for example, a delay gate having a predetermined delay amount is connected in a desired number of stages, and the CPU core clock 401 and the peripheral evaluation clock 402 having the desired delay amount are generated. Accordingly, in the example shown in FIG. 7, only four delay gates are shown. However, the present invention is not limited to this, and in the case shown in FIG. 5, a clock delayed by −12 ns to +16 ns is generated. Therefore, the number of stages of delay gates is required. Further, the delay amount that can be generated may have a certain margin in consideration of the influence of manufacturing variation and the like.

  In the skew setting value separation circuit 350, the skew adjustment value setting signal 403 is divided into a positive / negative signal and an absolute value signal. The skew setting value selection circuit 351 receives the positive / negative signal and the absolute value signal from the skew setting value separation circuit 350. When the positive / negative signal is negative, the skew setting value selection circuit 351 outputs the absolute value signal to the second CPU core register 333, and when the positive / negative signal is positive, the second value. An absolute value signal is sent to the peripheral evaluation chip register 343. The other register that has not sent the absolute value signal operates to send "1".

  The second CPU core register 333 stores data from the skew setting value selection circuit 351. The first CPU core register 332 receives and stores the data of the second CPU core register 333. The source clock 400 and outputs from the delay gates 321, 322, 323, and 324 connected in series to the source clock 400 are input to the first CPU core clock selection circuit 330 and the second CPU core clock selection circuit 331. In addition, VDD is input to the first CPU core clock selection circuit 330, and GND is connected to the second CPU core clock selection circuit 331.

  Data stored in the first CPU core register 332 is input as a signal switching signal of the CPU core clock selection circuit 330, and data stored in the second CPU core register 333 is input as a signal switching signal of the second CPU core clock selection circuit 331. The outputs of the first CPU core clock selection circuit 330 and the second CPU core clock selection circuit 331 are input to the CPU core register clear circuit 335, and the output of the CPU core register clear circuit 335 is the clear signal of the first CPU core register 332. It becomes.

  Outputs of the first CPU core clock selection circuit 330 and the second CPU core clock selection circuit 331 are input to the CPU core clock switching circuit 336. The output of the first CPU core register 332 is input to the CPU core clock switching signal generation circuit 334, and the output of the CPU core clock switching signal generation circuit 334 becomes the clock switching signal of the CPU core clock switching circuit 336, and the CPU core clock switching circuit The output of 336 becomes the CPU core clock 401.

  The second peripheral evaluation chip register 343 stores the data from the skew setting value selection circuit 351. The first peripheral evaluation chip register 342 receives and stores the data of the second peripheral evaluation chip register 343. Outputs from the source clock 400 and the delay gates 321, 322, 323, and 324 connected in series to the source clock 400 are input to the first peripheral evaluation clock selection circuit 340 and the second peripheral evaluation clock selection circuit 341. In addition, VDD is input to the first peripheral evaluation clock selection circuit 340, and GND is connected to the second peripheral evaluation clock selection circuit 341.

  The data stored in the first peripheral evaluation chip register 342 is input as a signal switching signal for the first peripheral evaluation chip clock selection circuit 340, and the data stored in the second peripheral evaluation chip register 343 is used for signal switching of the second peripheral evaluation clock selection circuit 341. Input as a signal.

  The outputs of the first peripheral evaluation clock selection circuit 340 and the second peripheral evaluation clock selection circuit 341 are input to the peripheral evaluation chip register clear circuit 345, and the output of the peripheral evaluation chip register clear circuit 345 is the output of the first peripheral evaluation chip register 345. It becomes a clear signal for the chip register 342. The outputs of the first peripheral evaluation clock selection circuit 340 and the second peripheral evaluation clock selection circuit 341 are connected to the input of the peripheral evaluation clock switching circuit 346.

  The output of the first peripheral evaluation chip register 342 is input to the peripheral evaluation clock switching signal generation circuit 344, and the output of the peripheral evaluation clock switching signal generation circuit 344 becomes the switching signal of the peripheral evaluation clock switching circuit 346. The output of the circuit 346 becomes the peripheral evaluation clock 402.

  FIG. 8 is a timing chart of clock switching in the skew adjustment block 311 of FIG. Here, an example is shown in which the CPU core clock 401 is switched from the output of the delay gate 322 to the output of the delay gate 324 at time T102. For example, when the operating voltage of the peripheral evaluation chip 313 is significantly lower than that of the CPU core 312, the CPU core 312 operates faster. Therefore, by adding a delay by the delay gate 322 to the operation clock of the CPU core 312, the peripheral evaluation chip The operation timing with 313 is matched. In this example, the voltage of the peripheral evaluation chip 313 is further lowered, and the operation of the CPU core 312 and the synchronization of the peripheral evaluation chip 313 are synchronized by switching to the delay gate 324 that has a large delay by the operation clock of the CPU core 312. is there.

  In response to the change in the skew adjustment value setting signal 403, the skew setting value separation circuit 350 and the skew setting value selection circuit 351 operate to supply the second CPU core register 333 with a skew setting value that is a CPU core clock switching signal. At time T100, the data stored in the second CPU core register 333 obtained from the skew adjustment value setting signal 403 is 0010H (delay signal 411 selection signal), and the delay signal 411 is selected. The output of the selection circuit 331 is the delayed signal 411.

  Since the data in the first CPU core register 332 is cleared by the CPU core register clear circuit 335, 0000H is output. The output from the first CPU core clock selection circuit 330 is the VDD when 0000H is selected, and the output signal 423 is Hi. Is output.

  Since the first CPU core register 332 is 0000H, the CPU core clock switching signal generation circuit 334 is Low, the second CPU core clock selection circuit 331 is selected, and the delay signal 411 is output to the CPU core clock 401.

  At time T101, the data in the second CPU core register 333 changes to 0101H (selection signal for the delay signal 413). 0010H (selection signal of the delay signal 411) that is data before the second CPU core register 333 is transferred to the first CPU core register 332. Therefore, the second CPU core clock selection circuit 331 outputs a delay signal 413, and the first CPU core clock selection circuit 330 outputs a delay signal 411.

  Since the first CPU core register 332 is not 0, the CPU core clock switching signal generation circuit 334 becomes Hi output, and the CPU core clock switching circuit 336 selects the output signal 423 of the first CPU core clock selection circuit 330 and outputs an output delay signal. 411 is output to the CPU core clock 401.

  At time T102, the delay signal 411 and the delay signal 413, which are the output signals of the first CPU core clock selection circuit 330 and the second CPU core clock selection circuit 331, are both at the same logic level at the low timing, and the CPU core register clear circuit 335 The output becomes Hi, and the data in the first CPU core register 332 is cleared. Therefore, the CPU core clock switching signal generation circuit 334 becomes Low, and the CPU core clock switching circuit 336 switches the output signal from the delay signal 411 to the delay signal 413, whereby the CPU core clock becomes the delay signal 413.

  As described above, here, the skew set value signal 403 changes at the time T101, but the CPU core clock 401 is switched at the time T102. In this way, the signals are switched at a timing such that the signals before and after the switching of the CPU core clock 401 are both in the low phase. That is, the clock signal 423 of the first CPU core clock selection circuit 330 is at the low level at the timing before time T102, and the clock signal 424 of the second CPU core clock selection circuit 331 is at the low level at the timing after time T102, and the time T102. Before and after, the clock signals 423 and 424 to be switched are both at the low level. Thus, regardless of the timing of the skew switching signal, the actual signal is switched in synchronization with the change timing of the signal before and after the change. it can.

  Next, FIG. 9 shows a timing chart when the clock is switched so that the delay enters the peripheral evaluation clock 402 side from the situation where the CPU core clock 401 side is delayed. In this example, the CPU core clock 401 is switched from the output of the first delay gate 322 to the through output without delay at the time T202, and the peripheral evaluation clock 402 is switched from the through output without delay at the time T203 to the output of the delay gate 323. Indicates.

  This is because, for example, the operating voltage of the peripheral evaluation chip 313 is lower than that of the CPU core 312, and the CPU core 312 operates faster. Therefore, the peripheral evaluation chip 313 is added by adding a delay to the operation clock of the CPU core 312 by the delay gate 322. When the operation timing of the peripheral core 313 rises from the voltage of the CPU core 312 from the state where the operation timing is synchronized with the CPU core 312, the operation clock of the CPU core 312 is not required to be delayed and switched to a through output without delay. For example, the operation clock of the peripheral evaluation chip 313 needs to be delayed, and the operation of the CPU core 312 and the operation of the peripheral evaluation chip 313 are matched by switching from the through output without delay to the delay gate 323.

  In response to a change in the skew adjustment value setting signal 403, the skew setting value separation circuit 350 and the skew setting value selection circuit 351 operate to supply the skew setting value that becomes the CPU core clock switching signal 421 to the second CPU core register 333, and A skew setting value corresponding to the evaluation clock switching signal 422 is given to the peripheral evaluation core register 343.

  At time T200, since the skew adjustment value setting signal 403 is the data of the second CPU core register 333 is 0010H (selection signal of the delay signal 411) and the delay signal 411 is selected, the second CPU core clock selection circuit A delay signal 411 is output from the output 331.

  Further, since the data of the second peripheral EVA core register 343 is 0001H (selection signal of the source clock 400) and the source clock 400 without delay is selected, the output of the second peripheral EVA clock selection circuit 341 is the source clock. 400 is output. Since the data of the first CPU core register 332 is cleared by the CPU core register clear circuit 335, 0000H is output, and the output of the first CPU core clock selection circuit 330 becomes VDD when 0000H is selected, and is output as the output signal 423 as Hi. ing.

  Since the first CPU core register 332 is 0000H, the CPU core clock switching signal generation circuit 334 becomes Low, the second CPU core clock selection circuit 331 is selected, and the delay signal 411 is output to the CPU core clock 401. Since the data of the first peripheral evaluation chip register 342 is cleared by the peripheral evaluation chip register clear circuit 345, 0000H is output, and the output of the first peripheral evaluation clock selection circuit 340 becomes VDD when 0000H is selected. Hi is output to the line 433.

  Since the first peripheral evaluation chip register 342 is 0000H, the peripheral evaluation clock switching signal generation circuit 344 becomes Low, the second peripheral evaluation clock circuit 341 is selected, and the source clock 400 without delay is output to the peripheral evaluation clock 402. Has been.

  At time T201, the data in the second CPU core register 333 changes to 0001H (selection signal for the source clock 400). 0010H (selection signal of the delay signal 411) that is data before the second CPU core register 333 is transferred to the first CPU core register 332. Therefore, the second CPU core clock selection circuit 331 outputs the source clock 400 without delay, and the first CPU core clock selection circuit 330 outputs the delay signal 411. The CPU core clock switching signal generation circuit 334 becomes Hi output because the first CPU core register 332 is not 0, the CPU core clock switching circuit 336 selects the output signal 423 of the first CPU core clock selection circuit 330, and the delay signal 411 is the CPU. It is output as the core clock 401.

  Next, at time T201, the data in the second peripheral evaluation chip register 343 changes to 0011H (selection signal for the delay signal 412). 0001H (selection signal of the source clock 400), which is data before the second peripheral evaluation chip register 343, is transferred to the first peripheral evaluation chip register 342. Therefore, the second peripheral evaluation clock selection circuit 341 outputs a delay signal 412 and the first peripheral evaluation clock selection circuit 340 outputs a source clock 400 without delay.

  The peripheral evaluation clock switching signal generation circuit 344 becomes Hi output because the first peripheral evaluation chip register 342 is not 0, and the peripheral evaluation clock switching circuit 346 selects the line of the output signal 433 of the first peripheral evaluation clock selection circuit 340, The source clock 400 without delay is output as the peripheral evaluation clock 402.

  At time T202, the delay signal 411 and the source clock 400, which are output signals of the first CPU core clock selection circuit 331 and the second CPU core clock selection circuit 331, are both low, and the output of the CPU core register clear circuit 335 is output. It becomes Hi and the data in the first CPU core register 332 is cleared. Therefore, the CPU core clock switching signal generation circuit 334 becomes Low, and the CPU core clock switching circuit 336 switches the output signal from the delay signal 411 to the source clock 400 without delay, so that the CPU core clock becomes the source clock 400.

  At time T203, the peripheral evaluation chip register clear circuit 345 is output at the timing when both the delay signal 412 and the source clock 400, which are output signals of the first peripheral evaluation clock selection circuit 340 and the second peripheral evaluation clock selection circuit 341, are Low. Becomes Hi and the data in the first peripheral evaluation chip register 342 is cleared. Therefore, the peripheral ever clock switching signal generation circuit 344 becomes Low, and the peripheral ever clock switching circuit 346 switches the output signal from the non-delayed source clock 400 to the delayed signal 412, so that the peripheral ever clock becomes the delayed signal 412.

  As described above, here, the skew set value signal 403 changes at the timing of the time T201. However, the switching of the signal of the CPU core clock 401 is performed according to the low phase timing T202 in which the signals before and after the switching are both at the same logic level. To change. That is, since the CPU core clock 401 selects the output 411 of the delay gate 322 until time T202 and selects the source clock 400 at time T202, both are low before and after time T202. Similarly, the peripheral evaluation clock 402 switches the signal at time T203, but changes the signal at the low phase timing (T203) in which the signals before and after the switching are both at the same logic level. That is, until the time T202, the source clock 400 is selected, and the output 412 of the delay gate 323 is selected at the timing of T202, so that the peripheral evaluation clock 402 becomes the Low level before and after the timing of T202. As a result, regardless of the timing of the skew switch signal, the actual signal is switched in synchronism with the signal change timing before and after the change, so that the generation of whiskers in the operation clock can be prevented and malfunction can be prevented. Can do.

  Previously, the adjustment value was obtained by comparing the clock phase, so when the voltage fluctuation range was wide at high frequencies, the delay could not be set to an appropriate amount if the delay exceeded the clock cycle. In this embodiment, skew adjustment values for optimal movement of the CPU evaluation chip 318 and the peripheral evaluation chip 313 are held in a table for each operating voltage in advance, so that even a delay of a clock period or more can be adjusted. For this reason, even in a system in which the operating frequency fluctuates, a clock skew of one cycle or more can be detected and set. Therefore, the timings of data input and output between the peripheral evaluation chip 313 and the CPU evaluation chip 318 are the same, and no malfunction occurs.

  Further, in this embodiment, the operation is performed by incorporating the actual timing skew for each set voltage, so that there is no delay adjustment error on the substrate due to the difference in the clock path on the substrate unlike the conventional case. Therefore, a system that does not cause a malfunction can be constructed.

Embodiment 2. FIG.
Next, a second embodiment of the present invention will be described. The user voltage measurement block 315 of the first embodiment can also be realized by the AD function (AD converter 361) of the microcomputer (MCU) 360. FIG. 10 is a block diagram showing an emulator according to this embodiment. The emulator 310 has an MCU 360, and the table block 314 uses the MCU 360 ROM. The MCU 360 can use a main board mounted on the emulator 310 and a microcomputer for controlling the I / F of the host machine. The present embodiment is effective when the MCU 360 has an extra AD function.

  In this case, a skew adjustment table is written in the microcomputer table block (ROM) 314, and the AD converter 361 monitors the user voltage. Based on the skew setting value from the table, the skew adjusting block 311 adjusts the operation clocks of the peripheral evaluation chip 313 and the CPU core 312.

  In the program of the MCU 360, the function of AD converting the operating voltage is always operated, and the AD conversion end interrupt is periodically sent to the table block 314, and the address is set to the voltage range A (3.0V-2). .0V) and the address corresponding to the voltage range B (5.5V or more) are set to address 0000H in the table block.

  In the present embodiment, the same effect as in the first embodiment is obtained. The voltage measurement block and the table block in the first embodiment are realized by the remaining ROM, AD converter, Port, or external expansion function in the emulator 310 and the MCU 360 for controlling the I / F of the host machine, thereby reducing costs. be able to.

  Furthermore, the configuration on the substrate is simplified. Furthermore, when the MCU 360 is mounted and its AD function is surplus, the emulator according to the present embodiment can be realized without adding new resources. For example, if there is a microcomputer that controls communication between the emulator 310 and the host machine 1 as shown in the overall configuration diagram of FIG. 1 and the function of the microcomputer is excessive, the MCU 360 required in the second embodiment is also used. Therefore, it is not necessary to install a new microcomputer, leading to cost reduction.

Embodiment 3 FIG.
Next, a third embodiment of the present invention will be described. In the present embodiment, the voltage measurement block in the first embodiment is realized by providing a comparator (analog IC). FIG. 11 is a block diagram of an emulator according to the third embodiment. The user voltage measurement block 315 in the first embodiment may be replaced with the comparator unit 363 in FIG. FIG. 12 shows details of the comparator unit 363. Comparators 501 to 504 are provided for each reference voltage value for switching the skew adjustment, and a user voltage is input to each of the comparators 501 to 504 as an expected value and a user voltage as a comparison target voltage. Then, the outputs of the comparators 501 to 504 are connected to the decoder 505.

  The decoder 505 decodes the output result of “High” or “LOW”, which is output by comparing each of the comparators 501 to 504 with the reference voltage and the user voltage to be compared. The operations after the decoder 505 are the same as in the first embodiment, and by selecting the skew adjustment value from the skew adjustment table obtained in advance and stored in the table block 314 by the address output from the comparator unit 363. , It can be operated with a skew suitable for the voltage of the user.

  Also in this embodiment, the same effects as those of the first embodiment are obtained. Furthermore, by using the comparator unit 363, the speed of voltage detection is increased, and settings that follow the real time by the user's operation can be performed. Further, since the conversion speed of the comparator unit 363 is 0.3 μs to 1 μs with respect to the AD conversion speed min6 μS of the microcomputer, the comparator unit 363 can react faster due to voltage fluctuation.

  As described above, the CPU evaluation chip 318 operates at a constant voltage, and the operation voltage of the peripheral evaluation chip 313 varies, and the program of each chip is executed by the clock whose clock skew is adjusted for each chip. And there are the following advantages over the emulator that inputs and outputs data between chips.

  That is, first, since skew can be adjusted in a wide voltage range with one product, it is not necessary to provide an emulator for each user voltage range, and a single emulator can handle a wide voltage range. .

  Second, since the optimum skew adjustment value according to the operating voltage can be automatically set, the user can use the optimum skew without being aware of the use environment.

  Third, even when skew deviation of one cycle or more occurs due to voltage fluctuation, skew adjustment can be performed correctly.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

1 is a diagram illustrating an entire system of an in-circuit emulator according to a first exemplary embodiment of the present invention. 3 is a block diagram showing functions of an emulator 310 according to the first embodiment of the present invention. It is a figure which shows the general circuit structure from a user voltage measurement block to outputting an address from a decoder. It is a flowchart which shows the preparation method of the skew adjustment table concerning Embodiment 1 of this invention. (a) And (b) shows the example of a result when the skew adjustment value by an individual difference varies. It is a figure which shows the example of the table stored in the table block concerning Embodiment 1 of this invention. It is a block diagram which shows the detail of the block for skew adjustment concerning Embodiment 1 of this invention. 8 is a timing chart of clock switching in the skew adjustment block of FIG. It is a figure which shows the timing chart at the time of switching a clock so that a delay may enter into the peripheral evaluation clock side from the situation where the CPU core clock side is delayed. It is a block diagram which shows the emulator concerning Embodiment 2 of this invention. It is a block diagram which shows the emulator concerning Embodiment 3 of this invention. It is a figure which shows the detail of the comparator part concerning Embodiment 3 of this invention. (A) is the emulation circuit of patent document 1, (b) is a timing chart which shows operation | movement of the emulation circuit shown to (a). It is a figure explaining the problem of patent document 1. FIG.

Explanation of symbols

2 Host control MCU
3 Emulation memory 4 Level shifter 5 User target board 6 Target I / F
310 emulator 311 skew adjustment block 312 evaluation chip 312 CPU core 313 peripheral evaluation chip 314 table block 315 user voltage measurement block 316 user power supply voltage supply unit 317 clock generator 318 CPU evaluation chip 320 buses 321 to 324 delay gate 330 first CPU core clock selection circuit 331 Second CPU core clock selection circuit 332 First CPU core register 333 Second CPU core register 334 CPU core clock switching signal generation circuit 335 CPU core register clear circuit 336 CPU core clock switching circuit 336 Core chip clock switching circuit 340 Peripheral evaluation clock selection circuit 340 First Peripheral evaluation clock selection circuit 341 Second peripheral evaluation clock selection circuit 342 First peripheral evaluation chip register 343 Second peripheral evaluation chip register 344 Peripheral evaluation clock switching signal generation circuit 345 Peripheral evaluation chip register clear circuit 346 Peripheral evaluation clock switching circuit 350 Skew setting value separation circuit 351 Skew setting value selection circuit 361 AD converter 362 Decoder 363 Comparator section 400 Source clock 401 CPU core clock 402 Peripheral evaluation clock 402 Peripheral evaluation clock 403 Skew adjustment value setting signal 404 Address output 405 User voltage 410-413 Delay signal 410-413 Delay gate 421 CPU core clock switching signal 422 Peripheral evaluation clock switching signal 423 output Signals 501 to 504 Comparator 505 Decoder 511 to 514 Comparison circuit

Claims (10)

An emulator that realizes the operation of the microcomputer including a CPU core part that realizes a CPU function of the microcomputer and a peripheral part that realizes peripheral functions,
A skew adjustment unit that inputs a source clock output from a clock generator and generates a first operation clock supplied to the CPU core unit and a second operation clock supplied to the peripheral unit;
A setting value table that stores a setting value that is obtained according to a user voltage supplied to the peripheral portion and that determines a delay amount to be added to the first or second operation clock;
The skew adjustment unit is an emulator for adjusting a skew between the first operation clock and the second operation clock based on the set value. The skew adjustment unit switches and selects the source clock and a plurality of delay clocks having different delay amounts to generate the first and second operation clocks, and the clocks before and after the switching have the same logic level. The emulator according to claim 1, wherein the source clock or the delay clock is selected at timing. A user voltage measurement unit,
The emulator according to claim 1, wherein the skew adjustment unit selects the setting value of the setting value table based on a measurement result of the user voltage measurement unit. The emulator according to claim 3, wherein the user voltage measuring unit is an AD converter that performs analog-digital conversion on a user voltage. The emulator according to claim 3, wherein the user voltage measurement unit is a comparator that compares a plurality of reference voltage values with the user voltage, and measures a voltage range of the user voltage. The emulator according to any one of claims 1 to 5, wherein the setting value table is a table including a user voltage range and a setting value for the user voltage range. The set value table is obtained by determining whether or not the CPU core unit and the peripheral unit operate normally by changing the delay value at an arbitrary voltage and operating the same. The emulator according to any one of claims 1 to 6. The emulator according to claim 7, wherein the set value is a value having the largest margin among the delay values in the normal operating range. The emulator according to any one of claims 1 to 8, wherein the CPU core unit and the peripheral unit are formed of different chips. A CPU core unit for realizing a CPU function of a microcomputer and a peripheral unit for realizing a peripheral function, and a first operation clock which is obtained in advance according to a user voltage supplied to the peripheral unit and is supplied to the CPU core unit or An emulation method for emulating the operation of the microcomputer by a setting value table storing a setting value for determining a delay amount added to a second operation clock supplied to the peripheral portion,
Measuring the user voltage;
Based on the measured result, a predetermined set value is selected from the set value table,
An emulation method for adjusting a skew between the first operation clock and the second operation clock based on the selected predetermined setting value.

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