JPH0590956A - Phase synchronizing oscillator - Google Patents

Abstract

PURPOSE:To generate a stable output clock without undesired phase fluctuation with less effect onto the output clock even when an inputted clock is subject to disturbance. CONSTITUTION:This oscillator consists of a voltage control oscillator 40, a 1st phase comparator 10 generating a voltage in response to a phase difference between an inputted high speed clock signal and a clock signal of the voltage control oscillator 40, a frequency divider 50 converting the generated clock signal into a low speed clock signal with a frequency equal to that of the low speed clock signal, a pulse width conversion circuit 60 changing the pulse width being an output of the frequency divider 50 by a half period of the high speed clock signal, a 2nd phase comparator 20 generating a binary signal in response to the phase difference between the output signal of the pulse width conversion circuit 60 and the low speed clock signal, an integration device 21 integrating the output signal of the 2nd phase comparator 20 and generating an average voltage, and a voltage adder 30 adding the voltage of the integration device 21 and an output of the 1st phase comparator 10 and generating a control voltage of the voltage controlled oscillator 40.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked oscillator frequently used in a device for processing multiplexed digital signals, and in particular, to a high-speed clock signal and a low-speed clock signal phase-locked to this signal, The present invention relates to a phase-locked oscillator that generates a high-speed clock signal synchronized with an input high-speed clock and a low-speed clock signal having a predetermined phase relationship with the input low-speed clock signal.

[0002]

2. Description of the Related Art A multiplexed digital signal usually has a frame structure. Therefore, in a multiplex converter that processes such a signal, a high-speed clock signal for identifying individual pulses of the multiplexed signal inside the device and a low-speed clock signal for processing the multiplexed signal in frame units. Is required.

Further, in order to efficiently perform signal processing between connected devices, input / output signals of the multiplex conversion device or the like need not be exactly equal in frequency.
The frame phase also needs to be a predetermined phase. For this reason, the station is equipped with a clock supply device that supplies a station reference clock for defining the reference frequency and frame phase. The frequencies and phases of various clocks required are determined.

Generally, the station reference clock is a composite signal in which a low-speed clock signal that defines the reference frame phase is superimposed on a high-speed clock signal, and a multiplexer or the like inputs this composite signal and internally outputs the high-speed clock signal. And a low-speed clock signal, and then converted into various clock signals required internally by a phase-locked oscillator.

FIG. 6 shows a first conventional example. The conventional example shown in FIG. 6 has a first input terminal 1 for inputting a high-speed clock signal.
00 and the second input terminal 1 for inputting the low-speed clock signal
01, and a phase comparator 10 that compares the phases of the high-speed clock signal input from the first input terminal 100 and the high-speed clock signal generated by the voltage controlled oscillator 40 to generate a voltage according to the phase difference between the two signals. The voltage control oscillator 40, which uses the voltage generated by the phase comparator 10 as a control voltage to generate a high-speed clock signal based on the control voltage, and the high-speed clock signal generated by the voltage-controlled oscillator 40 are frequency-divided and the second input terminal 10 is divided.
1, a frequency divider circuit 51 that generates a predetermined low-speed clock signal in phase synchronization with the low-speed clock signal input thereto, a first output terminal 200 that outputs the high-speed clock signal generated by the voltage-controlled oscillator 40, and a divider circuit. It has a second output terminal 201 for outputting the low-speed clock signal generated by the frequency circuit 51.

Next, the operation of the first conventional example will be described.

When the high speed clock signal is input from the first input terminal 100, the phase comparator 10 compares the phase of the high speed clock signal with the phase of the high speed clock signal generated by the voltage controlled oscillator 40, and finds the phase difference. The corresponding voltage is output. The voltage-controlled oscillator 40 generates a high-speed clock signal such that the phase difference becomes 0 based on the control voltage from the phase comparator 10. The frequency divider circuit 51 frequency-divides the high-speed clock signal generated by the voltage controlled oscillator 40 so as to be phase-synchronized with the low-speed clock signal input from the second input terminal 101, and outputs it as a low-speed clock signal.

FIG. 7 shows a second conventional example. The conventional example of FIG. 7 has a second input terminal 101 for inputting a low-speed clock signal.
And a phase comparator that compares the phase of the low-speed clock signal input from the second input terminal 101 with the phase of the low-speed clock signal generated by the frequency divider circuit 50 and generates two different logic levels according to the phase relationship between the two signals. 20, an integrator 21 that integrates the output signal of the phase comparator 20 to generate a control voltage of the voltage controlled oscillator 40, and a voltage that generates a high-speed clock signal based on the voltage generated by the integrator 21 as a control voltage. A controlled oscillator 40, a frequency divider circuit 50 for converting an output signal of the voltage controlled oscillator 40 into a low speed clock signal having a frequency equal to the input low speed clock signal, and a high speed clock signal generated by the voltage controlled oscillator 40. It has a first output terminal 200 for outputting and a second output terminal 201 for outputting the low-speed clock signal generated by the frequency dividing circuit 51.

Next, the operation of the second conventional example will be described.

When the low-speed clock signal is input from the second input terminal 101, the phase comparator 20 compares the phase of the low-speed clock signal with the phase of the low-speed clock signal generated by the frequency dividing circuit 50, and compares them. One of two different logic levels "1" and "-1" is generated depending on the phase difference.
The integrator 21 integrates the output signal of the phase comparator 20 and outputs an average voltage. In the voltage controlled oscillator 40, when the output voltage of the integrator 21 is used as a control voltage, a signal of maximum frequency when "1" and a minimum frequency when "-1" are output as a high-speed clock signal. In the frequency dividing circuit 50, the high speed clock signal from the voltage controlled oscillator 40 is divided and output as a low speed clock signal having the same frequency as the input low speed clock signal.

That is, in the phase locked oscillator according to the second conventional example, only the low speed clock signal is input, and the low speed clock signal and the high speed clock signal which are phase-locked with the low speed clock signal are generated.

[0012]

However, in the first conventional example described above, since the low-speed clock signal is generated outside the phase-locked loop, when a disturbance occurs in the low-speed clock signal input from the outside, There is an inconvenience that the low-speed clock signal output immediately has a great influence. That is, when the input high-speed clock signal is disturbed, the influence on the output clock signal can be reduced by appropriately setting the characteristics of the phase-locked oscillator, but when the input low-speed clock signal is disturbed. However, even if the disturbance is instantaneous, the output phase of the divider circuit is immediately controlled, so the phase of the low-speed clock signal that is output instantly fluctuates, and this clock signal is used. However, there is an inconvenience of causing a serious malfunction in the existing multi-conversion device.

Further, in the second conventional example, the high speed clock signal is not directly input, but only the low speed clock signal is used as the phase comparison input, so that the above problem is solved. However, it is necessary to minimize the stationary phase error in order to ensure individual pulse identification of the multiplexed signal,
Therefore, the phase comparison characteristics of the phase comparator are made extremely sensitive,
It was necessary to use a special phase-locked oscillator equipped with a perfect integration element as a loop filter. However, since the DC loop gain of such a special phase-locked oscillator is infinite, the steady-state characteristics are unstable, and it is not possible to suppress unnecessary phase fluctuations, that is, jitter included in the input clock. There was a drawback that jitter was generated by myself.

[0014]

SUMMARY OF THE INVENTION The object of the present invention is to improve the inconvenience of the conventional example, and in particular, to input a high-speed clock signal and a low-speed clock signal synchronized with this high-speed clock signal from the outside, and to phase the two types of clock signals. In a phase-locked oscillator that generates synchronized high-speed clock signal and low-speed clock signal, even if there is a disturbance in the clock input from the outside, there is little effect on the output clock and a stable output clock with no unnecessary phase fluctuation is generated. It is to provide a phase-locked oscillator capable of performing.

[0015]

Therefore, according to the present invention, a first input terminal for inputting a high-speed clock signal having a cycle t,
The second input terminal for inputting the low-speed clock signal of cycle T is compared with the phase of the high-speed clock signal input from the first input terminal and the high-speed clock signal generated by the voltage-controlled oscillator, and the phase difference between the two signals is detected. The first phase comparator for generating the voltage, the low-speed clock signal generated by the frequency dividing circuit and the high-speed clock signal generated by the voltage controlled oscillator are input, and the position of one change point of the pulse of the low-speed clock signal is set to "t". / 2 "
Pulse width to be changed to a signal in which a pulse whose pulse width is ("T / 2"-"t / 2") and a pulse whose pulse width is ("T / 2" + "t / 2") are alternately arranged A conversion circuit,
A second phase comparator that compares the phase of the output signal of the pulse width conversion circuit with the low-speed clock signal input from the second input terminal and generates two different logic levels according to the phase relationship between the two signals; An integrator that integrates the output signals of the second phase comparator to generate an average voltage of the output logic level;
The voltage adder that adds the output voltage of the phase comparator and the output voltage of the integrator to generate the control voltage of the voltage controlled oscillator, and the voltage generated by this voltage adder is used as the control voltage to generate a high-speed clock signal based on it. A voltage controlled oscillator, a frequency divider circuit for dividing a high speed clock signal generated by the voltage controlled oscillator to generate a predetermined low speed clock signal, and a first output for outputting the high speed clock signal generated by the voltage controlled oscillator It has a configuration including a terminal and a second output terminal for outputting a low-speed clock signal generated by the frequency dividing circuit. This aims to achieve the above-mentioned object.

[0016]

A high-speed clock signal with a cycle t and a low-speed clock signal with a cycle T are input from the outside.

(1) The phase difference between the output signal of the pulse width conversion circuit and the low-speed clock signal input from the outside is "t / 2".
Above or below or below "-t / 2":

The output signal of the pulse width conversion circuit has its falling change point changed by "t / 2" in comparison with the low speed clock signal from the frequency divider circuit in the cycle 2T, so that the output signal of the pulse width conversion circuit is changed. When the phase difference between the low-speed clock signal input from the and the outside is "t / 2" or more or "-t / 2" or less, the output of the second phase comparator always outputs the logic level "1" or " −1 ”is output, and the output voltage of the integrator 21 is also“ 1 ”or“ −1 ”. Therefore, the control voltage generated from the voltage adder becomes "1" or "-1" regardless of the output voltage of the first phase comparator. When the voltage output from the integrator is "1" and the maximum frequency is "-1", the voltage controlled oscillator uses the minimum frequency signal as the high-speed clock signal in phase synchronization with the input high-speed clock signal. Occur. The frequency dividing circuit divides the high speed clock signal output from the voltage controlled oscillator and outputs a low speed clock signal having a predetermined phase relationship with the input low speed clock signal.

(2) The phase difference between the output signal of the pulse width conversion circuit and the low-speed clock signal input from the outside is "t / 2".
Below or above "-t / 2":

The first phase comparator generates a voltage corresponding to the phase difference between the two high speed clock signals, the high speed clock signal from the outside and the high speed clock signal generated by the voltage controlled oscillator. The output signal of the pulse width conversion circuit changes its falling point by “t / 2” in the cycle 2T compared to the low-speed clock signal from the frequency divider circuit, so the output signal of the pulse width conversion circuit and the outside When the phase difference of the input low-speed clock signals is "t / 2" or less or "-t / 2" or more, the output signal of the second phase comparator has a logic level "1" every period 2T. The level "-1" is output.
At this time, the output voltage of the integrator 21 becomes zero. And
As long as the phase difference between the output signal of the pulse width conversion circuit input to the second phase comparator and the low-speed clock signal input from the outside is “t / 2” or less or “−t / 2” or more, the second The output signal of the phase comparator is a rectangular wave having a period of 2T, and even if the phase difference between the two signals changes within this range, the output voltage 0 of the integrator does not change. At this time, the control voltage output from the voltage adder is equal to the voltage output from the first phase comparator. Therefore, the voltage controlled oscillator uses the voltage output from the first phase comparator as a control voltage to generate a high speed clock signal phase-locked with the input high speed clock signal. Further, the frequency divider circuit divides the high speed clock signal output from the voltage controlled oscillator and outputs a low speed clock signal having a predetermined phase relationship with the input low speed clock signal.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIGS.

In the embodiment shown in FIG. 1, a first input terminal 100 for inputting a high speed clock signal f100 having a cycle t and a second input terminal 10 for receiving a low speed clock signal f101 having a cycle T.
1 and the phase of the high speed clock signal f100 input from the first input terminal 100 and the high speed clock signal f200 generated by the voltage controlled oscillator 40 described later are compared to generate a voltage according to the phase difference between the two signals. The phase comparator 10 and the low-speed clock signal generated by the frequency dividing circuit 50 and the high-speed clock signal generated by the voltage controlled oscillator 40 are input, and the position of one change point of the pulse of the low-speed clock signal is set to "t / 2" only. Pulse width conversion that changes the pulse width to a signal in which the pulse width becomes ("T / 2"-"t / 2") and the pulse width becomes "(T / 2" + "t / 2"). The circuit 60, the phase of the output signal f60 of the pulse width conversion circuit 60, and the low-speed clock signal f101 input from the second input terminal 101.
And a second phase comparator 20 that generates two different logic levels according to the phase relationship of both signals, and the output signal f20 of the second phase comparator 20 are integrated to obtain the average voltage of the output logic level. Generated integrator 21 and first phase comparator 10
Output voltage of the integrator 21 and the output voltage of the integrator 21 to generate a control voltage of the voltage controlled oscillator 40, and a voltage generated by the voltage adder 30 is used as a control voltage to generate a high-speed clock signal based on the voltage. Voltage controlled oscillator 40
And a frequency dividing circuit 50 for dividing the high speed clock signal generated by the voltage controlled oscillator 40 to generate a predetermined low speed clock signal.
A first output terminal 200 for outputting a high speed clock signal generated by the voltage controlled oscillator 40, and a second output terminal 201 for outputting a low speed clock signal generated by the frequency dividing circuit 50. There is.

Here, as shown in the phase comparison characteristic diagram of FIG. 2, the first phase comparator 10 has a first input terminal 100.
When the difference between the phase of the high-speed clock signal f100 input from and the phase of the high-speed clock signal f200 generated by the voltage controlled oscillator 40 is "t / 2", the maximum value "1" is set to "-t / 2".
In this case, the minimum value "-1" is output, and the phase difference and the output are in a linear relationship. That is, when the phase difference is between "t / 2" and "-t / 2", the output is "1" and "-1".
Takes a value between.

As shown in the phase comparison characteristic diagram of FIG. 3, the second phase comparator 20 has a phase of the output signal f60 of the pulse width conversion circuit 60 and a low-speed clock input from the second input terminal 101. The phase difference of the signal f101 is "0" and "T".
When it is between "/ 2", "1" is output, and when the phase difference is between "-T / 2" and "0", "-1" is output.

In this embodiment, the voltage controlled oscillator 40
Is the maximum frequency when the applied control voltage is "1",
When the minimum frequency is 1 ”, the voltage adder 3
0 is the maximum output voltage "1" regardless of the input voltage
In addition, the minimum output voltage is limited to "-1".

Next, the operation of this embodiment will be described with reference to FIG.

A high-speed clock signal f100 having a cycle t from the first input terminal 100 and a cycle T from the second input terminal 101.
The low speed clock signal f101 is input.

(1) Output signal f of pulse width conversion circuit 60
When the phase difference between 60 and the low-speed clock signal f101 input from the second input terminal 101 is “t / 2” or more:

As shown in FIG. 4, the pulse width conversion circuit 6
The output signal f60 of 0 changes its trailing edge changing point by "t / 2" in the cycle 2T, so the pulse width conversion circuit 6
When the phase difference between the output signal f60 of 0 and the low-speed clock signal f101 input from the second input terminal 101 is “t / 2” or more, the second phase comparator 20 always outputs the logic level “1”. Is output.

In this state, the output voltage of the integrator 21 also becomes "1".

The first phase comparator 10 has two high speed clock signals, a high speed clock signal f100 input from the first input terminal 100 and a high speed clock signal f200 generated by the voltage controlled oscillator 40. The voltage is generated according to the phase difference of the.

However, since the output voltage of the integrator 21 is "1", the control voltage generated from the voltage adder 30 is "1" regardless of the output voltage of the first phase comparator 10. ..

Since the voltage controlled oscillator 40 uses the voltage output from the integrator 21, that is, "1" as the control voltage, it generates a high-frequency clock signal f200 having a maximum frequency in phase with the input high-speed clock signal. ..

The frequency divider circuit 50 divides the high speed clock signal f200 output from the voltage controlled oscillator 40 and outputs it as a low speed clock signal f201 having a predetermined phase relationship with the input low speed clock signal f101.

(2) Output signal f of pulse width conversion circuit 60
When the phase difference between 60 and the low-speed clock signal f101 input from the second input terminal 101 is "-t / 2" or less:

As shown in FIG. 4, the pulse width conversion circuit 6
The output signal f60 of 0 changes its trailing edge changing point by "t / 2" in the cycle 2T, so the pulse width conversion circuit 6
When the phase difference between the output signal f60 of 0 and the low-speed clock signal f101 input from the second input terminal 101 is equal to or less than "-t / 2", the second phase comparator 20 always outputs the logic level "-t". 1 ”is output.

In this state, the output voltage of the integrator 21 is also "-
1 ”.

The first phase comparator 10 has two high-speed clock signals, a high-speed clock signal f100 from the first input terminal 100 and a high-speed clock signal f200 generated by the voltage controlled oscillator 40, which are input to the phase comparator. The voltage is generated according to the phase difference of the.

However, the output voltage of the integrator 21 is "-1".
Therefore, the control voltage generated by the voltage adder 30 does not depend on the output voltage of the first phase comparator 10 and is “−”.
1 ”.

Since the voltage controlled oscillator 40 uses the voltage output from the integrator 21, that is, "-1" as the control voltage,
A signal having the minimum frequency that is phase-locked with the input high speed clock signal is generated as the high speed clock signal f200.

The frequency divider circuit 50 divides the high speed clock signal f200 output from the voltage controlled oscillator 40 and outputs it as a low speed clock signal f201 having a predetermined phase relationship with the input low speed clock signal f101.

(3) Output signal f of pulse width conversion circuit 60
The phase difference between 60 and the low-speed clock signal f101 input from the second input terminal 101 is "t / 2" or less or "-t /".
If 2 or more:

In the first phase comparator 10, a voltage corresponding to the phase difference between the high speed clock signal f100 from the first input terminal 100 and the high speed clock signal f200 generated by the voltage controlled oscillator 40 is generated. Is generated.

Since the falling change point of the output signal f60 of the pulse width conversion circuit 60 changes by "t / 2" in the cycle 2T, the pulse width conversion circuit 6 as shown in FIG.
If the phase difference between the output signal f60 of 0 and the low-speed clock signal f101 input from the second input terminal 101 is "t / 2" or less or "-t / 2" or more, the second phase comparator 2
The output signal f20 of 0 outputs a logic level "1" and a logic level "-1" every cycle 2T.

Since the time constant of the integrator 21 is sufficiently large, the output voltage of the integrator 21 becomes zero. And the second
The phase difference between the output signal f60 of the pulse width conversion circuit 60 input to the phase comparator 20 and the low-speed clock signal f101 input from the second input terminal 101 is "t / 2" or less or "-t / 2". As far as the above, the output signal of the second phase comparator 20 is a rectangular wave with a period of 2T, and the output voltage 0 of the integrator 21 does not change even if the phase difference between the two signals changes within this range. ..

At this time, the control voltage output from the voltage adder 30 is equal to the voltage output from the first phase comparator 10.

Therefore, the voltage controlled oscillator 40 generates a signal which is phase-synchronized with the input high speed clock signal as the high speed clock signal f200 using the voltage output from the first phase comparator 10 as the control voltage.

Further, the frequency dividing circuit 50 is a voltage controlled oscillator 40.
The high-speed clock signal f200 output from is divided and output as a low-speed clock signal f201 having a predetermined phase relationship with the input low-speed clock signal f101.

That is, in the phase comparison characteristic of the control voltage generated from the voltage adder 30 of the present embodiment, the phase difference between the input and output clock signals is within "± t / 2" as shown in FIG. In this case, the control voltage is equal to the phase comparison characteristic of the first phase comparator 10 shown in FIG. 2, and when the phase difference is “t / 2”, the control voltage having the maximum value “1” and the phase difference “−t / The control voltage with the minimum value "-1" is output when "2", and the phase difference and the control voltage have a linear relationship. However, when the phase difference of the input / output clock signal is "t / 2" or more, the phase difference is different. When the maximum control voltage "1" of the voltage controlled oscillator 40 is "-t / 2" or less, the minimum control voltage "-1" is output.

Therefore, when a reference clock signal of an arbitrary phase is input, first the phase of the low speed clock signal input by the second phase comparator 20 and the phase of the low speed clock signal output by the voltage controlled oscillator 40 are compared. The frequency of the voltage controlled oscillator 40 is controlled so that the phase difference between the two clock signals is within "± t / 2". Next, when the phase difference between the input and output clock signals is within "± t / 2", the second phase comparator 20 becomes invalid, but instead the first phase comparator 10
Generates a control voltage so that the phase difference between the input and output clock signals becomes 0, and there is a predetermined phase relationship between the input high speed clock signal and the input low speed clock signal. A slow clock signal is generated.

[0051]

Since the present invention is constructed and functions as described above, according to this, even when a disturbance occurs in the input signal because both input signals are applied to the phase locked loop input, the output signal is not affected. The effect can be reduced, and since the phase control is effectively applied by the high-speed clock signal when the phase synchronization is established, it is necessary to use the perfect integrating element for the extremely sensitive phase comparator and loop filter. In addition, it is possible to provide an unprecedented excellent phase-locked oscillator that can generate a stable clock signal without unnecessary phase fluctuation.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a phase comparison characteristic diagram of the first phase comparator of FIG.

FIG. 3 is a phase comparison characteristic diagram of the second phase comparator of FIG.

FIG. 4 is a waveform diagram showing the operation of each unit in FIG.

5 is a phase comparison characteristic diagram of the voltage adder of FIG. 1. FIG.

FIG. 6 is a block diagram showing a first conventional example.

FIG. 7 is a block diagram showing a second conventional example.

[Explanation of symbols]

 10 first phase comparator 20 second phase comparator 21 integrator 30 voltage adder 40 voltage controlled oscillator 50 frequency dividing circuit 60 pulse width conversion circuit 100 first input terminal 101 second input terminal 200 first Output terminal 201 Second output terminal

Claims (1)

[Claims] 1. A phase-locked oscillator for externally inputting a high-speed clock signal and a low-speed clock signal synchronized with the high-speed clock signal, and generating a high-speed clock signal and a low-speed clock signal phase-synchronized with these two types of clock signals. , A voltage-controlled oscillator that generates a clock signal having a frequency corresponding to a given control voltage is compared with the input high-speed clock signal and the phase of the clock signal generated by the voltage-controlled oscillator, and the phase difference between them is determined. A first phase comparator that generates a voltage, a frequency divider that converts the generated clock signal into a low-speed clock signal having a frequency equal to the input low-speed clock signal, and a pulse width of an output signal of the frequency divider A pulse width conversion circuit that changes a half cycle of the high-speed clock signal input at a predetermined cycle, and this pulse width A second phase comparator for comparing the phase of the output signal of the conversion circuit and the phase of the input low-speed clock signal and generating a binary signal according to the phase difference between the second phase comparator and the output signal of the second phase comparator. A phase characterized by having an integrator for integrating and generating an average voltage, and a voltage adder for adding an output voltage of the integrator and an output signal of the first phase comparator to generate a control voltage of the voltage controlled oscillator. Synchronous oscillator.