JPH05265415A - Image display control circuit - Google Patents

Abstract

PURPOSE:To provide the image display control circuit which normally reads data out with relatively simple constitution even when data of one line of a display device require rows of plural memory cell arrays. CONSTITUTION:The image display control circuit is equipped with a memory 1, an address generating circuit 3 which generates read addresses, a data converting circuit 5 which converts read information, and a control means 7 which controls the read of the memory l; and the memory 1 consists of plural memory cell arrays 1-1 1-L and cyclically stored with blocks each consisting of plural words of the display data, block by block, from an optional memory cell array, and the control means 7 performs control so that when data of respective display lines are read out, a block containing starting data of a line and following L-1 blocks are read out at the same time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display control circuit for outputting image data to an information display device, and more particularly, when one line of data in a display device is spread over a plurality of memory cell array rows. The present invention relates to an image display control circuit that can normally read data with a simple configuration.

As the information display device, for example, a computer terminal, a television, or a monitor such as a teletext can be cited. With the recent improvement in the performance of information equipment, the information display device can be rewritten at high speed. Required functions and functions such as displaying a lot of information. In response to this request, there is provided a dual port memory that can rewrite the memory contents and read the memory for display almost independently. The cells of this memory are 256 x 2
It has a matrix structure of 56 or 512 × 512, and when it is used in a general information display device having a display screen of 640 × 400 dots, it is necessary to devise a circuit.

[0003]

2. Description of the Related Art FIG. 5 shows a schematic block diagram of a conventional image display control circuit. FIG. 6 shows an internal configuration diagram of the dual port memory. In the image display control circuit of FIG.
The dual port memory having the configuration of FIG. 6 is used.

In FIG. 6, a dual port memory 10 is shown.
0 is a 256 × 256 memory cell array 101, an address buffer 102, a row decoder 103 for selecting one row of the cell array 101, and 1 of a sense amplifier 105.
A column decoder 104 for selecting one and a row decoder 1
Sense amplifier 105 for reading the data selected in 03
And constitute a normal memory, and the data register 10 for one row (256 bits) of the memory cell array 101
8, a decoder 106 that selects the first data, and a shift register 107 that sequentially selects the data in the data register 108 form a serial port.

In this dual port memory 100, one row of the memory cell array 101 is read into the data register 108 in one read transfer cycle, and the clock CLK is output.
In synchronism with the above, the contents of the data register 108 can be sequentially read as the serial data SData.

Further, in FIG. 5, the image display control circuit is
A plurality of dual-port memories (100-1
-100-N) A memory 200 that stores display information in a parallel multiple bit configuration, and a horizontal synchronization signal Hsync # and a vertical synchronization signal Vs that periodically delimit data in each row.
sync # generation circuit 203 for generating sync #, address generation circuit 201 for generating an address for sequentially reading data of each row from memory 200 according to horizontal synchronization signal Hsync #, and display device 204 for displaying a plurality of bits read from memory 200. Or convert it to serial,
The data conversion circuit 202 converts the character code into a dot pattern. The display device 204 includes a horizontal synchronizing signal Hsyn from the synchronizing signal generating circuit 203.
The display data signal Data is sent from the data conversion circuit 202 as the c # and the vertical synchronization signal Vsync #.

For example, the screen configuration of the display device 204 is 256.
In the case of × 256 dots, it is sufficient to read out the data from the memory cell array 101 row by row and send it to the display device as it is.

By the way, as the screen configuration of the display device 204 in the current computer system, 640 × 400 dots is the mainstream. In addition, the memory is generally configured in units of 8 bits. In this case, the data for one line is 640/8 = 80 words. On the other hand, since one line of the dual port memory 100 has 256 words, 256
Words = 4 lines + 16 words, and the display line delimiter does not match the unit (for one row) of the memory cell array 101.

In FIG. 7, a row r of the dual port memory 100 is displayed on the display device 204 having a screen configuration of 640 × 400 dots.
The relationship diagram when ow0, row1, row2, ... Is mapped is shown. Further, FIG. 8 shows the dual port memory 100.
6 shows a timing chart when reading data from the.

As described above, when the data of one line of the display device 204 extends over different rows of the memory cell array 101, the row row0 is synchronized with the horizontal synchronizing signal Hsync #.
Data of the row is transferred to the data register 108 and the data is serially read from the head address of the line, and then the data of the row row1 is transferred to the data register 108 again in the middle of the i-th line of the display device 204 to continue the data. Need to read.

[0011]

Therefore, usually, the data processing is performed by determining that it is necessary to switch the rows of the memory by counting the addresses, but the processing is complicated. In addition, when the number of words from the first data of the line of the display device to the end of one row of the memory cell array is as small as several words, the period between the first transfer and the next transfer becomes short, and the precharge time of the dual port memory is reduced. In some cases, the display data cannot be read.

The present invention solves the above problems,
An object of the present invention is to provide an image display control circuit which can normally read out data with a relatively simple configuration even when one line of data in a display device extends over a plurality of rows of memory cell arrays.

[0013]

In order to solve the above problems, the image display control circuit of the first feature of the present invention is, as shown in FIG. 1, a memory 1 for storing display information, and a memory 1 for storing the display information. An address generation circuit 3 for generating addresses for sequentially reading display information, and a data conversion circuit 5 for converting the information read from the memory 1 according to a display device.
An image display control circuit, comprising: a control unit 7 for generating a synchronization signal Hsync # indicating the division of the display information and controlling reading from the memory 1.
Are composed of a plurality of memory cell arrays 1-1 to 1-L, and a plurality of words of display data are stored as one block in a cyclical manner in every block from an arbitrary memory cell array, and the control means 7 displays When reading the data of each display line of the device, the block containing the first data of the line and the subsequent L-1 blocks are controlled to be read simultaneously.

The image display control circuit according to the second aspect of the present invention is the image display control circuit according to claim 1,
As shown in FIG. 1, the memory 1 includes a memory cell array 1-1 in a matrix of M × N (M and N are arbitrary positive integers).
~ 1-L and a row decoder 11-1 for selecting M rows
~ 11-L and N-bit registers 12-1 to 12-L
A unit consisting of L and L (L is an arbitrary positive integer) is formed, and the control means 7 sets N words of display data to 1
Each block is cyclically stored as a block from any memory cell array in order, and when the data of each display line is read, the first data of each display line is stored from the memory cell array 1-i. Of the memory cell array 1-i-1 in which the last data of
12-i-1 and reads the registers 12-i-12
Control is performed so that data is serially output from -i-1 to the data conversion circuit 5.

An image display control circuit according to a third aspect of the present invention is the image display control circuit according to claim 1,
As shown in FIG. 3, the memory 1 includes M and N (M and N are arbitrary positive integer) matrix-shaped first and second dual port memories 2-1 and 2-2, and the address generation circuit. If the start address of each line from 3 corresponds to the first dual port memory 2-1, the same address is output to the first and second dual port memories 2-1 and 2-2, 2 dual port memory 2-2
In the case where it corresponds to, the address value obtained by adding 1 to the upper address of the address is added to the first dual port memory 2-1
To the first control circuit 8 which outputs to
And a second control circuit 9 for switching the outputs of the first and second dual-port memories 2-1 and 2-2 depending on whether or not N has been exceeded. Reference numeral 7 denotes the first and second dual port memories 2-1 and 2-using N words of display data as one block.
2 is stored alternately, and when the data of each display line is read out, the data of one display line is stored in the first and second dual ports by the first control circuit 8 and the second control circuit 9. Data is output serially from the memories 2-1 and 2-2.

An image display control circuit according to a fourth aspect of the present invention is the image display control circuit according to claim 2,
The memory 1 includes two units each including M × N (M and N are arbitrary positive integers) matrix memory cell arrays 1-1 and 1-2 and N-bit registers 12-1 and 12-2. Group and a selector that selects one from the outputs of the two sets of registers 12-1 and 12-2, and the two sets of registers 12-1 and 12-2 are connected to form a ring shape. Function as a shift register.

An image display control circuit according to a fifth aspect of the present invention is the image display control circuit according to claim 2,
The memory 1 includes two units each including M × N (M and N are arbitrary positive integers) matrix memory cell arrays 1-1 and 1-2 and N-bit registers 12-1 and 12-2. A pair, a counter that counts up to 2N, and a selector that selects one of the outputs of the two sets of registers 12-1 and 12-2 based on the counter output.

Furthermore, the image display control circuit of the sixth feature of the present invention is the image display control circuit according to claim 1, 2, 3, 4, or 5, wherein the control means 7 displays 1
The data of the line corresponds to the plurality of memory cell arrays 1-1 to 1-L or the dual port memory 2- in the memory 1.
Only when the data is stored in 1 and 2-2, the reading is performed simultaneously.

[0019]

In the image display control circuit of the first, second, fourth and fifth features of the present invention, the memory 1 is provided as shown in FIG.
M × N matrix memory cell arrays 1-1 to 1-
L and M corresponding to each memory cell array 1-1 to 1-L
Row decoders 11-1 to 11-L for selecting a plurality of rows,
A unit composed of N-bit data registers 12-1 to 12-L and an L set and a cell decoder 21 are configured.

The display data is cyclically stored for each block from an arbitrary memory cell array with N words as one block. When reading the data of each display line, the operation is as follows.

The cell decoder 21 outputs a signal indicating whether each of the memory cell arrays 1-1 to 1-L corresponds to a lower address or a higher address to a given lower address to each row decoder. 11-1 to 11-L
Output to. The row decoder 11-i (i = 1 to L) is
Based on the output of the cell decoder 21, one row of the memory cell array 1-i is selected according to the upper address when the address is equal to or higher than the specified address, and the next row of the memory cell array 1-i is selected when the address is lower than the specified address. Therefore, when the specified address corresponds to the i-th memory cell array 1-i, the row decoders 11-1 to 11-i-1
Selects the row next to the row specified by the high-order address, and the row decoders 11-i to 11-L select the row specified by the high-order address.

For example, as shown in FIG. 1, when the first data of one line to be displayed is in the second row row2-2 of the memory cell array 1-2, the memory cell arrays 1-2 to 1
-L selects the second row row2-2 to rowL-2, the memory cell array 1-1 selects the third row row1-3, row2-2 to rowL-2, row1-3.
Continuous image data of the data register 12-1 to 12
-L can be read. Therefore, even in the worst case where the first data of one line is at the end of row2-2, necessary image data of (L-1) × N words can be obtained.

Further, in the image display control circuit of the first and third features of the present invention, as shown in FIG.
Thus, when the head address of each line from the address generation circuit 3 corresponds to the first dual port memory 2-1, the same address is output to the first and second dual port memories 2-1 and 2-2. If it corresponds to the second dual port memory 2-2, the address value obtained by adding 1 to the upper address of the address is output to the first dual port memory 2-1 for memory access.
The second control circuit 9 counts from the column address to N, and switches the outputs of the first and second dual port memories 2-1 and 2-2 depending on whether or not N is exceeded and serially outputs data. I am trying.

Therefore, it is possible to output the image data without interruption from the first address. Furthermore, in the image display control circuit of the sixth feature of the present invention, the control means 7 causes
Only when the data of one line to be displayed is stored in the plurality of memory cell arrays 1-1 to 1-L in the memory 1 or the dual port memories 2-1 and 2-2, the simultaneous reading is performed. To

Therefore, power consumption can be reduced by reducing unnecessary memory accesses.

[0026]

Embodiments of the present invention will now be described with reference to the drawings. First Embodiment FIG. 2 shows a block diagram of an image display control circuit according to a first embodiment of the present invention.

In the figure, 256 × 256 first and second memory cell arrays 1-1 and 1-2, row decoders 11-1 and 11-2 for selecting rows, and data registers 12-1 and 12 are shown. -2 and two sets of units to configure the memory 1, and to configure the first memory cell array 1-1.
Is connected to a row decoder 11-1 via a shifter 24, and the second memory cell array 1-2 is directly connected to a row decoder 11-2.

An address generation circuit 3 for generating addresses A0 to A16 for sequentially reading display information from the memory 1, a data conversion circuit 5 for converting the information read from the memory 1 according to a display device, and display information. The timing generation circuit 7 that generates the synchronization signal Hsync # indicating the division of
And is omitted.

When the address A8 is at "L" level, the shifter 24 outputs the output of the row decoder 11-1 to the memory cell array 1-1 as it is, and the address A8 is "
In the case of the H "level, the output of the row decoder 11-1 is shifted by 1 bit and output to the memory cell array 1-1 to select the next row. Therefore, when the address A8 is in the" L "level. Two memory cell arrays 1-1 and 1-
When two identical rows are selected and the address A8 is at the "H" level, the first memory cell array 1-1 is the row next to the selected row of the second memory cell array 1-2,
It is transferred to the data registers 12-1 and 12-2.

The pointer p for designating the data to be read is
It is determined by the value of the shift register 22 that stores the result of decoding the lower addresses A0 to A8 by the decoder 23. By sequentially shifting the data of the shift register 23 by the clock CLK, the sequential data is selected and output as serial data SData. It

Therefore, even if the first data of the line is stored at the end of one of the memory cell arrays 1-1 or 1-2, consecutive data is simultaneously transferred from the other memory cell array 1-2 or 1-1. Since it is being read, the data is not interrupted.

In this embodiment, the reading after the data is transferred to the data registers 12-1 and 12-2 was carried out by the pointer p by the decoder 23 and the shift register 23, but the data registers 12-1 and 12- Two
With the shift register configuration, the data may be sequentially read out, or a counter may be provided and the data registers may be sequentially selected and read out.

In this embodiment, all the memory cell arrays are always read at the same time, but only the required memory cell array may be read by decoding the address and the required number of data. In this case, it is possible to reduce power consumption by reducing unnecessary memory accesses. Second Embodiment FIG. 3 shows a block diagram of an image display control circuit according to a second embodiment of the present invention.

In the figure, the image display control circuit of this embodiment comprises a memory 1, an address generation circuit 3, a timing generation circuit 7, a first control circuit 8, a second control circuit 9 and a data register 12. Has been done.

The memory 1 is composed of first and second IC dual port memories 2-1 and 2-2. The first control circuit 8 includes an adder 8A and multiplexers 8M1 and 8M2. The first dual-port memory 2-1 includes addresses A0 to A7 and addresses A0.
Outputs 9 to A16 obtained through the adder 8A are time-divisionally applied by the multiplexer 8M1, and addresses A0 to A7 and addresses A9 to A16 are timed by the multiplexer 8M2 to the second dual port memory 2-2. Data is read out by applying it to the divisions. The adder 8A
Is to add address A8 to addresses A9 to A16.

With this configuration, when the first dual port memory 2-1 is designated (address A
8 is "L" level), the same row address is applied to the first and second dual port memories 2-1 and 2-2, and the second dual port memory 2-2 is designated. When the address A8 is at the "H" level, the first dual port memory 2-1 is applied with a row address that is one higher than the row address specified for the second dual port memory 2-2. It

The second control circuit 9 includes a counter 9
C, JK flip-flop 9F, exclusive OR gate 9
G and a selector 9S, and the output data of the first and second dual port memories 2-1 and 2-2 are selected by the selector 9S and only one data is output. This selection is performed by the counter 9C having the addresses A0 to A7 as the initial value, counting from the column address to 255, and the carry signal CARR indicating whether or not it exceeds 255.
It is determined by the exclusive OR of Y and the address A8.

Further, generation of control signals RAS # (row address strobe signal) and CAS # (column address strobe signal) to the first and second dual port memories 2-1 and 2-2, and control of the counter 9C. Is performed by the timing generation circuit 7.

FIG. 4 is a timing chart for explaining the operation of the image display control circuit of this embodiment. The addresses A0 to A16 are output from the address generating circuit 3 in synchronization with the horizontal synchronizing signal Hsync #, and the JK flip-flop 9F is cleared. First dual port memory 2
The lower addresses A0 to A7 and the upper addresses A9 to A16 passed through the adder 8A are multiplexed and applied to -1, and the lower addresses A0 to A7 and the upper addresses A9 to are applied to the second dual port memory 2-2. A16 is directly multiplexed and applied.

From the timing generation circuit 7, a control signal R
AS # and CAS # are applied to the first and second dual port memories 2-1 and 2-2, respectively, and data Da
ta1 and Data2 are read at the falling edge of the clock CLK.

In the example of FIG. 4, the first data of the line is 2
It is the 40th data, and the 0th data is read from the first dual port memory 2-1 next to the 255th data.

The counter 9C starts counting from the lower address A0 to A7 at the time of reading the first and second dual port memories 2-1 and 2-2, and when it exceeds 255, the carry signal CARRY causes a JK signal. Set the flip-flop 9F. The exclusive OR of the output of the JK flip-flop 9F and the address A8 causes the selector 9S to output the first and second dual port memories 2-1.
2 and 2-2 outputs Data1 and Data2 are selected.

Therefore, the obtained data SData is uninterrupted from the first address as shown in FIG.

[0044]

As described above, according to the present invention,
The control means cyclically stores N words of display data as one block for each block from an arbitrary memory cell array, and when reading the data of each display line, the first data of each display line is stored. The data in the memory cell array from the existing memory cell array to the memory cell array in which the last data of the display line is stored is read into a register, and the register is controlled to be serially output to the data conversion circuit. As a result, it is possible to provide an image display control circuit which can normally read out data with a relatively simple configuration even when one line of data in a display device extends over a plurality of rows of memory cell arrays.

Further, according to the present invention, when the first control circuit causes the start address of each line from the address generation circuit to correspond to the first dual port memory, the first control circuit
And the same address is output to the second dual-port memory, and when the second dual-port memory is supported, an address value obtained by adding 1 to the lower address of the address is first.
To the dual port memory for memory access. On the other hand, the second control circuit counts the column address to N, and outputs the first and second dual port memories depending on whether or not N is exceeded. Since the data is switched and serially output, it is possible to provide an image display control circuit that can normally read data with a relatively simple configuration.

Furthermore, according to the present invention, the control means
Only when the data of one line to be displayed is stored in a plurality of memory cell arrays in the memory 1 or the dual port memory, the simultaneous reading is performed. Electric power can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of an image display control circuit according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of an image display control circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the image display control circuit of the second embodiment.

FIG. 5 is a schematic configuration diagram of a conventional image display control circuit.

FIG. 6 is an internal configuration diagram of a dual port memory.

FIG. 7 is a relationship diagram when a row of the dual port memory is mapped to the display device.

FIG. 8 is a timing chart when reading data from a conventional dual port memory.

[Explanation of symbols]

 1 ... Memory 1-1, 1-2 ... First and second memory cell arrays 1-1 to 1-L ... Memory cell array 2-1, 2-2 ... First and second dual port memory 3 ... Address generation Circuit 5 ... Data conversion circuit 7 ... Timing generation circuit (control means) 8 ... First control circuit 8A ... Adder 8M1, 8M2 ... Multiplexer 9 ... Second control circuit 9C ... Counter 9F ... JK flip-flop 9G ... Exclusive OR gate 9S ... Selector 11-1 to 11-L ... Row decoder 12, 12-1 to 12-L ... (Data) register 21 ... Cell decoder 22 ... Shift register 23 ... Decoder 24 ... Shifter CLK ... Clock A0-A16 ... Address SData ... Serial data p ... Pointer Hsync # ... Horizontal sync signal Vsync # ... Vertical sync signal CARRY ... Carry Signal RAS #, CAS # ... control signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yoshiya Kaneko 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (6)

[Claims] 1. A memory (1) for storing display information, an address generating circuit (3) for generating an address for sequentially reading display information from the memory (1), and information read from the memory (1). A data conversion circuit (5) for converting the data according to the display device, and a control means (7) for generating a synchronization signal (Hsync #) indicating the delimiter of the display information and controlling reading from the memory (1). An image display control circuit, comprising: a memory (1) comprising a plurality of memory cell arrays (1-1
.. 1-L), and multiple words of display data
Each block is cyclically stored as a block from an arbitrary memory cell array in order, and the control means (7), when reading the data of each display line of the display device, includes a block including the first data of the display line. , And an image display control circuit characterized by controlling so that the subsequent L-1 blocks are read out at the same time. 2. The memory (1) is a memory cell array (1) in a matrix of M × N (M and N are arbitrary positive integers).
-1 to 1-L), row decoders (11-1 to 11-L) that select M rows, and an N-bit register (12
-1 to 12-L), L (L is an arbitrary positive integer) sets, and the control means (7) sets N words of display data as one block and selects one block from any memory cell array. When the data of each display line is read out, the last data of the display line is stored from the memory cell array (1-i) in which the first data of each display line is stored. Memory cell array (1-i-
The data of the memory cell array up to 1) is stored in the register (1
2-i to 12-i-1), and control is performed so as to serially output data from the registers (12-i to 12-i-1) to the data conversion circuit (5). The image display control circuit according to claim 1. 3. The memory (1) includes first and second dual port memories (2-1 and 2-2) in a matrix of M × N (M and N are arbitrary positive integers), When the start address of each line from the address generation circuit (3) corresponds to the first dual port memory (2-1), the first and second dual port memories (2-1 and 2-2) The same address is output to the second dual port memory (2-2), an address value obtained by adding 1 to the upper address of the address is output to the first dual port memory (2-1). A first control circuit (8) for outputting and counting from a column address to N, and depending on whether or not N is exceeded, the first and second dual port memories (2-
And a second control circuit (9) for switching the outputs of 1 and 2-2), and the control means (7) uses the N words of the display data as one block for the first and second dual port memories. When alternately storing in (2-1 and 2-2) and reading out the data of each display line, the first control circuit (8) and the second control circuit (9) store one display line worth of data. Data of the first and second dual port memories (2-1
2. The image display control circuit according to claim 1, wherein the data is output serially from 2). 4. The memory (1) is a memory cell array (1) in a matrix of M × N (M and N are arbitrary positive integers).
-1, 1-2) and an N-bit register (12-1, 1)
2-2) and a selector that selects one from the outputs of the two sets of registers (12-1, 12-2), and the two sets of registers (12-1) , 12-2) are connected to function as a ring-shaped shift register. 5. The memory (1) includes a memory cell array (1) in a matrix of M × N (M and N are arbitrary positive integers).
-1, 1-2) and an N-bit register (12-1, 1)
2-2), two sets of units, a counter that counts up to 2N, and a selector that selects one of the outputs of the two sets of registers (12-1, 12-2) based on the counter output. The image display control circuit according to claim 2, further comprising: 6. The control means (7) displays one line of data in a plurality of memory cell arrays (1-1 to 1-L) or dual port memories (2-1 and 2-1) in the memory (1). The image display control circuit according to claim 1, wherein reading is simultaneously performed only when the data is stored over 2-2).