JP2003068072A - Frame memory circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a frame memory in which needless memory, needless write- in/read-out of data, and disturbance of a screen are prevented, and various image can be expressed with simple constitution of a circuit. SOLUTION: This frame memory circuit is a command control type, memory elements consisting of DRAM specifying an access word by row and column addresses are used, this memory element generates a memory access basic command cycle of a read-command or a write-command alternately, a read- command or a write-command is permitted only if necessary or a write-in/read- out counter is sequentially increased in the direction of row, when it exceeds the maximum value of the memory element, a column is increased, operation for restoring a row to the minimum value is performed, and a refresh-cycle is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frame memory circuit used for digital video signal processing and the like.

[0002]

2. Description of the Related Art The following techniques have been known as conventional techniques relating to frame memories. (1) The technique disclosed in Japanese Patent Application Laid-Open No. 2000-244839 uses synchronization in order to prevent video data from being written to an area other than a designated writing area of the memory even when the synchronization signal is unstable or absent. A first counter that is reset by a signal and counts a reference clock, and a count value between the start point and the end point of the writing area.
A write enable signal generation unit that generates a write enable signal, a second counter that takes in start point position data using a synchronization signal as a load signal, and counts a reference clock using a write enable signal as an enable signal, and the count value and end point position data. And a coincidence detection unit that uses the detection signal as the load signal of the second counter, and uses the count value of the second counter as the write address of the memory.

(2) The technique disclosed in Japanese Patent Application Laid-Open No. 2000-284766 reduces the capacity required for the memory used for multi-channel display so that inconvenience does not occur at the execution timing of the still function and the cancellation of the still function. In the memory, first storage areas 4 to 5 for storing video data of a plurality of channels and second storage areas 1 to 6 for storing video data of a moving image display channel among them are provided. The moving picture storage areas 2 to 3 and the areas 1 to 6 are switched by the write side parity signal WP for each field and output, and the count value of the counter is used as the write address. The output of the counter counting from the area start point 1 and the parity signal RP on the read side
Select the read address of the memory by switching with, and use the quiescent instruction to write the read area of the memory
The fixed area is fixed to 5, and the read area fixed release of the memory 26 is released from the areas 1 to 6 after the writing is started by releasing the stationary instruction.

(3) In the technique described in Japanese Patent Application Laid-Open No. 2000-284771, the image memory is composed of a DRAM and the DR
The memory area of the AM is composed of five memory areas M1 to M5 in which the column direction of the address is divided into five, and the input Y and C signals are converted by the data length conversion unit to increase the data length and then M1 in the DRAM. To M5 are cyclically written and cyclically read, and the Y and C signals read from the DRAM by the read data control unit are delayed by 1, 2 and 3 frames.
Signal (Y-1F to Y-3F), C with 1 or 2 frame delay
The signals are sorted into signals (C-1F, C-2F), converted to the original data length, and output.

[0005]

The above-mentioned conventional techniques have the following problems to be solved. (1) A complicated circuit is used to calculate a row address and a column address. Moreover, the memory space is wasted. Furthermore, when performing processing such as enlarging / reducing, it may happen that only one signal is issued for control, but the conventional control method could not perform more complicated control. (2) The clock supplied to the memory element requires a fixed frequency other than the write clock and the read clock. (3) Since the end point processing is performed without using the data mask function of the memory element or the shift register, unnecessary data is written or read.

(4) The frame memory does not have the one-shot writing function. (5) Dual screen function, with two write addresses, 1
One was set to the display position, but the other was not set outside the display range (outside the read range) and was set inside the display range. Therefore, when changing the display position, a sequence is set up. It was necessary to operate two addresses with. (6) The various control signals are not synchronized with the vertical synchronization signal, and the image may be disturbed and stopped in the middle of one screen.

The present invention provides a frame memory capable of simplifying the circuit configuration, eliminating waste of memory, eliminating unnecessary data writing and reading, eliminating screen disturbance, and capable of expressing various images. The purpose is.

[0008]

SUMMARY OF THE INVENTION The present invention has as its basic constituent element a memory element which is of a command control type and which comprises a DRAM for designating an access word by a row address and a column address. , The memory access basic command cycle in this memory element is alternately generated for read and write, and the read command or write command is permitted only when necessary, and the write and read counters are sequentially increased in the row direction, A configuration in which a refresh cycle is eliminated by incrementing a column when the maximum value of the memory element is exceeded, returning a row to a minimum value, and circulating a DRAM address a plurality of times in one frame. Characterized by combining any one or two of the elements A frame memory circuit.

With the above-mentioned structure, the circuit is simplified, the memory space is not wasted, the circuit for supplying the memory element uniquely is not required, and unnecessary data writing / writing is performed. No need to read, no need to set sequence when changing write address to be displayed by dual screen function, setting is simple, and various control signals are synchronized by VSYNC. The image is disturbed in the middle of one screen,
It has excellent effects such as elimination of the problem of stillness, and the possibility of expressing various images by combining functions such as a mirror inversion function, a one-shot function, and a two-screen function.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. (1) Functional description of each control signal WRSTX: A signal issued once in one frame to initialize a write operation. WEN: A signal that permits writing to the memory. WLENDX: A signal issued once per line to indicate the end of writing. WLINCX: A signal issued once per line to increment the write address by one line. RRSTX: A signal issued once per frame to initialize the read operation. REN: A signal that permits reading from the memory. RLSTRX: A signal that is issued once per line and indicates the beginning of the line. RLINCX: A signal issued once per line to increment the read address by one line.

(2) Description of Basic Operation FIG. 1 is a block diagram of a frame memory circuit according to the present invention. The write data register section 10, DRAM 11,
It is composed of a read data register section 12 and a frame memory control section 13. The Y data input terminal 1 is provided on the input side of the write data register unit 10.
4, Cr data input terminal 15 and Cb data input terminal 1
6 is connected to the frame memory control unit 13
Various control signal input terminals 17 are connected to the input side of
A Y output terminal 18, a Cr output terminal 19 and a CB output terminal 20 are connected to the output side of the read data register section 12.

The frame memory control section 13 generates a control signal for the write data register section 10 and D
Command signal generation to the RAM 11 and control signal generation to the read data register unit 12 are performed. In the write data register unit 10, the frame memory control unit 1
Data is written to the DRAM 11 in accordance with the write system control signal from 3. The read data register section 12
Then, according to the read system control signal from the frame memory control unit 13, the data is read from the DRAM 11.

The DRAM 11 has data input, address input, and various command inputs (BACT, BPRC, RE).
AD, WRITE, REF), data output, and data mask output. As shown in FIG. 6, the DRAM 11 has a structure in which one word has 32 dots, and one dot has 8 bits of data, so that one word has 256 bits. By using the data mask function of the DRAM 11, it is possible to control the starting point coordinates, the ending point coordinates, and the width of the image on a dot-by-dot basis. Also, D
The command cycle given to the RAM 11 is shown in FIG. In FIG. 7, AC: bank active,
NO: non-operation, RE: read, WR: write, PR: precharge.

The frame memory control unit 13
2 shows a block diagram thereof, the command generation unit 21, the overtaking detection unit 22, the write command generation unit 2
3, a read command generator 24, a write address generator 25, a read address generator 26, and a write / read address selector 27. On these inputs, the write system setting signal input terminal 28 and the write system control signal input terminal 2
9, a read system setting signal input terminal 30, a DRAM reset signal input terminal 31, and a read system control signal input terminal 32 are connected, and an address signal output terminal 3 is provided on the output side.
3, write data control signal output terminal 34, read data control signal output terminal 35 and DRAM control signal output terminal 3
6 is connected.

As shown in FIG. 12, the overtaking detecting section 22 causes the overwriting because the writing and the reading are asynchronous. Therefore, overtaking detection is performed from the write and read parities, and an overtaking control signal is generated and output. As shown in FIG. 3, the command generating unit 21 includes a counter 37 and a decoder 38. A signal from the DRAM reset signal input terminal 31 is input to the input side of the counter 37, and the command generating unit 21 also receives the signal. Two
In 1, the command generation to the DRAM 11 is mainly performed, and D
The write control signal, the read control signal, and the write / read address selection signal are also transmitted to the DRAM 11 via the RAM control signal output terminal 36, and the write command generation unit 23 and the read command generation unit 2 are generated, respectively.
4 and write / read address selection unit 27.

In the write command generator 23, the write system setting signal from the write system setting signal input terminal 28,
A write address control signal from the write control signal input terminal 29 is used to generate a write address control signal and a write data control signal. The write address generator 25
Then, the write address is generated by the write system setting signal, the write system control signal, and the write address control signal from the write command generation unit 23.

The read command generator 24 generates a read address control signal and a read data control signal based on the read system setting signal and the read system control signal. In the read address generation unit 26, a read system setting signal, a read system control signal and a read command generation unit 24.
A read address is generated by a read address control signal from the. The write / read address selection unit 27
Then, the write address and the read address are selected according to the address selection signal from the command generator 21.

The write data register section 10 is shown in FIG.
As shown in, the shift register section 77, the first buffer 78, and the second buffer 76 are included.
In the shift register unit 77, 8-bit data is serial-parallel converted according to the shift enable signal,
Convert to 256-bit data. When the serial-parallel conversion is completed, a fast buffer enable signal is generated and data is stored in the fast buffer 78. When the second buffer 76 is empty or after the data in the second buffer 76 has been written to the DRAM 11, data is transferred from the first buffer 78 to the second buffer 76 according to the second buffer enable signal. When data is accumulated in the second buffer 76 and a write command is issued, 1 is written to the DRAM 11.
Data is written in 256 bits. With this repetition, the write operation is performed.

As shown in FIG. 5, a block diagram of the read data register section 12 includes a circuit (a) composed of a buffer 39a and a selector 40a and a circuit (b) composed of a buffer 39b and a selector 40b arranged in parallel with each other. The 3-1 selector 41 is provided and connected to the output side of these circuits. The circuit (c) including the buffer 39c and the selector 40c is used in the multi-channel function, and the details will be described later.

In such a circuit configuration, since data must be output from the frame memory circuit in accordance with REN for reading, data may be accumulated in the buffer 39 from the DRAM 11 before REN is input to the frame memory circuit. There must be. Therefore, RL
The read command immediately after the STRX is input causes the buffer 39a of the circuit (a) to store 256-bit line head data, and the next read command causes the buffer 39b of the circuit (b) to store the 256-bit data of the second line. Accumulate data. When REN is input to the frame memory circuit, parallel-serial conversion is performed by the selector 40a or the selector 40b according to the select signal in the read data control signal from the read command generation unit 24, and 25
Convert 6-bit data to 8-bit data. Further, the data of the circuit (a) or (b) is selected by the 3-1 selector 41 in the subsequent stage. After REN is input to the frame memory circuit, the data of the circuit (a) or (b) is output every time REN is input by 32CK. Therefore, all the data of the buffers 39a and 39b are output. Immediately after the read command, an enable signal is generated at the same time, and the data in the buffers 39a and 39b is updated. The read operation is performed by repeating this operation.

(3) End point processing The right and left end points of the image are processed by using the data mask function attached to the DRAM 11. The left end and right end are processed as follows. 3-1: Data on the left side is masked by the number left at the left end HSTR (horizontal start point coordinate) / 32. For example, if HSTR = 37, HSTR / 32 = 1 and the remainder becomes 5, and the first 5 dots that are continuous with the first word in the second word are DRAM.
End point processing is performed using the data mask function 11 of FIG. 3-2: The right side data is masked by the number obtained by subtracting 32 from the right end (the number of HSTR + WEN) / 32. For example,
If HSTR = 37 and the number of WENs = 200, then (HSTR + 200) / 32 = 7 remainder 13 32−13 = 19, and the first 13 dots that are continuous with the 7th word in the 8th word are not data-masked. The 19-dot shift register and the data mask function of the DRAM 11 are used to perform end point processing.

(4) CK supplied to the DRAM 11 As the clock MCK supplied to the DRAM 11, a high frequency clock is selected and used from the write system clock SCK and the read system clock PCK. However, if the frequencies are the same, the read system clock PCK is selected.

(5) Address calculation method Write address generator 25 and read address generator 26
The basic operation of writing and reading is the same as the method of calculating an address by the X counter 42, as shown in FIG.
Y counter 43, adder 44 and two DFFs 45, D
It consists of FF46. In FIG. 8, assuming that the vertical start point coordinate is p on the n line, first, the Y counter 43 determines the start point corresponding to the p on the n line on the address map shown in FIG. 9, and the X counter 42 sets 1 row (1 row (1 The address is calculated by incrementing each word (32 dots), and data writing / reading is performed. One line (eg 1
When the writing or reading of (00 rows) is completed, the number of rows of one line is added to the Y counter 43 by the adder 44 by the increment signal, the starting point on the address map corresponding to the (n + 1) th line is determined, and the nth line Perform the same processing as. The DFF 45 carries out a carry for every 250, for example, and outputs a column address, and the DFF 46 outputs, for example, a row address in units of 250. In this way, the calculation is performed on the scale of the X counter 42 / Y counter 43, and it is assigned to the row address / column address. This allocation is as follows: The number of write words for one line is designated in advance, and the Y counter 43 adds the number of write words for one line. Alternatively, the number of write words for one line is designated in advance, and the Y counter 43 is multiplied by the number of write words for one line when the address is converted. .. Alternatively, the number of write pixels for one line is designated in advance, and the number of write words for one line is calculated.
Add the number of write words for one line. Alternatively, the number of write pixels for one line is designated in advance, the number of write words for one line is calculated, and the Y counter 43 and the number of write words for one line are multiplied at the time of address conversion. When handling a plurality of data such as RGB, as shown in FIG. 10, an adder 4 is added between the adder 44 and the DFF 45.
4a is inserted, a necessary value is added only to the column address, and data writing / reading is performed. A specific example will be described based on the address map shown in FIG.
After writing the data of 1 to pr, when writing G data, add 20 and write to pg, and when writing B data, add 20 and write to pb. When handling n kinds of data, the DRAM 11 is divided into n pieces and the same address calculation is performed.

[0024] (6-1) vertical mirror inversion function (1) When performing the vertical mirrored by the write side are the same as the image display number of lines of one frame in the Y counter 43 _first write vertical start point coordinates in Fig. 27 When the value, that is, the value of the last line is loaded and the write line increment signal is input, the number of rows of one line is subtracted, the write address in the line direction is determined, and writing to the DRAM 11 is performed from the beginning as usual. Do vertical mirror inversion. In this way, when writing, the data in the line direction of one frame is rearranged vertically and written in the memory 11, and reading is performed in the forward direction from the beginning of writing and vertical mirror inversion processing is performed.

[0025] (6-2) vertical mirror inversion function (2) when performing the vertical mirrored in the lead side, writing is carried out as usual, the video display line in the Y counter 43 _second read vertical start point coordinates in Fig. 27 The same value as the number, that is, the value of the final line is loaded, and when the read line increment signal is input, the row number of one line is subtracted, the read address in the line direction is inverted, and reading is performed to invert the vertical mirror. To do. In this way, writing is performed in the memory 11 in the forward direction from the beginning of the input data, and in reading, the vertical mirror inversion processing is performed by performing the writing in the reverse direction from the written data of the lowermost line of one frame.

(6-3) Horizontal Mirror Inversion Function (No. 1) In normal horizontal data, one line consists of n words and the number of data in one word is m. In the example below, FIG.
As shown in 0 (a), the case where one line has three words and the number of data of one word is 20 will be described. When horizontal mirror inversion is performed on the write side in such an arrangement of horizontal data, it is necessary to invert the words in the line and the data in the word. At the writing horizontal start point coordinate of the X counter 42 ₁ shown in 27, the same value as the display width of the image, that is,
The value at the right end in FIG. 30A is loaded, and when the count enable signal is input, it is down-counted and the write address is inverted. The inversion of the data in the word is reversed and transferred to the first buffer 78 of the write data register unit 10 shown in FIG. 4 by reversing the order of the data at the time of serial-parallel conversion, and the subsequent processing is the same as usual. Then, the DRAM 11 is written (see FIG. 30).
(B)). Reading is performed from the beginning as usual, and horizontal mirror inversion is performed. In this way, when writing, the arrangement of the words on one line and the arrangement of the data within the words are both reversed in the opposite direction and written into the memory 11, and reading is performed from the beginning of the writing in the forward direction, and the horizontal mirror Reverse processing is performed. The display data at this time is shown in FIG.
Shown in.

(6-4) Horizontal Mirror Inversion Function (Part 2) When the address is inverted on the write side and the data is inverted on the read side to perform the horizontal mirror inversion, first, FIG.
The write horizontal start point coordinate of the X counter 42 ₁ shown in FIG. 7 is loaded with the same value as the display width of the image, that is, the value at the right end in FIG. Invert. The inversion of the data in the word is reversed and transferred to the first buffer 78 of the write data register unit 10 shown in FIG. 4 by reversing the order of the data at the time of serial-parallel conversion, and the subsequent processing is the same as usual. And DRAM
Writing is performed in 11 (FIG. 30C). in this way,
At the time of writing, the arrangement of the data in the word is left as it is, and only the arrangement of the words of one line is reversed in the reverse direction to write it in the memory 11, and in the reading, the arrangement of the data in the written word is reversed in the reverse direction. At the same time, the words on one line are arranged in the forward direction to perform the horizontal mirror inversion process.
The display data at this time is shown in FIG.

(6-5) Horizontal Mirror Inversion Function (Part 3) In the case of inverting the address on the read side and inverting the data on the write side to perform the horizontal mirror inversion, first, FIG.
X counter 42 _second read horizontal start coordinate equal to the display width of the picture to that shown in 7, i.e., loads the value of the right end in FIG. 30 (a), the by counting down Once in the count enable signal, a read address Invert. Further, the inversion of the data in the word is performed by converting the order of the data in the serial-parallel conversion to the D shown in FIG.
Writing is performed in the RAM 11 (FIG. 30 (d)). In this way, when writing, the arrangement of words on one line is left unchanged, only the arrangement of data in words is inverted in the opposite direction to write to the memory 11, and for reading, the arrangement of words on one line is written. The horizontal mirror inversion processing is performed in the reverse direction and by arranging the data in the word in the forward direction. The display data at this time is shown in FIG.

(6-6) Horizontal Mirror Inversion Function (4) When horizontal mirror inversion is performed on the read side, the word in the line is inverted by inverting the read address. Figure 2
X counter 42 _second read horizontal start coordinate equal to the display width of the picture to that shown in 7, i.e., loads the value of the right end in FIG. 30 (a), the by counting down Once in the count enable signal, a read address Invert. Further, the inversion of the data in the word is performed by converting the serial-parallel conversion in the read data register unit 12 in the order reverse to the normal order and inversion (FIG. 30).
(E)). In this way, writing is performed in the memory 11 in the forward direction from the beginning of the input data, and reading is performed by inverting both the written one-line word arrangement and the data arrangement within the word in the opposite direction, and then horizontally. Mirror inversion processing is performed. The display data at this time is shown in FIG.

(6-7) Vertical / Horizontal Mirror Inversion Function (No. 1) The vertical / horizontal mirror inversion function is performed by the combination of the vertical mirror inversion function (No. 1) and the horizontal mirror inversion function (No. 1). That is, the vertical mirror inversion function (No. 1), when writing, vertically rearranges the data in the line direction of one frame and writes the data in the memory 11, and the reading is performed in the forward direction from the beginning of the writing to perform the vertical mirror inversion processing. And then
At the same time, the horizontal mirror inversion function (No. 1) inverts the arrangement of the words of one line and the arrangement of the data in the words in the opposite direction at the time of writing, and writes the same in the memory 11.
Reading is performed in the forward direction from the written head and horizontal mirror inversion processing is performed to perform vertical / horizontal mirror inversion.

(6-8) Vertical / Horizontal Mirror Inversion Function (Part 2) Vertical / horizontal mirror inversion is performed by a combination of the vertical mirror inversion function (No. 1) and the horizontal mirror inversion function (No. 2). That is, the vertical mirror inversion function (No. 1), when writing, vertically rearranges the data in the line direction of one frame and writes the data in the memory 11, and the reading is performed in the forward direction from the beginning of the writing to perform the vertical mirror inversion processing. And then
At the same time, the horizontal mirror inversion function (part 2) keeps the arrangement of data in words as it is at the time of writing, and inverts only the arrangement of words in one line in the reverse direction, so that the memory 11
Writing and reading are performed by arranging the data in the written word in the reverse direction and by arranging the words of one line in the forward direction to perform the horizontal mirror inversion process.
Vertical / horizontal mirror inversion.

(6-9) Vertical / Horizontal Mirror Inversion Function (3) Vertical / horizontal mirror inversion is performed by a combination of the vertical mirror inversion function (2) and the horizontal mirror inversion function (1). That is, in the vertical mirror inversion function (No. 2), writing is performed in the memory 11 in the forward direction from the beginning of the input data, and in reading, the writing is performed in the reverse direction from the written data of the lowermost line of one frame. The vertical mirror inversion processing is performed, and at the same time, the horizontal mirror inversion function (part 1) inverts both the word arrangement of one line and the data arrangement in the word in the opposite direction at the time of writing, and writes the same in the memory 11. Reading is performed in the forward direction from the written head and horizontal mirror inversion processing is performed to perform vertical / horizontal mirror inversion.

(6-10) Vertical / Horizontal Mirror Inversion Function (Part 4) Vertical / horizontal mirror inversion is performed by a combination of the vertical mirror inversion function (No. 2) and the horizontal mirror inversion function (No. 2). That is, in the vertical mirror inversion function (No. 2), writing is performed in the memory 11 in the forward direction from the beginning of the input data, and in reading, the writing is performed in the reverse direction from the written data of the lowermost line of one frame. The vertical mirror inversion processing is performed, and at the same time, the horizontal mirror inversion function (part 2) retains the data arrangement in the word as it is at the time of writing, and inverts only the word arrangement of one line in the reverse direction, and the memory 11 For writing and reading, the arrangement of the data in the written word is performed in the reverse direction and the arrangement of the words of one line is performed in the forward direction, and the horizontal mirror inversion processing is performed to perform the vertical / horizontal mirror inversion. .

(6-11) Vertical / Horizontal Mirror Inversion Function (Part 5) Vertical / horizontal mirror inversion is performed by a combination of the vertical mirror inversion function (No. 1) and the horizontal mirror inversion function (No. 3). That is, the vertical mirror inversion function (No. 1), when writing, vertically rearranges the data in the line direction of one frame and writes the data in the memory 11, and the reading is performed in the forward direction from the beginning of the writing to perform the vertical mirror inversion processing. And then
At the same time, the horizontal mirror inversion function (part 3) keeps the arrangement of the words of one line as they are, and reverses only the arrangement of the data in the words in the reverse direction when writing.
Writing and reading are performed by arranging the written 1-line words in the reverse direction and by arranging the data in the words in the forward direction to perform horizontal mirror inversion processing.
Vertical / horizontal mirror inversion.

(6-12) Vertical / Horizontal Mirror Inversion Function (Part 6) Vertical / horizontal mirror inversion is performed by a combination of the vertical mirror inversion function (No. 1) and the horizontal mirror inversion function (No. 4). That is, the vertical mirror inversion function (No. 1), when writing, vertically rearranges the data in the line direction of one frame and writes the data in the memory 11, and the reading is performed in the forward direction from the beginning of the writing to perform the vertical mirror inversion processing. And then
At the same time, the horizontal mirror inversion function (No. 4) writes in the memory 11 in the forward direction from the beginning of the input data,
Reading is performed by inverting the written one-line word arrangement and the data arrangement in the word in opposite directions, and performing horizontal mirror inversion processing to perform vertical / horizontal mirror inversion.

(6-13) Vertical / Horizontal Mirror Inversion Function (No. 7) Vertical / horizontal mirror inversion is performed by a combination of the vertical mirror inversion function (No. 2) and the horizontal mirror inversion function (No. 3). That is, in the vertical mirror inversion function (No. 2), writing is performed in the memory 11 in the forward direction from the beginning of the input data, and in reading, the writing is performed in the reverse direction from the written data of the lowermost line of one frame. The vertical mirror inversion processing is performed, and at the same time, the horizontal mirror inversion function (part 3) retains the word arrangement of one line as it is during writing, and inverts only the data arrangement in the word in the reverse direction, and the memory 11 For writing and reading, the arrangement of the written 1-line words is performed in the reverse direction, and the arrangement of the data in the words is performed in the forward direction, and the horizontal mirror inversion processing is performed to perform the vertical / horizontal mirror inversion. .

(6-14) Vertical / horizontal mirror inversion function (No. 8) Vertical / horizontal mirror inversion is performed by a combination of the vertical mirror inversion function (No. 2) and the horizontal mirror inversion function (No. 4). That is, in the vertical mirror inversion function (No. 2), writing is performed in the memory 11 in the forward direction from the beginning of the input data, and in reading, the writing is performed in the reverse direction from the written data of the lowermost line of one frame. The vertical mirror inversion process is performed, and at the same time, the horizontal mirror inversion function (part 4) writes in the memory 11 in the forward direction from the beginning of the input data, and reads out the sequence of words in one line written and the word By inverting both data rows in the opposite direction and performing horizontal mirror inversion processing,
Performs horizontal mirror inversion.

(7) Overtaking reduction processing function When using the two-screen function or the multi-channel function,
Overwriting occurs because writing and reading are asynchronous. Details of the overtaking detection unit 22 are shown in FIG.
Overtaking detection is performed from the write and read parities, and an optimal address is selected from the two addresses, the address of the display position and the address outside the display range, according to the generated overtaking control signal, and reading is performed.

(8) Dual-screen function As shown in FIG. 13 (a), when a dual-screen image displaying a sub-screen 49 on the main screen 48 is constructed, as shown in FIG. 14, a main LSI 50 and a sub-LSI 51 are provided. Is used. Of these, the main LSI 50 performs image processing of the main screen 48 input from one of the input terminals 52 as usual, but in the area of the sub screen 49 in FIG. 13A, input from the other input terminal 53 to the sub LSI 51. The selected sub-screen 49 is selected and output to the output terminal 54 to form a two-screen image. The sub LSI 51 is the DRAM 1
1 memory area is divided into two banks, A bank and B bank.
As shown in the timing chart of FIG. 5, the A or B bank is written according to the write parity, the data of the A or B bank is read according to the read bank switching signal, and the sub screen 49 as shown in FIG.
To synthesize. In the sub-LSI 51, the write sync signal and the read sync signal are out of sync with each other, so that overtaking occurs. In the case of FIG. 15, during the period from detection of overtaking to detection of next overtaking, the read parity inversion signal is output to the read bank switching signal, and overtaking is performed again in the frame next to the frame in which overtaking has occurred. Read the data of the occurred frame.

(9) Multi-channel function Even when the multi-channel function is used, the main LSI 50 and the sub L are connected as shown in FIG.
Two of SI51 are used. The multi-channel will be described with reference to FIG. In the main LSI 50 on the main screen 48 side shown in FIG. 16A, the image processing of the main screen 48 is performed as usual as in the case of the two-screen function, and in the multi-channel area 55, the image combined by the sub-LSI 51 is displayed. Select and output to configure multi-channel video. In the sub-LSI 51, one screen of moving image and several screens of still image are configured. The sub LSI 51, as shown in FIG.
An area in which an image is displayed and a remaining memory area are divided, an area in which a moving image is desired to be displayed is referred to as an A bank, and an area used for composing a moving image in the remaining portion not in an image is referred to as a B bank. The horizontal / vertical start coordinates are designated at an arbitrary position in bank A for displaying the moving image. For bank B, the horizontal / vertical start point coordinates can be specified in an area that is not displayed on the screen. The lower 5 bits of the horizontal start point coordinates (in the case of 32-word configuration) are the lower 5 bits of the horizontal start point coordinates of bank A. Specify the same value. This is to align the words in the A bank and B bank when reading. FIG. 18 shows a multi-channel data processing method. In FIG. 18, the still image signal is read when the horizontal multi-window signal is H, and the moving image signal is read when the horizontal multi-window signal is L. As described above, the read data is 2-word preceding read before REN is input. Since the special data 1 shown in FIG. 18 is stored in the buffer 39c of the circuit (c) of the read data register section 12 shown in FIG. 5, the special data 1 shown in FIG. It is selected and output when H ". Further, the special data 2 is the buffer of the circuit (c) while the special data 1 is read and then the normal data (a) (b) (a) (b). Accumulated in 39c,
Like the special data 1, it is selected and output when the special data selection signal is "H". In this way, the multi-channel moving image area and the still image area are switched. In the multi-channel function as well as the two-screen function,
Although overtaking occurs, the processing method for overtaking mitigation is similar to the case of the two-screen function.

(10) Ring operation function The ring operation function is a function used when the memory capacity required for displaying one frame of image is larger than the memory capacity of the DRAM 11. FIG. 19 is a circuit for performing a ring operation, and includes an X counter 42, a Y counter 43, adders 44, 44a, and a DFF which form the write address generation unit 25 and the read address generation unit 26 shown in FIG.
The ring motion detector 56 is added to the components 45 and 46. Note that, for example, in the case of 10-bit input, the upper 5 bits of the output of the previous stage adder 44 are on the column address side and the lower 5 bits are on the row address side. FIG. 20 is a block diagram of the ring motion detection unit 56, which includes a first match detection unit 57, a second match detection unit 58,
It is composed of a first DFF 59, a second DFF 60, and an OR circuit 61. In FIG. 20, the first coincidence detection unit 57 detects that the value after the addition of the X counter 42 and the Y counter 43 coincides with the value of the last address of the DRAM 11, and the write command or read command. Is issued and a write or read operation is performed, then an address reset signal is issued by that command, and X
The counter 42 and the Y counter 43 are reset. Also,
In the second match detection unit 58, when the Y counter 43 exceeds the capacity of the DRAM 11 when it is next incremented, the address at the time of the next increment is calculated and output from the Y counter 43 in advance. When it is detected that the value exceeds the capacity, an address reset signal is issued by the next increment signal and the X counter 42
And Y counter 43 is reset. The ring operation is performed by the above two methods.

(11-1) Freeze Function (1): W
When EN is invalidated, the freeze function is a function of displaying an image at a certain time in a still state. When the freeze function selection signal is input to the frame memory circuit, the input WEN is invalidated and the data in the DRAM 11 is read out without being rewritten. Even if a freeze function selection signal is input in the middle of writing, it does not freeze in the middle of a frame, and writing is performed until the next vertical synchronization signal is input, then freezes in the next frame and the image is displayed still. In this case, DR
No signal comes from the root before AM11.

(11-2) Freeze Function (No. 2): When Disabling the Write Command When the freeze function selection signal is input to the frame memory circuit, the write command is disabled and the data in the DRAM 11 is read without rewriting. To do. Similar to (1) above, even if a freeze function selection signal is input during writing, it does not freeze in the middle of a frame, writing is performed until the next vertical synchronization signal is input, and freezes in the next frame. Display the video still. In this case, DRA
I have stopped writing to M11.

(12) One-shot writing function The one-shot writing function is a function for displaying one frame image immediately after the one-shot writing function selection signal is input while the freeze function is used. During the freeze period, WEN or write command becomes invalid,
The WEN or write command is enabled for one frame immediately after the input of the one-shot write function selection signal, and DR
One shot writing is performed by rewriting the data of AM11, and the image is displayed until the one shot writing function selection signal is input or the freeze function is released.
Similar to the freeze function selection signal, even if the one-shot write function selection signal is input during writing, the one-shot write is not performed until the vertical synchronization signal is input, and immediately after the vertical synchronization signal is input. Works in a frame.

(13) Strobe Function The strobe function is a function of dividing the display screen into a plurality of divided screens and displaying a frame-by-frame image. FIG. 21 shows an example of screen division when the strobe function is used. . To realize the strobe function, the one-shot writing function is used to rewrite the data in the memory area of the DRAM 11 corresponding to the divided screen to be displayed on the divided display screen. Therefore, set the horizontal start point coordinates, vertical start point coordinates, horizontal display width and vertical display width of the split screen you want to rewrite, and rewrite only the data in the memory area corresponding to the split screen,
All you have to do is read the data on the entire screen. On the screen corresponding to the memory area where the data has not been rewritten, the data that has been written is read and displayed. Therefore, in the example of FIG. 21, when it is desired to sequentially display frame-by-frame images from 1 to 16, the horizontal start point coordinates, vertical start point coordinates, horizontal display width, and vertical display width may be set in order from 1. If the image to be displayed is larger than the split screen, it is reduced and written in the memory area, and the same processing is performed.

(14) Fill Function The fill function is a function for erasing data within the memory writing range of the DRAM 11. This is for erasing data by inputting a GND level signal and performing read data processing without using the data from the DRAM 11 input to the read data register section 12. This function is used to display the multi-channel initial screen or the initial screen when using the flash function.

(15) VSYNC synchronization function The VSYNC synchronization function is 1 when various settings are changed.
This is a function to change the settings all at once by synchronizing with VSYNC so that the image is not disturbed in the middle of the screen.

FIG. 22 is a circuit relating to claims 1, 4, 5 and 7, wherein a write / read command mask processing section 62 is inserted between the decoder 38 of the command generating section 21 and the memory element 11. By doing so, the memory element 11
The memory access basic command cycle in 1) is alternately generated for read and write, and the read command or the write command is permitted only when necessary.

FIG. 23 is a circuit relating to claims 3, 5, 6 and 7, wherein a write control section 63 and a read control section 64 as a configuration of the frame memory control section 13 are provided in front of the memory element 11. By providing the memory element 11, the memory element 11 is provided with WRSTX (a signal issued once per frame, which initializes a write operation), WEN (a signal which permits writing to the memory), WEN.
LENDX (a signal issued once per line to indicate the end of writing), WLINCX (a signal issued once to one line and incrementing the write address by one line), RRSTX (issued once per frame to perform a read operation) Signal for initialization), REN (signal for permitting reading from memory), RLSTRX (signal issued once per line to indicate the beginning of the line), RLINCX
Data is written / read in accordance with each control signal (a signal issued once per line and incrementing the read address by one line), and WLENDX and WL
INCX, RLSTRX, and RLINX are controlled separately. As a result, complicated control such as enlargement / reduction is enabled. That is, when enlarging / reducing, there is a case where only one signal is issued for control, but the conventional control method could not perform more complicated control. However, according to the present invention, WLENDX and WLINCX are used. And RLST
By separately controlling RX and RLINX, for example,
It enables complicated control when issuing and controlling only one signal, such as enlargement / reduction.

FIG. 24 relates to claim 9. By providing the clock selection unit 65 in the preceding stage of the memory element 11, which one of the write system clock and the read system clock is supplied to the memory device 11. It constitutes a means for selecting a high frequency clock.

FIG. 25 relates to the tenth and eleventh aspects. By providing the end point processing unit 66 in the preceding stage of the memory element 11, the left end point processing is performed by using the data mask function of the memory element 11. By using the means or the data mask function of the memory element 11, the right end point processing is performed.

FIG. 26 relates to claim 12,
By providing the shift register 67 and the end point processing unit 68 in the preceding stage of the memory element 11, a means for performing the right end point processing by using the data mask function of the shift register 67 and the memory element 11 is configured.

FIG. 27 relates to claims 13 to 26. In the preceding stage of the memory device 11, the write data register section 73, X counters 421 and 422, and Y counter 43 are provided.
1, 432, adders 441, 442, a row address selector 69, a column address selector 70 are provided, and a read data register section 71 is provided at a subsequent stage of the memory element 11, thereby configuring a unit having a vertical and horizontal mirror inversion processing function. is doing.

FIG. 28 relates to the twenty-seventh and twenty-eighth aspects, and by providing the ring motion detector 72, X / Y
When the counters 42 and 43 exceed the physical memory space,
A means for returning the X / Y counters 42 and 43 to 0 or a Y counter +1 exceeds the physical memory space, and WLINCX
Or when RLINCX is detected, X / Y counter 4
Means for returning 2, 43 to 0 and means for designating or changing the write start address are arranged at arbitrary positions within the read range.

FIG. 29 relates to claims 29 to 58. The data fill processing section 7 is provided in the preceding stage of the memory element 11.
4, the VSYNC synchronization control processing unit 75, the write data register unit 73, the write control unit 63, and the read control unit 64 are provided, and the read data register unit 71 is provided in the subsequent stage of the memory element 11, so that the end point processing function and the mirror inversion are performed. Function, one-shot function, fill function,
The freeze function, the two-screen function, the function of designating / changing the write start address, and the function of synchronizing with VSYNC can be arbitrarily combined.

[0056]

Since the present invention is configured as described above,
It has the following effects. By calculating the row address and the column address at once on the scale of X / Y and distributing them, the circuit becomes simple and the memory space is not wasted. Also, WLENDX and WLINC
By separately controlling X, RLSTRX, and RLINCX, it is possible to perform complicated control in the case of issuing and controlling only one signal such as enlargement / reduction.

By selecting and supplying a clock for writing or a clock for reading as a clock to be supplied to the memory element, a circuit for supplying the memory element independently becomes unnecessary.

By utilizing the data mask function of the memory element and the shift register, writing and reading of unnecessary data can be eliminated.

When changing the write address to be displayed by the two-screen function, by setting the other address outside the display range, that is, outside the read range, operations such as forming a sequence become unnecessary, and the setting is made. Will be easier.

By synchronizing various control signals with VSYNC, there is no problem that the image is disturbed or stationary in the middle of one screen.

By combining functions such as the mirror inversion function, the one-shot function, and the two-screen function, it is possible to express various images.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a frame memory circuit according to the present invention.

FIG. 2 is a block diagram of a frame memory control unit in FIG.

FIG. 3 is a block diagram of a command generation unit in FIG.

FIG. 4 is a block diagram of a write data register unit in FIG.

5 is a block diagram of a read data register section in FIG. 1. FIG.

FIG. 6 is a configuration diagram of the DRAM in FIG.

7 is an explanatory diagram of a command cycle given to the DRAM in FIG.

FIG. 8 is a block diagram of a write / read address generation unit in FIG.

FIG. 9 is an explanatory diagram of an address map of the DRAM in FIG.

10 is a block diagram of an example of the write / read address generation unit in FIG. 2 different from that in FIG. 8;

11 is an explanatory diagram of an address map when a plurality of data in the DRAM in FIG. 1 are handled.

FIG. 12 is a block diagram of an overtaking detection unit.

FIG. 13 is an explanatory diagram for forming two screens, (a)
Is an explanatory diagram of a two-screen display image, and (b) is an explanatory diagram of an image synthesized by a sub LSI.

FIG. 14 is a block diagram of means having a two-screen configuration function.

FIG. 15 is a timing chart when the two-screen function is used.

FIG. 16 shows an example of a multi-channel display configuration,
(A) is an explanatory diagram of multi-channel display, (b) is
It is explanatory drawing of the multi-channel image to synthesize | combine.

FIG. 17 is an explanatory diagram of a memory usage example when configuring a multi-channel.

FIG. 18 is an explanatory diagram of a multi-channel data processing method.

FIG. 19 is a block diagram of an address control unit when performing a ring operation.

FIG. 20 is a block diagram of a ring motion detector.

FIG. 21 is an explanatory diagram of an example of screen division when using a flash function.

FIG. 22 is a block diagram of a circuit that permits a read or write command only when necessary.

FIG. 23: WRSTX, WEN, WLENDX, WLI
NCX, RRSTX, REN, RLSTRX, RLIN
Data is written / read according to each control signal of CX, and WLENDX, WLINCX, and RLSTRX are read.
FIG. 3 is a block diagram of a circuit for separately controlling RINX and RLINX.

FIG. 24 is a block diagram of a unit that selects a clock having a higher frequency from a write system clock and a read system clock as a clock supplied to the memory element 11.

FIG. 25 is a block diagram of a means for performing the left end point processing by using the data mask function of the memory element 11 or a means for performing the right end point processing by using the data mask function of the memory element 11.

FIG. 26 is a block diagram of means for performing right end point processing using the shift register 67 and the data mask function of the memory element 11.

FIG. 27 is a block diagram of means having vertical and horizontal mirror inversion processing functions.

FIG. 28: Means for returning the X / Y counters 42, 43 to 0 when the X / Y counters 42, 43 exceed the physical memory space, or Y counter +1 exceeds the physical memory space and detects LINX. When the X / Y counter 42,
4 is a block diagram of a unit for returning 43 to 0 and a unit for designating or changing a write start address at an arbitrary position within a read range. FIG.

FIG. 29 is a circuit that arbitrarily combines each function of an end point processing function, a mirror inversion function, a one-shot function, a fill function, a freeze function, a two-screen function, a function of designating / changing a write start address, and a function of synchronizing with VSYNC. It is a block diagram of.

FIG. 30 is an explanatory diagram of an example in which the horizontal mirror inversion processing function is different.

[Explanation of symbols]

10 ... Write data register section, 11 ... DRAM, 12
... Read data register section, 13 ... Frame memory control section, 21 ... Command generating section, 22 ... Overtaking detecting section, 23 ... Write command generating section, 24 ... Read command generating section, 25 ... Write address generating section, 26 ... Read address Generation unit, 27 ... Write / read address selection unit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Toru Aida             1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Stock             Within the company Fujitsu General F-term (reference) 5C052 AA17 CC05 GA03 GA07 GC04                       GD01 GD05 GD09 GE01 GE04                       GE07 GF02 GF03 GF05                 5M024 AA55 AA84 AA90 BB07 BB23                       BB27 BB35 BB36 DD85 EE17                       KK07 KK13 KK15 KK24 KK28                       KK29 KK30 LL01 PP01 PP07                       PP10

Claims (58)

[Claims] 1. A DRAM of command control type, which specifies an access word by a row address and a column address.
A frame memory circuit characterized in that a memory element consisting of a memory element is used, and a memory access basic command cycle in this memory element is alternately generated for read and write, and a read command or a write command is permitted only when necessary. . 2. A DRAM of command control type, which specifies an access word by a row address and a column address.
The memory element is used to sequentially increase the write / read counter in the row direction, increment the column when the maximum value of the memory element is exceeded, and return the row to the minimum value. Times DRAM
The frame memory circuit is characterized in that the refresh cycle is eliminated by circulating the address of. 3. A DRAM of command control type, which specifies an access word by a row address and a column address.
The memory element is composed of WRSTX (a signal that is issued once per frame and that initializes a write operation), WEN (a signal that allows writing to the memory), and WLENDX (1 line). , A signal indicating the end of writing), WLINCX (a signal issued once per line and incrementing the write address by one line), RRSTX (a signal issued once per frame to initialize the read operation) ), REN (a signal that permits reading from the memory), RLSTRX (a signal that is issued once per line to indicate the beginning of the line), RLINCX (a signal that is issued once per line and increments the read address by one line). Data is written / read according to each control signal of
NDX and WLINX and RLSTRX and RLINX
A frame memory circuit characterized in that and are controlled separately. 4. A DRAM of command control type, which specifies an access word by a row address and a column address.
A memory element consisting of is used, the memory access basic command cycle in this memory element is alternately generated for read / write, the read command or write command is permitted only when necessary, and the write / read counter is set in the row direction. When the maximum value of the memory element is exceeded, the column is incremented, and the row is returned to the minimum value.
A frame memory circuit characterized by eliminating refresh cycles by circulating M addresses. 5. A DRAM of command control type, which specifies an access word by a row address and a column address.
A memory element comprising a memory access basic command cycle in which a read command and a write command are alternately generated, a read command or a write command is permitted only when necessary, and the memory element is WRSTX (1 A signal that is issued once per frame, which initializes the write operation), WEN (a signal that allows writing to the memory), WLENDX (a signal that is issued once per line and indicates the end of writing), WLINCX (1 A signal that is issued once to a line and that increments the write address by one line), RRSTX (a signal that is issued once per frame to initialize the read operation), REN (a signal that permits reading from memory), RLSTRX ( Signal that is issued once per line and indicates the beginning of the line), RLIN X (issued once a line, the signal for one line increment the read address) performs writing and reading of data in accordance with the control signal, the WLE
NDX and WLINX and RLSTRX and RLINX
A frame memory circuit characterized in that and are controlled separately. 6. A command control type DRAM for designating an access word by a row address and a column address.
The memory element is used to sequentially increase the write / read counter in the row direction, increment the column when the maximum value of the memory element is exceeded, and return the row to the minimum value. Times DRAM
The refresh cycle is eliminated by circulating the addresses of WRSTX (a signal that is issued once in one frame to initialize the write operation) and WEN (write is permitted in the memory). Signal), WLENDX (a signal that is issued once for one line to indicate the end of writing), WLINCX (a signal that is issued once for one line and increments the write address by one line), RRSTX (is issued once for one frame, A signal that initializes the read operation), REN (a signal that permits reading from the memory), RLSTRX (a signal that is issued once per line to indicate the beginning of the line), and RLINCX (which is issued once per line and is read Write data according to each control signal (address increment signal by 1 line) It reads, the WLE
NDX and WLINX and RLSTRX and RLINX
A frame memory circuit characterized in that and are controlled separately. 7. A command control type DRAM for designating an access word by a row address and a column address.
The memory element consisting of is used, the memory access basic command cycle in this memory element is alternately generated for read and write, the read command or the write command is permitted only when necessary, and the write / read counter is set in the row direction. When the maximum value of the memory element is exceeded, the column is incremented, and the row is returned to the minimum value.
By repeating the M address, the refresh cycle is eliminated, and further, this memory device has WRSTX (a signal that is issued once in one frame and that initializes the write operation), WEN (write is permitted in the memory). Signal), WLENDX (a signal issued once per line to indicate the end of writing), WLINCX (a signal issued once per line and incrementing the write address by one line), RRSTX (issued once per frame) , A signal that initializes the read operation), REN (a signal that permits reading from the memory), RLSTRX (a signal that is issued once per line and represents the beginning of the line), RLINCX (which is issued once per line, Write data according to each control signal (signal that increments the read address by one line) Performed only and reading, the WLE
NDX and WLINX and RLSTRX and RLINX
A frame memory circuit characterized in that and are controlled separately. 8. An X / Y counter is used for calculation, which is assigned to a row address and a column address. This assignment specifies the number of write words for one line in advance, and the Y counter 43 sets a write word for one line. Means for adding numbers, means for preliminarily designating the number of write words for one line, and means for multiplying the Y counter 43 and the number of write words for one line at the time of address conversion, predesignating the number of write pixels for one line, and one line The Y counter 43 calculates the number of write words of 1 line, and the Y counter 43 adds the number of write words of 1 line, or specifies the number of write pixels of 1 line in advance, calculates the number of write words of 1 line, and When Y
A counter 43 and means for multiplying the number of write words of one line by means of multiplying the number of write words of one line.
The frame memory circuit described in 5, 6, or 7. 9. The frame memory circuit according to claim 8, further comprising means for selecting a clock having a higher frequency from a write system clock and a read system clock as a clock supplied to the memory element. . 10. The frame memory circuit according to claim 8, further comprising means for performing a left end point processing by using a data mask function of the memory element. 11. The frame memory circuit according to claim 8, further comprising means for performing a right end point processing by using a data mask function of the memory element. 12. The frame memory circuit according to claim 8, further comprising means for performing a right end point processing by using a data mask function of the shift register and the memory element. 13. When writing, data in the line direction of one frame is rearranged vertically and written in the memory 11,
9. The frame memory circuit according to claim 8, further comprising means for performing a vertical mirror inversion process by performing reading from a written head in a forward direction. 14. A means for performing a vertical mirror inversion process by performing writing from the head of input data to the memory 11 in a forward direction and reading from the data of the lowest line of one frame in a reverse direction at the time of reading. 9. The frame memory circuit according to claim 8, further comprising: 15. When writing, the word arrangement of one line and the data arrangement within the word are both inverted in the opposite direction and written into the memory 11, and reading is performed from the beginning of the writing in the forward direction, and the horizontal reading is performed. 9. The frame memory circuit according to claim 8, further comprising means for performing mirror inversion processing. 16. When writing, the arrangement of data in a word is left unchanged, and only the arrangement of words in one line is reversed in the opposite direction to write to the memory 11 and read out.
The sequence of data in the written word is in the reverse direction, and
9. The frame memory circuit according to claim 8, further comprising means for performing a horizontal mirror inversion process by arranging words on one line in a forward direction. 17. When writing, the word arrangement of one line is left as it is, and only the data arrangement within the word is inverted in the opposite direction for writing and reading in the memory 11.
Reverse the written word sequence of one line, and
9. The frame memory circuit according to claim 8, further comprising means for performing a horizontal mirror inversion process by arranging data in a word in a forward direction. 18. Writing is performed in the memory 11 in the forward direction from the beginning of input data, and reading is performed by inverting both the written 1-line word sequence and the written data sequence in the reverse direction, 9. The frame memory circuit according to claim 8, further comprising means for performing horizontal mirror inversion processing. 19. When writing, the data in the line direction of one frame is rearranged vertically and written in the memory 11.
For reading, a means for performing a vertical mirror inversion process by going in the forward direction from the beginning of writing, and for writing, inverting the arrangement of words on one line and the arrangement of data in words in the opposite direction to the memory 11 9. A means for performing writing and reading in the forward direction from the beginning of writing and performing a horizontal mirror inversion process is provided.
Frame memory circuit described. 20. When writing, the data in the line direction of one frame is rearranged vertically and written in the memory 11.
For reading, the means for performing the vertical mirror inversion process by going forward from the beginning of writing, and for writing, the arrangement of the data in the word is left unchanged and only the arrangement of the words of one line is reversed in the opposite direction. For writing and reading in the memory 11, the arrangement of the data in the written word is performed in the reverse direction, and the arrangement of the words of one line is performed in the forward direction.
9. The frame memory circuit according to claim 8, further comprising means for performing a horizontal mirror inversion process. 21. A means for performing writing in the memory 11 in the forward direction from the beginning of input data, and in reading, performing the vertical mirror inversion processing by performing in the reverse direction from the written data of the lowermost line of one frame. When writing,
Both the arrangement of the words on one line and the arrangement of the data within the words are reversed in the opposite direction, and written into the memory 11, and reading and writing are performed in the forward direction from the written head to perform horizontal mirror inversion processing. 9. The frame memory circuit according to claim 8, wherein: 22. A means for performing writing from the beginning of input data to the memory 11 in the forward direction, and performing reading from the data of the lowest line of one frame written in the reverse direction to perform vertical mirror inversion processing. When writing,
With the arrangement of the data in the word as it is, only the arrangement of the words on one line is inverted in the opposite direction and written into the memory 11, and the reading is performed by reversing the arrangement of the data in the written word in the opposite direction and 9. The frame memory circuit according to claim 8, further comprising means for performing a horizontal mirror inversion process by arranging words in a forward direction. 23. When writing, data in the line direction of one frame is rearranged vertically and written in the memory 11,
For reading, the means for performing the vertical mirror inversion process by going forward from the beginning of writing, and for writing, the word arrangement of one line is left unchanged and only the data arrangement within the word is reversed in the opposite direction. To write and read data in the memory 11, the written 1-line words are arranged in the reverse direction, and the data in the words are arranged in the forward direction.
9. The frame memory circuit according to claim 8, further comprising means for performing a horizontal mirror inversion process. 24. When writing, the data in the line direction of one frame is rearranged vertically and written in the memory 11,
Reading is performed in the forward direction from the written head to perform vertical mirror inversion processing. Writing is performed in the memory 11 in the forward direction from the head of the input data. Read is performed in the word sequence of the written one line and the word. 9. The frame memory circuit according to claim 8, further comprising means for performing a horizontal mirror inversion process by inverting both of the data in the column in the opposite direction. 25. A means for performing writing in the memory 11 in the forward direction from the beginning of the input data, and in reading, performing the vertical mirror inversion processing by performing in the reverse direction from the written data of the lowermost line of one frame. When writing,
With the arrangement of words on one line unchanged, only the arrangement of data within the word is inverted in the opposite direction and written to the memory 11, and reading is performed by reversing the arrangement of the written one-line words and within the word. 9. The frame memory circuit according to claim 8, further comprising means for performing a horizontal mirror inversion process by arranging data in a forward direction. 26. A means for performing writing in the memory 11 in a forward direction from the beginning of input data, and in reading, performing a vertical mirror inversion process by performing in a reverse direction from the written lowermost line data of one frame. Then, writing is performed in the memory 11 in the forward direction from the beginning of the input data, and reading is performed by inverting the written one-line word arrangement and the data arrangement within the word in the opposite direction, and then performing horizontal mirror inversion. 9. The frame memory circuit according to claim 8, further comprising a processing unit. 27. Means for returning the X / Y counter to 0 when the X / Y counter exceeds the physical memory space, or Y counter + 1 exceeds the physical memory space, and WLINC.
9. A means for returning the X / Y counter to 0 when X or RLINX is detected.
Frame memory circuit described. 28. A write start address can be specified or changed at any position within the read range, and VS
9. The frame memory circuit according to claim 8, further comprising means for synchronizing the designation or change of the write start address with YNC. 29. A device having a function for validating the write control for only one frame and comprising means for synchronizing a signal for validating the write control for only one frame in VSYNC. 8. The frame memory circuit described in 8. 30. The frame memory circuit according to claim 8, further comprising means having a function of validating the WEN signal for only one frame. 31. The frame memory circuit according to claim 8, further comprising means having a function of validating the write command signal for only one frame. 32. The frame memory according to claim 8, further comprising means having a fill function of writing and erasing arbitrary fixed data without using the data held in the memory element. circuit. 33. The frame memory circuit according to claim 8, further comprising means having a function of invalidating write control in the memory element. 34. The frame memory circuit according to claim 8, further comprising means having a function of invalidating a WEN signal as write control in the memory element. 35. The frame memory circuit according to claim 8, further comprising means having a function of invalidating a write command signal in the memory element. 36. The memory device has two write addresses, one of which is set at a display position and the other of which is set outside the display range, and data is written alternately for each frame, and data is read from the address designated by the overtaking control signal. 9. The frame memory circuit according to claim 8, further comprising means having a dual screen function. 37. A means having an end point processing function for performing a left end and / or a right end point processing by using a data mask function of a memory device, and a means having a vertical and / or horizontal mirror inversion processing function. 9. The frame memory circuit according to claim 8, wherein: 38. A means having an end point processing function for performing end point processing at the left end and / or the right end using a data mask function of a memory device, and a one-shot function for validating a write control or a write command signal for only one frame. 9. A means for having the same is provided, and the one-shot write control signal is synchronized with VSYNC.
Frame memory circuit described. 39. Means having an end point processing function for performing end point processing at the left end and / or right end using a data mask function of a memory device, and a fill function for erasing retained data by writing arbitrary fixed data. 9. The frame memory circuit according to claim 8, further comprising: 40. A means having an end point processing function for performing end point processing at the left end and / or the right end using a data mask function of a memory element, and a means having a freeze function for invalidating a write control or a write command signal. Equipped, VS
9. The frame memory circuit according to claim 8, wherein the freeze control signal is synchronized with YNC. 41. A means having an end point processing function for performing end point processing at the left end and / or the right end by using a data mask function of a memory element and two write addresses, one of which is displayed at the other display position. 9. The frame memory circuit according to claim 8, further comprising means having a two-screen function which is set outside the range, is alternately written for each frame, and reads data from an address designated by the overtaking control signal. 42. Means having a vertical and / or horizontal mirror reversal processing function in a memory element, and means having a function of designating or changing a write start address at an arbitrary position within a read range. And VS
9. The frame memory circuit according to claim 8, wherein the YNC synchronizes the mirror inversion control signal with the write start address designation / change. 43. Means for providing a vertical and / or horizontal mirror inversion function in a memory device, and means for having a one-shot function for validating a write control signal or a write command signal for only one frame, and mirroring at VSYNC 9. The frame memory circuit according to claim 8, wherein the inversion control signal and the one-shot write control signal are synchronized with each other. 44. A memory device is provided with means having a vertical and / or horizontal mirror reversal processing function, and means having a fill function of erasing retained data by writing arbitrary fixed data. 9. The frame memory circuit according to claim 8. 45. Means for providing a vertical and / or horizontal mirror inversion processing function in a memory device, and means for having a freeze function for invalidating a write control or write command signal, and a mirror inversion control signal for VSYNC. 9. The frame memory circuit according to claim 8, wherein the frame memory circuit is synchronized with a freeze control signal. 46. Means having a vertical and / or horizontal mirror reversal processing function in a memory device and two write addresses, one of which is set at a display position and the other of which is set outside the display range, and alternated for each frame. And a means having a two-screen function for reading data from an address designated by a write / overtaking control signal, and the VSYNC is used to synchronize the mirror inversion control signal with the write start address designation / change. The frame memory circuit according to claim 8. 47. Means having a one-shot function for validating write control or write command signal for only one frame in a memory element, and means for having a fill function for erasing the held data by writing arbitrary fixed data. 9. The frame memory circuit according to claim 8, further comprising: a one-shot write control signal synchronized with VSYNC. 48. A device having a fill function for writing and erasing data held in a memory device by writing arbitrary fixed data, and a device having a freeze function for invalidating a write control or a write command signal, V
9. The frame memory circuit according to claim 8, wherein the freeze control signal is synchronized with SYNC. 49. Means having an end point processing function for performing left end and / or right end point processing using a data mask function of a memory device, means having a vertical and / or horizontal mirror inversion processing function, and one frame 9. A means having a one-shot function for validating only a write control or a write command signal is provided, and the mirror inversion control signal and the one-shot write control signal are synchronized with VSYNC. Frame memory circuit. 50. Means having an end point processing function for performing end point processing of the left end and / or right end using the data mask function of the memory device, and means having a vertical and / or horizontal mirror inversion processing function. 9. The frame memory circuit according to claim 8, further comprising: a means having a fill function for erasing the existing data by writing arbitrary fixed data, and synchronizing the mirror inversion control signal with VSYNC. 51. Means having an end point processing function for performing left end and / or right end point processing using a data mask function of a memory element, means having a vertical and / or horizontal mirror inversion processing function, and write control. Or a means having a freeze function for invalidating the write command signal,
9. The frame memory circuit according to claim 8, wherein the mirror inversion control signal and the freeze control signal are synchronized with each other by VSYNC. 52. A unit having an end point processing function for performing end point processing at the left end and / or the right end using a data mask function of a memory device, a unit having a vertical and / or horizontal mirror inversion processing function, and one frame. Only a write control or a means having a one-shot function for validating a write command signal and a means for having a fill function for writing and erasing the held data by writing arbitrary fixed data are provided, and a mirror inversion control signal is provided by VSYNC. 9. The frame memory circuit according to claim 8, wherein the one-shot write control signal and the one-shot write control signal are synchronized with each other. 53. Means having an end point processing function for performing left end and / or right end point processing using the data mask function of the memory device, and means having a vertical and / or horizontal mirror inversion processing function are held. It has a means for having a fill function for erasing the fixed data by writing arbitrary fixed data and a means for having a freeze function for invalidating the write control or write command signal, and the mirror inversion control signal and the freeze control signal by VSYNC. 9. The frame memory circuit according to claim 8, wherein the frame memory circuit is synchronized with. 54. Means having an end point processing function for performing left end and / or right end point processing by using a data mask function of a memory element, means having a vertical and / or horizontal mirror inversion processing function, and one frame Only a write control or a means having a one-shot function for validating a write command signal and two write addresses are provided, one of which is set at a display position and the other of which is set outside the display range, and writing is alternately performed for each frame to control overtaking. Means for reading data from an address designated by a signal, and a means for synchronizing a mirror inversion control signal, a one-shot write control signal, and a write start address designation / change with VSYNC. 9. The frame memory circuit according to claim 8, which is characterized in that 55. Means having an end point processing function for performing end point processing of the left end and / or right end by using a data mask function of a memory device, and means having a vertical and / or horizontal mirror inversion processing function are held. Means that has a fill function that erases the existing data by writing any fixed data, and has two write addresses, set one to the display position and the other to the outside of the display range, and alternately write and pass each frame. Means for reading data from an address designated by the control signal and having a two-screen function.
9. The frame memory circuit according to claim 8, wherein the YNC synchronizes the mirror inversion control signal with the write start address designation / change. 56. Means having an end point processing function for performing end point processing at the left end and / or right end using a data mask function of a memory element, means for having a vertical and / or horizontal mirror inversion processing function, and write control Alternatively, a means having a freeze function for invalidating the write command signal and two write addresses are provided, one of which is set at a display position and the other of which is set outside the display range, and writing is alternately performed for each frame, and the overtaking control signal instructs 9. A means having a two-screen function for reading data from a different address is provided, and VSYNC synchronizes the mirror inversion control signal, the freeze control signal, and the write start address designation / change. Frame memory circuit described. 57. Means having an end point processing function for performing end point processing at the left end and / or right end using the data masking function of the memory device; means having a vertical and / or horizontal mirror inversion processing function; and one frame Only, a means having a one-shot function for validating a write control or a write command signal, a means for having a fill function for writing and erasing held data by writing arbitrary fixed data, and two write addresses, one of which is provided At the display position, the other is set outside the display range, alternately written for each frame, and a means having a two-screen function of reading data from the address designated by the overtaking control signal is provided. It is characterized in that the one-shot write control signal and the write start address designation / change are synchronized. The frame memory circuit according to claim 8. 58. Means having an end point processing function for performing end point processing at the left end and / or right end using the data mask function of the memory element, and means having a vertical and / or horizontal mirror inversion processing function are held. That has a fill function to write the fixed data to erase it by writing any fixed data, a means to have a freeze function to invalidate the write control or write command signal, and two write addresses, one at the position to display , A means for setting the other to outside the display range, writing alternately for each frame, and reading data from the address designated by the overtaking control signal, and a mirror inversion control signal and a freeze control signal by VSYNC. 9. The frame memory circuit according to claim 8, wherein the writing start address designation / change is synchronized. Road.