JPH04326770A - Thin film transistor - Google Patents

Abstract

PURPOSE:To eliminate a special stopper in the case of etching, to reduce photomasks to be used, and to simplify a photoprocessing step by incorporating selectivity of etching in a semiconductor film 5. CONSTITUTION:A thin film transistor in which gate electrode 2, a gate insulating film 4 and a semiconductor film 5 are sequentially formed on an insulating board 1, and a source electrode and a drain electrode 7 are formed on the film 5, a region 5a containing hydrogen in a high concentration is formed in the film 5.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor, and more particularly to a thin film transistor whose manufacturing process is simplified.

0002

[Prior art and its problems] Conventionally, thin film transistors used in active matrix liquid crystal display devices, etc. have two types in which the transparent conductive film serving as the pixel electrode is located above the transistor, and one in which the transparent conductive film serving as the pixel electrode is located below the transistor. There are two types of wafers, each manufactured by the method shown in FIGS. 5 and 6.

That is, in the case where the pixel electrode is located below the transistor as shown in FIG.
As shown in a), an indium tin oxide (ITO) layer 22 that will become a pixel electrode is formed on an insulating substrate 21 made of glass or the like.
and a chromium (Cr) layer 23 that will become a gate electrode are formed by vacuum evaporation, sputtering, etc.
is formed into a predetermined pattern using an etching method or the like. Next, as shown in the same figure (b), indium tin oxide layer 2
2 is formed into a predetermined pattern by etching or the like. Next, as shown in the same figure (c), a tantalum oxide layer (TaOX) 24 and a silicon nitride layer (Six Ny) 25 that will become a gate insulating film, a non-doped semiconductor layer 26 that will become a channel region, and an etching stopper are formed. A silicon nitride layer 27 is formed. Next, as shown in FIG. 2D, the silicon nitride film 27 is formed into a predetermined pattern by etching or the like so that it remains only on the gate insulating film 23. Next, as shown in the same figure (e),
An n+ type semiconductor layer 28 is formed to make ohmic contact with the electrode. Next, as shown in FIG. 2F, a contact hole 29 is formed on the side of the transistor by, for example, an etching method. Next, as shown in FIG. 4G, a molybdenum silicide (MoSi) layer 30 and an aluminum layer 31, which will become source and drain electrodes, are formed by vacuum evaporation or sputtering. Next, as shown in the figure (h), the aluminum layer 31 on the gate electrode 23,
An ohmic contact layer is formed by removing and separating the molybdenum silicide layer 30 and the n+ type semiconductor layer 28 by an etching method using an aqueous solution of hydrogen fluoride and nitric acid. During this etching, the silicon nitride film 27 serves as an etching stopper. Finally, a passivation film 32 made of silicon nitride or the like is formed to complete the process. In the method for manufacturing a thin film transistor described above, (a) of FIG.
Since etching is performed in each step of (b), (d), (f), and (h), five photomasks are required.

In addition, in the case where the pixel electrode is located above the transistor as shown in FIG. 6, first, as shown in FIG. ) A film 52 is formed and formed into a predetermined pattern by etching or the like. Next, the same figure (b)
As shown in the figure, the surface of the tantalum film 52 is anodized,
A tantalum oxide (TaOx) film 53 is formed. next,
As shown in FIG. 4C, a first insulating film 54 made of silicon nitride or the like, a non-doped semiconductor film 55 serving as a channel region, and a second insulating film 56 made of silicon nitride or the like are formed. The first insulating film 54 becomes a gate insulating film, and the second insulating film 56 becomes an etching stopper layer. Next, as shown in FIG. 5D, the second insulating film 56 is deposited so that the second insulating film 56 remains only on the gate electrode 52.
6 is etched away. Next, as shown in FIG. 5(e), an n+ type semiconductor layer 57 is formed for making ohmic contact with the electrode. Next, the same figure (f)
As shown in FIG. 3, the peripheral portions of the n+ type semiconductor layer 57 and the non-doped semiconductor layer 55 are removed by etching or the like. Next, as shown in FIG. 6G, a metal film 58 made of titanium (Ti) or the like, which will serve as source/drain electrodes, is formed and patterned by etching or the like. In addition, in this step, the transparent conductive film 59 described later is the semiconductor layer 55,
57, the semiconductor layers 55, 5
The metal film 58 is patterned so that the peripheral portion of the metal film 58 made of titanium is completely covered with the metal film 58 made of titanium. Next, as shown in FIG. 6(h), a transparent conductive film 59 that will become a pixel electrode is formed and patterned by an etching method. Finally, as shown in FIG. 6(i), a passivation film 60 made of a silicon nitride film or the like is formed to complete the process. In the method for forming a thin film transistor shown in FIG.
) (f) (g) (h) A photomask is required for each step.

[0005] In the conventional manufacturing process of thin film transistors, the reason why an etching stopper layer made of a silicon nitride film or the like is provided is to protect the non-doped semiconductor layer from being lost due to over-etching and to protect the n+ type semiconductor layer from being lost due to over-etching. This is to completely remove the layer and increase the OFF resistance.

[0006] As described above, the conventional thin film transistor manufacturing method uses a large number of photomasks, so the photo process takes time and has a problem of poor mass productivity.

[0007]

[Structure of the Invention] The present invention was devised in view of the above-mentioned problems, and includes sequentially forming a gate electrode, a gate insulating film, and a semiconductor film on an insulating substrate, and also forming a gate electrode, a gate insulating film, and a semiconductor film on this semiconductor film. A thin film transistor having a source electrode and a drain electrode formed therein is provided, wherein the semiconductor film has a region containing hydrogen at a high concentration.

[0008]

[Operation] According to the present invention, since the semiconductor film has a region containing hydrogen at a high concentration, the etching rate can be made different within the semiconductor film, and therefore it is not necessary to provide a stopper layer during etching. Therefore, it is possible to provide a thin film transistor with a simplified photo process.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a sectional view showing a thin film transistor according to the present invention, and 1 is an insulating substrate made of glass or the like.

A gate electrode 2 is formed on the insulating substrate 1, and a tantalum oxide film (
TaOx ) 3 and silicon nitride film (Six Ny ) 4
and a non-doped semiconductor film 5.
are stacked in sequence. On this non-doped semiconductor layer 5, source/drain electrodes 7 are formed separately, and between the source/drain electrodes 7 and the semiconductor layer 5 is an n+ type semiconductor layer 6 for establishing ohmic contact. is provided. Note that the gate insulating films 3 and 4 may have a single layer structure of the silicon nitride film 4.

The semiconductor film 5 contains, for example, 2
A region 5a containing hydrogen at 5 vol% or more is provided. That is, the semiconductor layer 5 is formed by the plasma CVD method while maintaining the substrate temperature at around 200°C, but when monosilane (SiH4) is used as the source gas, the semiconductor layer contains around 15 vol% hydrogen. I will do it. On the other hand, disilane (Si2 H6) is used as a raw material gas.
When using , the growth rate becomes high and the amount of hydrogen in the film can be increased. Specifically, depending on conditions such as growth rate, gas flow rate ratio, substrate temperature, etc.
It is possible to vary it in the range of ~50%.

FIG. 2 shows the relationship between the hydrogen content in the semiconductor film and the etching rate. Figure 2 shows hydrofluoric acid (HF): nitric acid (HNO3): acetic acid (CH3 COOH) = 1:10.
: Etching rate (Å/s) using x etching solution
), and the line marked with ● in the figure shows the etching rate of a semiconductor film with a hydrogen content of 15 to 20 vol%, and the line marked □ in the figure shows the etching rate of a semiconductor film with a hydrogen content of 30 to 50 vol%. shows the etching rate. in this way,
It can be seen that the etching rate varies depending on the combination of the hydrogen content in the semiconductor film and the composition of the etching solution (particularly the composition ratio x of acetic acid), and that selectivity in etching the semiconductor layer can be obtained. That is, the region 5a containing hydrogen at a high concentration
shows strong resistance to a mixed solution of hydrofluoric acid, nitric acid, and acetic acid, and has high etching selectivity with respect to other regions of the semiconductor film 5. In particular, remarkable selectivity can be obtained when the composition ratio x of acetic acid is set to 4 or more.

Therefore, in the present invention, as shown in FIG. 3A, when forming the non-doped semiconductor film 5, for example, monosilane is used as the raw material gas to a thickness of about 400 Å, and then it is changed to disilane and deposited to a thickness of 100 Å. Then, a region 5a containing hydrogen at a high concentration is formed, and then an n+ type semiconductor layer 6 containing about 0.5% phosphorus is formed using monosilane and phosphine (PH3) serving as an n type impurity. Further, as shown in FIG. 3(b), the non-doped semiconductor film 5
When forming by plasma CVD method, monosilane is used up to about 200 Å, then gradually switched to disilane, and
After about 100 Å, a region 5a containing hydrogen at a high concentration is formed by completely using disilane, and then an n+ type semiconductor layer 6 is formed using monosilane and phosphine, which becomes an n-type impurity.
form. Further, as shown in FIG. 3(c), disilane is used in a region of about 300 to 400 Å in the non-doped semiconductor layer 5, and silane is used in other parts to form a region 5a containing hydrogen at a high concentration, and then Monosilane and n
An n+ type semiconductor layer 6 is formed using phosphine as a type impurity.

With any of the above methods, etching selectivity can be obtained between the non-doped semiconductor film 5 and the n+ type semiconductor layer 6 or within the non-doped semiconductor layer 5, and the region 5a containing hydrogen at a high concentration can be etched. It can function as an etching stopper layer. Next, a method for manufacturing the above-mentioned thin film transistor will be explained based on FIG. 4.

First, as shown in FIG. 2A, a metal film 2 that will become a gate electrode is formed to a thickness of about 2000 Å by vacuum evaporation or sputtering, and then patterned by etching or the like. As this metal film 2, aluminum (Al), chromium (Cr), tantalum (Ta), etc. are suitably used. Further, as the etching solution, phosphoric acid is preferably used when etching aluminum, a ceric ammonium nitrate aqueous solution is suitably used when etching chromium, and fluoronitric acid is suitably used when etching tantalum.

Next, as shown in FIG. 3(b), a tantalum oxide film 3, a silicon nitride film 4 serving as a gate insulating film, a non-doped semiconductor layer 5 serving as a channel region, an n+ type semiconductor layer 6, and a source/drain Titanium (Ti) that becomes the electrode
), etc., are sequentially laminated.

The tantalum oxide film 3 is made to a thickness of about 2000 Å by, for example, an anodic oxidation method, the silicon nitride film 6 is made to a thickness of about 2000 Å by, for example, a plasma CVD method, and the non-doped semiconductor layer 5 is made to a thickness of 500 Å by, for example, a plasma CVD method.
For example, the n+ type semiconductor layer 6 is coated with plasma C to a thickness of about 00 Å.
The source/drain electrode layer 7 is formed to a thickness of about 1000 Å by VD or the like, and the source/drain electrode layer 7 is formed to a thickness of about 4000 Å by vacuum evaporation or sputtering.

Next, as shown in FIG. 2C, the metal layer 7, the n+ type semiconductor layer 6, and the non-doped semiconductor layer 5 around the upper part of the gate electrode 2 are removed by etching. In this case, an etching solution such as fluoronitric acid is used.

Next, as shown in FIG. 4(d), a transparent conductive film 8 made of tin oxide or the like is formed to a thickness of about 1000 Å by sputtering.

Next, as shown in FIG. 1, the transparent conductive film 8, the metal layer 7, and the n+ type semiconductor layer 6 are formed on the gate electrode 2.
Remove by etching. When etching the transparent conductive film 8, for example, a salt-nitric acid-based etching solution is used using zinc as a catalyst, and when etching the metal layer 7 and the n+ type semiconductor layer 6, for example, hydrofluoric acid (HF), nitric acid (HNO3),
An etching solution made of a mixed solution of acetic acid (CH3 COOH) or the like is used.

In this case, since a region 5a containing hydrogen at a high concentration is provided near the top of the non-doped semiconductor layer 5, this region 5a acts as a stopper during etching.

Finally, a passivation film 10 made of a silicon nitride film or the like as shown in FIG. 1 is formed to complete the thin film transistor.

[0023]

As described above, according to the thin film transistor of the present invention, a gate electrode, a gate insulating film, and a semiconductor film are sequentially formed on an insulating substrate, and a source electrode and a drain electrode are formed on this semiconductor film. In the formed thin film transistor, since the semiconductor film has a region containing hydrogen at a high concentration, the etching rate can be varied within the semiconductor film, and there is no need to provide a special stopper layer during etching. A thin film transistor with a simplified photo process can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a thin film transistor according to the present invention.

[Figure 2] Diagram for explaining differences in etching rate of semiconductor layers due to differences in hydrogen content

FIG. 3 is a diagram for explaining how to incorporate hydrogen into the semiconductor layer of the present invention.

FIG. 4 is a diagram for explaining the method for manufacturing a thin film transistor according to the present invention.

[Figure 5] Diagram for explaining the manufacturing process of conventional thin film transistors

[Figure 6] Diagram for explaining the manufacturing process of another conventional thin film transistor

[Explanation of symbols]

1: Insulating substrate 2: Gate electrode 4: Gate insulating film 5: Semiconductor layer 5a: Region containing hydrogen at high concentration 7: Source/drain electrode

Claims (1)

[Claims] 1. A thin film transistor in which a gate electrode, a gate insulating film, and a semiconductor film are sequentially formed on an insulating substrate, and a source electrode and a drain electrode are formed on the semiconductor film, in which the semiconductor film contains hydrogen at a high concentration. A thin film transistor characterized by having a region containing