KR100483526B1 - Thin film transistor and its manufacturing method - Google Patents

Abstract

The present invention relates to a thin film transistor and a method of manufacturing the same, wherein a contact layer in contact with an aluminum alloy film is formed of a microcrystalline silicon layer to form a source and drain electrode as a single film having a low resistance and to prevent spike phenomenon. In addition, since the contact characteristics between the aluminum alloy film and ITO are not good, an aluminum-silicon alloy film is added between the aluminum alloy film and the ITO film.

Description

Thin film transistor and method of manufacturing the same

The present invention relates to a thin film transistor, and more particularly, to a thin film transistor using aluminum (Al) or an aluminum alloy (Al alloy).

In general, since the wiring of the liquid crystal display device is used as a means for transmitting a signal, it is required to suppress signal delay and disconnection.

In general, in order to cope with high definition and large area of a thin film transistor liquid crystal display, it is an important problem to form a wiring and a thin film transistor using a low resistance metal.

The most used metals to date include aluminum (Al), aluminum alloy (Al alloy), chromium (Cr), molybdenum (Mo), molybdenum alloy (Mo alloy), titanium (Ti), tantalum (Ta), and the like. It is common to use aluminum or aluminum alloy which has the lowest specific resistance among these.

However, in the case of using aluminum (Al) or aluminum alloy (Al alloy), a hillock phenomenon in which crystal grows appears. In addition, when there is contact with indium tin oxide (ITO) as in a liquid crystal display, a battery effect may occur due to the ITO etchant, or a spike may occur when contacted with an amorphous silicon layer. A protective metal film is formed on top or bottom of aluminum or aluminum alloy.

Next, a structure of a thin film transistor according to the related art will be described with reference to the accompanying drawings.

1 is a cross-sectional view showing the structure of a thin film transistor according to the prior art.

As shown in FIG. 1, in the conventional thin film transistor, a gate electrode 2 made of an aluminum alloy (Al-Nd) film and a gate insulating film 3 covering the gate electrode 2 are formed on the substrate 1. have. A semiconductor layer 4 made of an amorphous silicon layer and a contact layer 5 made of doped amorphous silicon are sequentially formed on the gate insulating film 3. The contact layer 5 is divided into two parts at a portion corresponding to the gate electrode 2, and a source and drain electrode made of an aluminum film or an aluminum alloy film on each of the contact layer 5 and the gate insulating film 3. (7, 8) are formed one by one. A protective film 11 is formed on the substrate 1 to cover the source and drain electrodes 7 and 8 and has an opening 9 on the drain electrode 8. The pixel electrode 12 connected to the drain electrode 8 through the opening 9 is formed on the passivation layer 11.

In such a conventional thin film transistor, a protective film 6 made of a metal is formed to prevent the aluminum alloy film of the source and drain electrodes 7 and 8 from coming into contact with the amorphous silicon layer of the contact layer 5 so that spike phenomenon occurs. have.

Therefore, in the manufacturing method of such a thin film transistor, the process which should form the protective film 6 is added.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and the problem is to simplify the manufacturing process of the thin film transistor and improve the product characteristics by forming the source and data electrodes in a single layer.

In the thin film transistor according to the present invention, a gate electrode is formed on the substrate, and a semiconductor layer formed on the gate insulating film covering the gate electrode is formed of a microcrystalline silicon layer. Source and drain electrodes are formed on the semiconductor layer.

The gate electrode and the source and drain electrodes may be formed as a single film of an aluminum alloy film or a molybdenum alloy film or as a double film in which a molybdenum film or a molybdenum alloy film is added on top of the aluminum alloy film.

In the method of manufacturing a thin film transistor according to the present invention, microcrystalline silicon is deposited and patterned to form a semiconductor layer.

In the thin film transistor and the manufacturing method thereof according to the present invention, the spike phenomenon does not occur even when the aluminum alloy film of the source and drain electrodes and the semiconductor layer of the microcrystalline silicon layer are integrated into contact.

Here, the spike phenomenon will be described in detail in the embodiment according to the present invention.

Microcrystalline silicon also has better electron mobility than amorphous silicon.

Then, embodiments of the thin film transistor according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can be easily implemented.

2 is a cross-sectional view illustrating a structure of a thin film transistor according to an exemplary embodiment of the present invention.

The gate electrode 200 and a protective film 600 are formed on the substrate 100. The gate electrode 200 may be formed of a double film including a single film of an aluminum alloy film or a molybdenum alloy film or an aluminum alloy film as a lower film and a molybdenum film or molybdenum alloy film as an upper film.

A gate insulating layer 300 made of an oxide film or a nitride film is formed on the gate electrode 200.

The contact layer 510 of the semiconductor layer 400 of the hydrogenated amorphous silicon (a-Si: H) layer and the microcrystalline silicon layer heavily doped with n + impurities are formed on the gate insulating layer 300 on the gate electrode 200. 520 is formed on both sides of the gate electrode 200.

A source electrode 700 is formed on the gate insulating layer 300 and one doped microcrystalline silicon layer 510, and a drain is formed on the doped microcrystalline silicon layer 520 opposite to the source electrode 700. The electrode 800 is formed. Here, the source and drain electrodes 700 and 800 may be formed as a double film including a single film of an aluminum alloy film or a molybdenum alloy film or an aluminum alloy film as a lower film, and a molybdenum film or molybdenum alloy film as an upper film.

A passivation layer 110 covering the source and drain electrodes 700 and 800 is formed on the substrate 100, and an opening 900 exposing the drain electrode 800 is formed in the passivation layer 110.

Finally, a pixel electrode 120 made of ITO and connected to the drain electrode 800 is formed on the passivation layer 110 through the opening 900.

Here, in the case where the source and drain electrodes 700 and 800 are formed of an aluminum alloy (Al-Nd) film containing neodium (Nd), the aluminum alloy (Al-Nd) film is formed of ITO and the pixel electrode 120. In order to generate a battery effect by contact, an aluminum-silicon alloy film including silicon (Si) is formed on the aluminum alloy (Al-Nd) film or aluminum except Al-Nd. -Only a single film of an Al-Si alloy film is used to prevent battery effects.

As such, when the microcrystalline silicon layers 510 and 520 are formed under the source and drain electrodes 700 and 800 of the aluminum alloy film, spikes generated when the contact layer 5 is formed of an amorphous silicon layer in the related art. The phenomenon can be prevented.

Here, the spike phenomenon is that when a metal layer such as aluminum is formed on top of the silicon layer and heat treated, a recrystallized layer, which is a contact layer at the interface between the two layers when silicon is dissolved and cooled in aluminum, is formed deeply or broadly. It means that the failure of the device is caused.

Next, a method of manufacturing a thin film transistor according to an exemplary embodiment of the present invention will be described.

An aluminum alloy layer or a molybdenum alloy layer is stacked on the transparent insulating substrate 100 and photo-etched using a mask to form a gate electrode 200 of a single layer. When the gate electrode 200 is formed of a double layer, an aluminum alloy layer may be used as a lower layer and a molybdenum layer or a molybdenum alloy layer may be formed as an upper layer. Here, as a method of forming the protective film 600 on the gate electrode 200, an anodization method or a double film described above is formed.

The gate insulating layer 300 made of silicon nitride, the hydrogenated amorphous silicon layer, and the hydrogenated microcrystalline silicon layer heavily doped with N-type impurities are sequentially stacked, and then contact layers 510 and 520 of the doped microcrystalline silicon layer are stacked. ) And photo-etched using the semiconductor layer 400 of the amorphous silicon layer as a mask.

After the aluminum alloy layer is stacked, the source electrode 700 and the drain electrode 800 form a data pattern by etching using a mask.

The source and drain electrodes 700 and 800 may be formed of a single film of molybdenum alloy, and unlike the prior art, the contact layers 510 and 520 may be formed of a microcrystalline silicon layer to prevent spikes even with a single film. In addition, low-resistance source and drain electrodes 700 and 800 may be formed to cope with large area and high resolution.

Subsequently, the exposed doped microcrystalline silicon layers 510 and 520 are etched using the source and drain electrodes 700 and 800 as masks, and then separated from both sides around the gate electrode 200, while both doped microcrystals are etched. The semiconductor layer 400 of the amorphous silicon layer between the contact layers 510 and 520 of the silicon layer is exposed.

After the protective layer 110 is stacked, an opening 900 for exposing an upper portion of the drain electrode 800 is formed by photolithography using a mask.

In this case, when the drain electrode 800 is formed of an aluminum alloy (Al-Nd) film, an aluminum-silicon alloy (Al-Si-alloy) may be formed on the aluminum alloy (Al-Nd) film, or an aluminum-silicon alloy may be formed. Use a single membrane.

Finally, ITO is stacked and etched using a mask to form the pixel electrode 120 connected to the drain electrode 800 through the opening 900.

By forming an aluminum-silicon alloy (Al-Si-alloy) on the aluminum alloy (Al-Nd) film of the drain electrode 800, it is possible to prevent the battery effect caused by the contact of the ITO and the aluminum alloy film.

Therefore, in the thin film transistor and the manufacturing method according to the present invention, by forming the contact layer as a microcrystalline silicon layer, even if the source and drain electrodes are formed of an aluminum alloy film, the spike phenomenon can be prevented and the manufacturing process is simplified as a single film formation. can do. In addition, in order to prevent contact with ITO, an aluminum-silicon alloy film may be formed on the aluminum alloy film to prevent battery effects.

1 is a cross-sectional view showing the structure of a thin film transistor according to the prior art,

2 is a cross-sectional view illustrating a structure of a thin film transistor according to an exemplary embodiment of the present invention.

Claims (11)

Board, A gate electrode formed on the substrate, A gate insulating layer formed on the substrate and covering the gate electrode; A semiconductor layer formed on the gate insulating film of the gate electrode and formed of an amorphous silicon layer; A contact layer formed in two parts on the semiconductor layer, doped with high concentration, and made of microcrystalline silicon, A source and drain electrode formed on the contact layer, wherein the source and drain electrodes are made of a double film having an aluminum alloy film as a lower film and a molybdenum film or a molybdenum alloy film as an upper film; A protective film formed on the substrate and having an opening on the drain electrode; And a pixel electrode formed on the passivation layer and connected to the drain electrode through the opening. In claim 1, The gate electrode is a thin film transistor including a single film of an aluminum alloy film or a molybdenum alloy film or a double film including a lower film of an aluminum alloy film and a molybdenum or molybdenum alloy film as an upper film. In claim 1, And a silicon-silicon alloy film on the aluminum alloy film of the source and drain electrodes. Depositing and patterning a metal film on the transparent insulating substrate to form a gate electrode, Forming a gate insulating film on the substrate; Depositing and patterning an amorphous silicon layer on the substrate to form a semiconductor layer, Forming a contact layer with microcrystalline silicon, Stacking and patterning an aluminum alloy film and a molybdenum film or a molybdenum alloy film thereon to form a source electrode and a drain electrode, and etching a part of the contact layer using the source and drain electrodes as a mask; Stacking a passivation layer to expose a portion of the drain electrode; Stacking and etching a transparent conductive material to form a pixel electrode connected to the drain electrode. In claim 4, Stacking an aluminum-silicon alloy film on top of the aluminum alloy film of the source and drain electrodes. Board, A gate electrode formed on the substrate and having sidewalls formed in a tapered structure; A gate insulating layer formed on the substrate and covering the gate electrode; A semiconductor layer formed on the gate insulating film of the gate electrode and formed of an amorphous silicon layer; A contact layer formed on the semiconductor layer, doped, and made of microcrystalline silicon, A source electrode and a drain electrode formed on the contact layer, respectively, and formed of a double film having an aluminum alloy film as a lower film and a molybdenum film or a molybdenum alloy film as an upper film; A protective film formed on the substrate and having an opening on the drain electrode; And a pixel electrode formed on the passivation layer and connected to the drain electrode through the opening. In claim 6, And a sidewall of the passivation layer defining the opening has a tapered structure. In claim 6, And a sidewall of the semiconductor layer and the contact layer has a tapered structure. Board, A gate electrode formed on the substrate, A gate insulating layer formed on the substrate and covering the gate electrode; A semiconductor layer formed on the gate insulating film of the gate electrode and formed of an amorphous silicon layer; A contact layer formed on the semiconductor layer, doped and made of microcrystalline silicon, A source electrode and a drain electrode formed on the contact layer, respectively, and formed of a double film having an aluminum alloy film as a lower film and a molybdenum film or a molybdenum alloy film as an upper film; A protective film formed on the substrate and defined by sidewalls having a tapered structure and having an opening exposing the drain electrode; And a pixel electrode formed on the passivation layer and connected to the drain electrode through the opening. In claim 9, And a sidewall of the gate electrode has a tapered structure. In claim 9, And a sidewall of the semiconductor layer and the contact layer has a tapered structure.

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