JPH1027153A - Bus transfer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the scale of a control program by making it unnecessary to read out address information from another storage device in the case of connecting a peripheral device having no register capable of storing address information. SOLUTION: Only address information registers 7, 8 are added to a bus transfer device having a peripheral device including no address information register and connected to a bus similarly to peripheral devices 4, 5. The added address information registers 7, 8 store the address information A2, A3 of the peripheral devices 4, 5 having no address information register. A program stored in a CPU 1 acquires the address information A2, A3 of all the peripheral devices 4, 5 only by reading out information from the registers 7, 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bus transfer device used for a computer.

[0002]

2. Description of the Related Art A conventional bus transfer device has a configuration in which a CPU 1, peripheral devices 3 to 5, and an address information storage device 6 are connected to a bus 2, as shown in FIG. Here, the peripheral device 3 includes an address information register 3a, and stores address information A1 for the CPU 1 to read from and write to the peripheral device 3. However, the peripheral devices 4 and 5 do not include an address information register. At this time, in order for the CPU 1 to read and write to the peripheral devices 4 and 5, it is necessary to use the address information A2 and A3 separately stored in the address information storage device 6.

FIG. 5 shows a flowchart of a program stored in a CPU of a conventional bus transfer device. In the operation step S1, in reading the slot SLN, first, N = 1 is set as an initial value to acquire the value of the address information register from the slot SL1. In the operation step S2, it is determined that reading has been completed up to the final slot by determining that N has exceeded the number of final slots. In reading the slot SL1, since N has not reached the last slot, the operation step S3 is executed.

In an operation step S3, an instruction for reading the address information register of the slot SL1 is issued. Slot S
L1 includes a peripheral device 3 having an address information register 3a.
Is connected, the address information A1 is returned to the CPU 1 via the bus 2. Thereby, the operation step S
4 recognizes that the address information A1 has been returned,
Since the presence of the address information register 3a can be recognized, "existing" is reported in the register check processing.

Since the address information register 3a exists in the register check processing in the operation step S4, the register reference processing S1 consisting of the operation steps S3, S4 and S5
0 will be performed. By the operation step S5 in the register reference processing S10, as shown in FIG.
Address information A1 corresponding to L1 is stored in address table AT by CPU1. In the operation step S6, the value of N is increased by 1, and the slot SL2 is designated.

In the operation step S2, the slot number is set to the number of slots N previously determined by the system (for example, N = 8).
It is determined whether or not the last slot SLN has been read out by comparing whether or not the last slot has been reached. However, since the last slot has not been reached after reading out the slot SL1, a report “not the last slot” is made. Since it is not the last slot, an instruction to read the next slot SL2 is issued in operation step S3.

Since the peripheral device 4 has no address information register, no address information is returned in response to the instruction to read the slot SL2. Therefore, a report that "the address information register does not exist" is made in the register check processing in the operation step S4. Since the address information register does not exist in the register check processing in the operation step S4, the storage device reference processing S11 including the operation steps S8 and S9 is performed.

In operation S8, the address information table stored in the address information storage device 6 in the format shown in FIG. 7 is referred to, and the address information A2 corresponding to the slot SL2 is read.
Is read. In the operation step S9, it is confirmed that the address information A2 read from the address information storage device 6 is paired with the slot number SL2, and it is recognized that "address information is valid". In the operation step S5, as shown in FIG. 6, the address information A2 corresponding to the slot SL2 is stored in the address table AT by the CPU 1.

After the operation steps S6 and S2, a read instruction is issued for the next slot SL3.
Since there is no address information register in the register check process in step 4, the address information A3 corresponding to the slot SL3 is stored in the address table AT by referring to the address information table of the address information storage device 6.

Regarding the slot SL4, the address information storage device 6 itself does not have an address information register.
Address information is not returned in response to the instruction to read slot SL4. Therefore, in the register check processing in operation step S4, a report that "address information register does not exist |" is made.

Since there is no address information register in the register check processing in operation S4, a storage device reference processing S11 consisting of operation steps S8 and S9 is performed. In the operation step S8, the address information table stored in the address information storage device 6 in the format shown in FIG. In operation S9, the slot number SL is added to the address information read from the address information storage device 6.
Since there are no four, the address information is recognized as "invalid." Therefore, the address information of the slot SL4 is not registered in the address table AT as a peripheral device.

When the slot number reaches the slot number N in the operation step S2, it is recognized as "the last slot". At this time, the reading of the slot ends, and processing step S7 is executed. In processing step S7, necessary address information Ax is selected from the address table AT, and reading / writing to the peripheral device is performed.

[0013]

The conventional bus transfer device needs to read the address information register 3a and the address information storage device 6 in order to obtain the address information A1 to A3 of the peripheral devices 3 to 5, respectively. Therefore, two types of register reference processing S10 and storage device reference processing S11 are required, and there is a problem that the number of programs stored in the CPU 1 increases.

In the storage device referring process S11,
Since it is necessary to read from the address information storage device before acquiring the address information of the peripheral device, it is necessary to embed the address information of the address information storage device in the program.

An object of the present invention is to provide a bus transfer device which eliminates the need to read address information from another storage device when connecting a peripheral device having no register for storing address information, and reduces the scale of a control program. Is to do.

[0016]

According to the present invention, there is provided a bus transfer system in which a peripheral device having a register storing address information for reading and writing and a peripheral device having no register storing the address information are connected together. An address information register which stores address information corresponding to a peripheral device having no register storing the address information and is connected to a slot independent of the peripheral device;
The program stored in U acquires address information of all peripheral devices only by processing of reading the address information register.

According to the present invention, the presence of the address information register having the address information for all the peripheral devices can eliminate the storage device reference processing from the program stored in the CPU.

[0018]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the bus transfer device shown in FIG. 1, peripheral devices 3 to 5 and address information registers 7 and 8 are connected to a CPU 1 via a bus. The address information registers 7 and 8 are connected to the slots of the bus 2 in the same manner as the peripheral devices.

FIG. 2 shows a flowchart of a program stored in the CPU 1. In the operation step S1, in reading the slot SLN, first, N = 1 is set as an initial value to acquire the value of the address information register from the slot SL1. In the operation step S2, it is determined that reading has been completed up to the final slot by determining that N has exceeded the number of final slots. In reading the slot SL1, since N has not reached the last slot, the operation step S3 is executed.

In the operation step S3, an instruction to read the address information register of the slot SL1 is issued. Slot S
L1 includes a peripheral device 3 having an address information register 3a.
Is connected, the address information A1 is returned. In the operation step S4, it can be recognized that the address information A1 has been returned, so that "existing" is reported.

Since the address information register 3a exists in the register check process in the operation step S4, the address information A1 corresponding to the slot SL1 is stored in the address table AT by the CPU 1 in the operation step S5 as shown in FIG. . In operation step S6, the value of N is set to 1
The slot SL2 is increased, and the slot SL2 is designated.

In operation step S2, since N does not exceed the number of the last slot, operation step S3 is executed. In operation step S3, an instruction to read the address information register of slot SL2 is issued. But slot SL
2 is a peripheral device 4 having no address information register
Is connected, no address information is returned.
In the register check process in the operation step S4, it is recognized that the address information is not returned, and "not present".
Is reported. Since there is no address information register in the register check processing in operation step S4,
The operation step S6 is immediately executed, the value of N is increased by 1, and the slot SL3 is designated.

Since the slot SL3 is not the last slot in the operation step S2, the operation steps S3 and S4 are executed. However, since the slot SL3 does not have the address information register similarly to the slot SL2, it is reported that the slot SL3 does not exist in the operation step S4. Is performed, and the value of N is set to 1 in operation step S6.
The slot SL4 is increased to indicate the slot SL4.

In operation step S2, since N does not exceed the number of final slots, operation step S3 is executed. In the operation step S3, an instruction to read the address information register of the slot SL4 is issued. Since the address information register 7 is connected to the slot SL4, the address information A2 is returned.

In the operation step S4, it can be recognized that the address information A2 has been returned, so that "existing" is reported. Since the address information register 7 exists in the register check process in the operation step S4, the address information A2 corresponding to the slot SL4 is stored in the address table AT by the CPU 1 in the operation step S5 as shown in FIG. In operation step S6, the value of N is set to 1
Increase the number, and designate the slot SL5.

In operation step S2, since N does not exceed the number of final slots, operation step S3 is executed. In the operation step S3, an instruction to read the address information register of the slot SL5 is issued. Since the address information register 8 is connected to the slot SL5, the address information A3 is returned. In the operation step S4, it can be recognized that the address information A3 has been returned, so that "existing" is reported. Since the address information register 8 exists in the register check process in the operation step S4, the address information A3 corresponding to the slot SL5 is stored in the address table AT by the CPU 1 in the operation step S5 as shown in FIG. In the operation step S6, the value of N is increased by 1, and the next slot is designated.

If N reaches the final slot number in the operation step S2, it is recognized as "the last slot". At this time, the reading of the slot ends, and the processing step S7
Execute In processing step S7, necessary address information Ax is selected from the address table AT, and reading / writing to the peripheral device is performed.

Since the address information register 7 stores the address information A2 of the peripheral device 4, the processing step S
7, the peripheral device 4 actually connected to the slot SL2 can be read and written by referring to the address information A2 corresponding to the slot SL4. Similarly, since the address information register 8 stores the address information A3 of the peripheral device 5, the slot SL is stored in the processing step S7.
By reading the address information A3 corresponding to 5, the peripheral device 5 can be actually read and written.

[0029]

As described above, according to the present invention, the CPU 1
Need only have a register reference process, and can omit the address information storage device and the storage device reference process, which has the effect of reducing the size of the program.

Further, the present invention has an effect that it is not necessary to embed the address of the address information storage device itself in a program.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the present embodiment.

FIG. 3 is a diagram illustrating a storage state of address information stored in an address information table according to the present embodiment.

FIG. 4 is a block diagram showing an example of the related art.

FIG. 5 is a flowchart for explaining the operation of the conventional example.

FIG. 6 is a diagram illustrating a storage state of address information stored in a conventional address information table.

FIG. 7 is a diagram illustrating a storage state of address information stored in a conventional address information storage device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Bus 3,4,5 Peripheral device 6 Address information storage device 3a, 7,8 Address information register SL1 SL5 Slot A1-A3 Address information S1-S11 Operation steps

Claims (4)

[Claims] A peripheral device having no register storing address information for reading / writing; and an address information register storing address information of said peripheral device and connected to a bus similarly to said peripheral device, A bus transfer device using address information of the address information register as address information of a peripheral device. 2. A bus transfer device in which a peripheral device having a register storing address information for reading and writing and a peripheral device having no register storing the address information are mixed and connected, and the address information is stored in the bus transfer device. An address information register which stores address information corresponding to a peripheral device having no register and is connected to a slot independent of the peripheral device; and a program stored in a CPU reads all of the address information register only by reading the address information register. A bus transfer device for acquiring address information of a peripheral device. 3. The bus transfer device according to claim 2, wherein the address information register is provided for each of the peripheral devices having no register storing the address information. 4. An address information register storing address information corresponding to a peripheral device which does not have a register storing address information for reading / writing is connected to a bus similarly to the peripheral device, and the address information of the peripheral device is stored. Wherein the address information of the address information register is used.