JPH04213427A - Production of electrode wiring of multiplayered metal film - Google Patents

Abstract

PURPOSE:To prevent the occurrence of trouble such as a leakage current of a thin film transistor by removing the overhang of the upper metal layer of a gate electrode made of a multilayered metal film by re-etching. CONSTITUTION:The overhang of the upper metal layer 120b of a multilayered metal film circuit 12 formed at the time of etching the lower metal layer 120a is removed by re-etching and the sides of the upper and lower metal layers are aligned. Since bubbles are not confined, a film formed later such as a gate insulating film formed by plasma CVD or an operative semiconductive layer is made free from abnormality and the occurrence of trouble such as a leakage current of a thin film transistor can be prevented.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing multilayer metal film electrode wiring. Specifically, when the end faces of the multilayer metal film gate electrode wiring of a thin film transistor used in an active matrix liquid crystal display panel are aligned and smoothed, and a gate insulating film is formed thereon, defects occur from the end face of the gate electrode wiring. The present invention relates to a method of manufacturing a multilayer metal film electrode wiring that prevents the occurrence of

0002

[Prior Art] Simple matrix type liquid crystal display devices and active matrix type liquid crystal display devices are often used as liquid crystal display devices for displaying graphics, but active matrix type liquid crystal display devices are superior in terms of display quality. In particular, in the case of color display, active matrix type liquid crystal display devices are considered to be the most promising and have been put into practical use in some cases.

FIG. 3 is a perspective view of an active matrix liquid crystal display panel. In the figure, reference numeral 1 denotes an active matrix substrate on which a thin film transistor element array is formed on a transparent substrate 11, and each element is provided with a transparent electrode corresponding to a display pixel. 40 and 50 are a gate bus line and a drain bus line to which the gate electrode and drain electrode of each thin film transistor element are connected, and an alignment film 60 is provided thereon.

On the other hand, 2 is a common electrode substrate, and a transparent solid electrode 21 and an alignment film 22 are laminated on a transparent substrate 20. Both substrates are sealed with a sealing material (not shown) between the substrates with a spacer (not shown) in between so that a narrow space is formed with the alignment film surface in the middle, and the liquid crystal 3 is injected into the space and sealed. In this way, an active matrix liquid crystal display panel is constructed.

[0005] Although this figure is for black and white display,
If a color filter is added to this, a color liquid crystal display panel is constructed. FIG. 4 is a diagram showing an example of the configuration of a thin film transistor, and is a conceptually enlarged view of a part of the thin film transistor element group of the active matrix substrate 1 described in FIG. 3 above.

In the figure, reference numeral 10 denotes a thin film transistor, in which a gate electrode 12' protrudes from a gate bus line 40, a metal thin film wiring such as Ti, Ta, Al, Cu, etc., and an active semiconductor on a gate insulating film (not shown). layer 15
, For example, amorphous silicon film (a-Si
A drain bus line 5 is formed from both sides of the drain bus line 5.
For example, ITO (
A thin film transistor is constructed by disposing a source electrode connected to a transparent electrode 19 made of (In2O3-SnO2). Since its operating mechanism is well known, its explanation will be omitted.

FIG. 5 is a diagram showing an example of a multilayer metal film gate electrode wiring of a conventional thin film transistor. is a top view.

For example, a gate electrode 12' is formed on a transparent substrate 11 made of glass or the like (for example, a lower metal film 12'a is made of aluminum with good conductivity, and a layer of Ti which is a high melting point metal for surface protection is formed on the lower metal film 12'a). ) is formed, and then a gate insulating film 13, for example a SiO2 film, an active semiconductor layer 15 is formed.
For example, these are formed by plasma CVD method,
Furthermore, as shown in the figure, a drain electrode 16 and a source electrode 17 are formed with the contact layer 14 in between, thereby configuring a thin film transistor.

Although only one gate portion is shown in the above figure, it goes without saying that in reality, a large number of elements are formed two-dimensionally at the same time.

0010

[Problems to be Solved by the Invention] However, when forming the gate electrode 12' of the above-mentioned thin film transistor, conventionally, after etching the underlying metal film, Al, with a mixed aqueous solution of phosphoric acid, nitric acid, and acetic acid, for example, , the upper metal film, Ti, is reactive ion etched in a mixed gas of CF4 + O2, so A
1 is side-etched in the subsequent isotropic etching, and the end face forms an overhanging structure of Ti as shown in the figure, and as a result, as shown in Figure 5, many bubbles remain on the end face and are generated in the subsequent process. There are serious problems such as defects 4 occurring in the gate insulating film 13 and the active semiconductor layer 15 and an increase in leakage current of the thin film transistor, and solutions to these problems are required.

[0011]

[Means for solving the problem] The above problem is solved by the substrate 11
In a method for manufacturing a multilayer metal film electrode wiring, in which a multilayer metal film 120 is formed on top of the multilayer metal film 120, a resist pattern 5 is formed thereon, and then each layer of the multilayer metal film 120 is etched separately to form an electrode wiring. Metal film 120a
The overhang of the upper metal film 120b that occurs when etching can be solved by a method for manufacturing a multilayer metal film electrode wiring characterized by etching again to align the etched surfaces of both the upper and lower metal film side surfaces. Note that the effect can be further improved by removing the resist pattern 5 in advance when re-etching and removing the overhang of the upper metal film 120b.

0012

[Operation] According to the present invention, the overhang of the upper metal film of the gate electrode 12 made of a multilayer metal film is appropriately thinned by re-etching, the overhang structure is removed, and the end face shape is smoothly aligned. , air bubbles etc. are not trapped, and therefore the film formation performed in the later stage,
For example, defects such as abnormal growth do not occur in the gate insulating film 13 and the active semiconductor layer 15, which are films produced by plasma CVD or the like, and problems such as leakage current of thin film transistors can be prevented.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a method according to an embodiment of the present invention, showing and explaining the main manufacturing steps in order.

In the figure, 12 is a multilayer metal film electrode wiring, for example, a gate electrode of a thin film transistor. Note that the same reference numerals are given to the same parts as those explained in the above drawings, and the explanation of the same parts will be omitted.

Step (1): For example, a lower metal film 120a is formed on a transparent substrate 11 made of glass or the like.
For example, a 100 nm thick Al film (a film with good conductivity) is deposited, and a 40 nm thick Ti film (a protective film with good heat resistance) is sputtered thereon as the upper metal film 120b.

Step (2): A resist pattern 5 is formed on the above-mentioned processed substrate in a region where a gate electrode is to be formed. Step (3): Upper metal film 120b of the treated substrate,
That is, using the Ti film resist pattern 5 as a mask, the Ti film pattern 120' is etched by, for example, RIE (reactive ion etching) using SF4 gas.
form b.

Step (4): The lower metal film 120a, that is, the Al film, is etched on the treated substrate using a phosphoric acid mixed aqueous solution (phosphoric acid + nitric acid + acetic acid + water) to form a lower electrode film 12a. At this time, since Al is etched isotropically, side etching progresses and overhangs occur on both sides of the Ti film pattern 120'b as shown in the figure.

Step (5): The above-mentioned treated substrate is again subjected to moderate RIE using, for example, SF4 gas to etch away only the overhangs occurring on both sides of the Ti film pattern 120'b, thereby removing the upper electrode film 12b. form. At this time, during RIE under these conditions, Al is hardly side-etched.

Step (6): The treated substrate is treated with a suitable resist stripping solution to remove the resist pattern 5.
A multilayer metal film gate electrode wiring 12 is formed by the method of the present invention. Using the substrate on which the multilayer metal film electrode wiring 12 is formed, a gate insulating film, for example, a SiO2 film,
A thin film transistor is constructed by forming an active semiconductor layer, such as an a-Si film, by, for example, a plasma CVD method, and further forming a drain electrode and a source electrode with a contact layer in between. In this case, unlike the conventional case, since there is no overhang in the Ti electrode film which is the upper electrode film 12b of the gate electrode, abnormal growth can be prevented in the plasma CVD film formed thereon.
Therefore, a thin film transistor using the same has no characteristic deterioration, and yield and reliability are improved.

FIG. 2 is a diagram showing another embodiment of the method of the present invention, showing and explaining the main manufacturing steps in order.
The same reference numerals are given to the same parts as those explained in the above drawings, and the explanation of the same parts is omitted.

Step (1): For example, a lower metal film 120a is formed on a transparent substrate 11 made of glass or the like.
For example, an Al film (a film with good conductivity) with a thickness of 100 nm is deposited, and a Ti film (a protective film with good heat resistance) with a thickness of 80 nm, for example, is sputtered thereon as the upper metal film 120b.

Steps (2) to (4): Processes are carried out according to steps (2) to (4) of the method of the embodiment described above with reference to FIG. Step (5): The treated substrate is treated with a suitable resist stripping solution to remove the resist pattern 5.

Step (6): The above-mentioned processed substrate is again subjected to moderate RIE using, for example, SF4 gas to etch away the overhangs occurring on both sides of the Ti film pattern 120'b and remove the upper electrode film 12b. Form. At this time, during RIE under these conditions, Al is hardly side-etched.

In this embodiment, the electrode film 1 on the upper layer of the gate electrode
Since the thickness of the Ti electrode film 2b is thicker, for example twice as thick, than in the case of the previous embodiment, even if the surface portion is etched when the overhang is etched away by RIE. A sufficient thickness remains, and the surface of the gate electrode can be cleaned at the same time, and post-processing, such as P-CVD (plasma CVD) film formation of the gate insulating film, can be easily performed, and a good film can be obtained. It has the advantage of being able to be generated.

It should be noted that the above-mentioned embodiments are merely examples, and it goes without saying that other materials and process conditions may be used for each part as appropriate, as long as they do not go against the spirit of the present invention. For example, as the lower metal film 120a, Cu may be used instead of an Al film (a film with good conductivity), and as the upper metal film 120b, for example, other than a Ti film (a protective film with good heat resistance) may be used. W,Mo
, Ta, etc. may also be used.

Further, in the embodiment, the case of a two-layer metal film has been described, but it goes without saying that the method of the present invention can be applied to a case of three or more layers, if necessary.

[0027]

As explained above, according to the present invention, the overhang of the upper metal film 12b of the gate electrode made of a multilayer metal film is appropriately thinned by re-etching, and the overhang structure is removed to improve the shape of the end face. Since they are arranged in a gentle manner, air bubbles are not trapped. Therefore, film formation performed at a later stage, for example, plasma CVD
For example, defects 4 do not occur in the gate insulating film 13 and the active semiconductor layer 15, which are the films produced by the above, and problems such as leakage current of thin film transistors can be prevented, and the yield of products such as active matrix type liquid crystal display devices can be improved. This greatly contributes to improving quality and reliability.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating an embodiment of the method of the present invention.

FIG. 2 is a diagram showing another embodiment method of the present invention.

FIG. 3 is an external perspective view of an active matrix liquid crystal display panel.

FIG. 4 is a diagram showing a configuration example of a thin film transistor.

FIG. 5 is a diagram showing an example of multilayer metal film gate electrode wiring of a conventional thin film transistor.

[Explanation of symbols]

Claims (2)

[Claims] Claim 1: A multilayer metal film (120
), and after forming a resist pattern (5) thereon, each layer of the multilayer metal film (120) is etched separately to form an electrode wiring. metal film (120
The upper metal film (12
0b) A method for manufacturing a multilayer metal film electrode wiring, which comprises etching the overhang again to align the etched surfaces of the side surfaces of both the upper and lower metal films. 2. The multilayer metal film according to claim 1, wherein the resist pattern (5) is removed in advance when the overhang of the upper metal film (120b) is removed by re-etching. Method for manufacturing electrode wiring.