JP2737982B2 - Method for manufacturing thin film transistor - Google Patents

Description

The present invention relates to a method of manufacturing a self-aligned thin film transistor matrix for preventing occurrence of short-circuit defects, and relates to a thin film transistor capable of preventing cracking of a gate insulating film due to mechanical and physical stress. Forming a resist film self-aligned with the underlying gate electrode on the surface of the channel protective film formed on the transparent insulating substrate, and using the resist film as a mask to protect the channel. In the manufacture of a thin film transistor in which an exposed portion of the film is removed and a source electrode and a drain electrode are formed facing each other on the active semiconductor layer exposed in the removed portion, a desired amount of both side walls of the resist film is removed. Both edges of the channel protective film are exposed, and an ohmic contact is formed on the exposed surface of the operating semiconductor layer including the exposed channel protective film. After stacking a conductive film Ntakuto layer and the source and drain electrodes, and configured to form the source and drain electrodes by applying a lift-off method using the resist film.

[Industrial applications]

The present invention relates to a method for manufacturing a self-aligned thin film transistor matrix for preventing occurrence of short circuit defects.

A liquid crystal display device has characteristics such as low power consumption, light weight, and color display. Therefore, the liquid crystal display device has been commercialized as a display device for pocket televisions and information terminals, and is gaining a wide market. In particular, a thin film transistor-driven active matrix type liquid crystal display device capable of displaying a large-capacity and clear gradation display has been partially put into practical use, and is being actively developed.

In this thin film transistor matrix, a thin film transistor is added to each pixel. Therefore, in order to manufacture such a transistor, it is necessary that tens of thousands to hundreds of thousands of transistors can be formed with no defect and a high yield, and that the cost be low.

Furthermore, when used for an information terminal, even a single point defect may be read as erroneous information, so that the requirement for no defect is stricter.

[Conventional technology]

The second method of manufacturing a conventional thin film transistor matrix
This will be described with reference to FIGS.

As shown in FIG. 2A, a gate electrode G is formed on a glass substrate 1. Next, as shown in FIG.
The gate insulating film 2, the active semiconductor layer 3, and the channel protective film 4 are formed by a plasma chemical vapor deposition (P-CVD) method.

Next, as shown in FIG.
The resist film applied thereon is subjected to backside exposure using the gate electrode G as a mask as shown by an arrow, thereby forming a resist film 5 that is aligned with the gate electrode G.

Next, as shown in FIG. 4D, the exposed portion of the channel protective film 4 is etched away using the resist film 5 as a mask.

Next, after forming the ohmic contact layer 6 and the source / drain electrode film 7 while leaving the resist film 5, the resist film 5 is removed, and the ohmic contact layer 6 and the electrode film 7 adhered thereon are removed. After lift-off, source and drain electrodes S and D are formed, and the thin film transistor shown in FIG. 3 is completed.

As described above, in the conventional manufacturing method, the channel protective film 4 and the source / drain electrodes S are formed by forming the resist film 5 aligned with the gate electrode G and performing etching and lift-off using the resist film 5 as a mask. , D,
It is self-aligned with the resist film 5 and is formed as a mutually inverted pattern.

Therefore, according to the conventional manufacturing method, the channel protective film 4 and the source and drain electrodes S and D do not have a positional shift.
Moreover, there is an advantage that a photomask for forming these is not required.

However, when a thin film transistor is manufactured through the above series of steps, the resist film for etching the channel protective film 4 is the same as the lift-off resist film.
After the lift-off, a minute gap 8 is formed between the channel protective film 4 and the source and drain electrodes S and D. Due to the presence of the gap 8, a mechanical stress or a physical stress is generated in the gate insulating film 2. Cracks occur in the gate insulating film 2 and as a result, the gate electrode G and the source / drain electrodes S,
D was short-circuited, causing display defects.

[Problems to be solved by the invention]

Therefore, in order to prevent the occurrence of display defects, it is necessary to prevent the gate insulating film 2 from cracking even if mechanical stress or physical stress occurs after the completion of the thin film transistor.

Accordingly, an object of the present invention is to prevent cracking of a gate insulator due to mechanical and physical stress.

[Means for solving the problem]

According to the present invention, a gate electrode, a gate insulating film, and a channel protective film are formed on an insulating substrate, and an exposed portion of the channel protective film is formed thereon by using a resist film formed in self-alignment with the gate electrode as a mask. After removing and then reducing at least the dimension of the resist film in the channel direction, a source / drain electrode layer is formed, and unnecessary portions thereof are removed by a lift-off method to form source and drain electrodes. And

(Operation)

As described above, by reducing the size of the resist film after etching the channel protective film, the end of the channel protective film is exposed in the step of forming the source / drain electrode layers. Therefore, the end portions of the source and drain electrodes overlap with the end portions of the channel protective film, and the end face of the channel protective film and the end face of the source and drain electrodes do not have a structure that abuts each other. There is no gap in

Therefore, even if mechanical stress and physical stress occur,
Cracks are less likely to occur in the gate insulating film, and the occurrence of short-circuit defects is reduced.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 (a) to 1 (g).

[See FIG. 1 (a)] A Ti film having a thickness of about 80 nm is formed on a glass substrate 1 by a sputtering method, and unnecessary portions thereof are removed to form a gate electrode G.

[Refer to FIG. (B)]

Next, a gate insulating film having a thickness of about 3
0 nm SiN film 2, about 10 nm thick a-Si as the operating semiconductor layer
An SiO ₂ film 4 having a thickness of about 10 nm is formed as a layer 3 and a channel protective film.

[Refer to Fig. (C)]

A photoresist is applied to the entire surface, and the photoresist is applied to the back surface using the gate electrode G as a mask, as shown by an arrow, to form a resist film 5 aligned with the gate electrode G.

[Refer to Fig. (D)]

Next, using the resist film 5 as a mask, the exposed portion of the SiO ₂ film 4 is removed.

[See (e) in the figure]

Thereafter, prior to the formation of the source and drain electrodes,
The resist film 5 is subjected to isotropic etching. As an etching method, for example, ashing conditions of a resist film,
That is, an oxygen (O ₂ ) gas is flowed at a flow rate of about 50 sccm to about 5 Pa
A high frequency (RF) power of about 300 W is applied in an O ₂ atmosphere controlled to a moderate pressure, plasma etching is performed under isotropic etching conditions, and the entire exposed surface of the resist film 5 is etched by a desired amount. In this embodiment, this etching amount is set to about 1
μm.

Note that this etching does not necessarily have to be isotropic etching. For example, only a desired amount of both side walls in the channel length direction of the resist film may be removed by an ion beam etching method. In short, the source and drain electrodes are formed in a subsequent source and drain electrode forming step. The resist film surface may be partially removed so that the end of the channel protection film on the side is exposed.

[See (f) in the figure]

After the size of the resist film 5 is reduced in this way, the n ⁺ a-Si layer 6 is formed as an ohmic contact layer to a thickness of about 30 nm.
A Ti film 7 having a thickness of about 100 nm is formed as a source / drain electrode film.

In the present embodiment, since the dimensions of the resist film 5 are reduced, both ends of the channel protective film 4 in the channel length direction are exposed when the n ⁺ a-Si layer 6 and the Ti film 7 are formed. . Therefore, the n ⁺ a-Si layer 6 and the Ti film 7 are formed such that their ends overlap the exposed ends of the channel protective film 4. Therefore, in the present embodiment, there is no gap between the channel protective film and the source / drain electrode films unlike the related art.

[See (g) in the figure]

Next, while removing the resist film 5, the Ti film 7 and the n ⁺ a-Si layer 6 adhered thereon are lifted off to form source and drain electrodes S and D, thereby completing the thin film transistor according to the present embodiment. .

As shown in the figure, the thin film transistor formed according to the present embodiment has a channel protective film 4 and source and drain electrodes S and D.
Since there is no gap between the gate insulating films G, even if mechanical or physical stress is generated, no crack is formed,
The occurrence of short-circuit failure is greatly reduced.

In the present embodiment, only the plasma etching step is added after the etching of the channel protective film, and there is no possibility that the manufacturing process becomes complicated.

〔The invention's effect〕

As described above, according to the present invention, it is possible to prevent a gap from being generated between the channel protective film and the source / drain electrodes by reducing the shape of the resist film after etching the channel protective film, Even if mechanical stress or physical stress occurs, cracks are less likely to occur in the gate insulating film, and the occurrence of short-circuit defects is reduced.

[Brief description of the drawings]

1 (a) to 1 (g) are explanatory views of a manufacturing process according to one embodiment of the present invention, FIGS. 2 (a) to 2 (e) are explanatory views of a conventional TFT manufacturing method, and FIG. 3 is a conventional TFT. FIG. In the figure, 1 is an insulating substrate (glass substrate), 2 is a gate insulating film (Si
N film), 3 is an operating semiconductor layer, 4 is a channel protective film (SiO ₂
Film), 5 is a resist film, 6 is an ohmic contact layer,
7 is a source / drain electrode film, 8 is a gap, G is a gate electrode, and S and D are source and drain electrodes.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Teruhiko Ichimura 1015 Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (56) References JP-A-60-104670 (JP, A) JP-A-60-160 45066 (JP, A)

Claims (1)

(57) [Claims] A resist film (5) self-aligned with a lower gate electrode (G) is formed on the surface of a channel protective film (4) formed on a transparent insulating substrate (1). Using the mask (5) as a mask, the exposed portion of the channel protective film (4) is removed, and a source electrode (S) and a drain electrode (D) are formed on the active semiconductor layer (3) exposed in the removed portion. In manufacturing the thin film transistor, a desired amount of both side walls of the resist film (5) is removed to expose both end portions of the channel protective film (4), and the operation including the exposed channel protective film is performed. After stacking an ohmic contact layer (6) and a conductive film (7) for source and drain electrodes on the exposed surface of the semiconductor layer (3), a lift-off method using the resist film (5) is performed to form the source and drain. Electrodes (S, D A) a method of manufacturing a thin film transistor.