JPH04199663A - Pad grid array package - Google Patents

Abstract

PURPOSE:To protect a package against cracks at mounting by a method wherein an empty space nearly as large as a pattern surface is provided to the rear side of a conductor pattern layer connected to a semiconductor chip, and a recess is provided to the pressing surface of a package main body. CONSTITUTION:A heat sink 14 joined to a semiconductor chip 16 is provided to all the surface of a package main body 10, and a gap 30 is provided between the rear of a conductor pattern layer 24 and the heat sink 14. Therefore, a recess 32 is provided to the rear of the conductor pattern layer 24, the protrusion 14a of the heat sink 14 is housed in the recess 32, and the semiconductor chip 16 is joined to the protrusion 14a and supported. When the heat sink 14 is pressed down at the mounting of a package main body 10, a pressure acts on a pad 12 through the intermediary of the package main body 10, and the pad 12 is uniformly pressed down. By this setup, a package can be properly mounted as protected against cracks.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to pad grid array packages.

(Prior Art) A pad grid array package is mounted using pads provided on the outer surface of the package as external connection terminals.

FIG. 5 shows a conventional example in which a semiconductor device using a pad grid array package is mounted on a substrate. and a heat sink 14. The semiconductor chip 16 is bonded to the heat sink 14 and sealed with a lid 18.

FIG. 6 shows a plan view of the pad grid array package. The package body 10 is provided with a conductor pattern layer 24 having a conductor pattern formed on its surface so as to surround a storage recess 22 in which the semiconductor chip 16 is accommodated.

(Problem to be Solved by the Invention) The semiconductor device described above is connected to the mounting board 20 via the pad 12, but the semiconductor device can be mounted by soldering at the pad portion, or by positioning the semiconductor device on the mounting board. There is a method of press-fitting with the holding pad portion pressed.

When mounting semiconductor devices by pressure mounting, a pressing force of about 300 g is applied per bottle to ensure a secure connection, but recently, as packages are becoming more pin-multiple, the pressing force for one package as a whole is It can reach up to several tens of kilograms. As a result of such a large pressing force being applied to the package, a problem arises in that the package body cracks when the package is mounted.

This is because a pressing force during mounting is applied to the thinly formed conductor pattern layer 24, and cranking occurs due to the inability to withstand the stress generated by the pressing force. As shown in FIG. 6, cracks often occur in the conductor pattern layer 24 at some corners where stress concentration tends to occur.

Recent pad grid array packages have become larger in size and thinner as the number of pins increases. For example, a package with an external size of 45+ nm and a thickness of about 3 mm is used. For this reason, the storage recess 2 in which the semiconductor chip is mounted is
2 has expanded, making it easier for the crank to fit into the conductor pattern layer.

Note that when a semiconductor device is mounted by soldering, the semiconductor device is pressed and soldered to a mounting board, so there is a problem similar to that described above in that the package is cracked.

The present invention has been made to solve the above problems,
The purpose is to provide a pad grid array package that can be reliably mounted without causing any cracks in the package when mounted.

(Means for solving problems) The present invention has the following configuration to achieve the above object.

That is, in a pad grid array package that is mounted by pressing a package body against a mounting board and soldering or pressure-fitting, a conductor pattern layer on which a conductor pattern is formed to connect to a semiconductor chip mounted on the package body. The package body is characterized in that a recess is formed on the pressing surface of the package body so as to form a gap on the back side in approximately the same area as the pattern surface on which the conductor pattern is formed.

Further, a heat sink is attached to the pressing surface of the package body, and a gap is provided between the semiconductor chip mounting surface of the heat sink and the back surface of the conductor pattern layer.

(Function) By forming a recess on the pressing surface that presses the package body during mounting and forming a gap on the back side of the conductive pattern layer, the pressing force during mounting does not directly act on the conductive pattern layer. Stress concentration on the conductor pattern layer is alleviated, and cracks are prevented from occurring due to pressing force.

(Embodiments) Hereinafter, preferred embodiments of the present invention will be described in detail based on the accompanying drawings.

FIG. 1 is an embodiment showing a state in which a semiconductor device using a pad grid array package according to the present invention is mounted.

The pad grid array package of this embodiment includes a package body 10, a pad 12, and a heat sink 14 bonded to the package body 10. Package body 1
0 is provided with a conductor pattern layer 24 having a conductor pattern formed on an exposed surface to be connected to a semiconductor chip. The conductor pattern and the pad 12 are connected by an internal wiring pattern.

In this embodiment, a heat sink 14 for bonding a semiconductor chip 16 is provided on the entire surface of the package body 10, and a feature is that a gap 30 is provided between the back surface of the conductive pattern layer 24 and the heat sink 14. Conductor pattern layer 2
4 protrudes like a tongue in cross section facing the side surface of the semiconductor chip 16 as shown in the figure. The gap 30 is provided at the rear surface of the tongue-like protruding conductor pattern layer 24 so as to be spaced apart from the heat sink 14.

In the embodiment shown in FIG. 1, a recess 32 is formed on the back surface of the conductive pattern layer 24, and the protrusion 14a of the heat sink 14 is housed in the recess 32.

A semiconductor chip 16 is bonded and supported by the protrusion 14a, and after the semiconductor chip 16 and the conductor pattern of the conductor pattern layer 24 are connected by wire bonding, the lid 18 seals the semiconductor chip 16.

When the semiconductor device obtained in this way is press-fitted and mounted, when the heat sink 14 is pressed, a pressing force acts on the pad 12 portion through the package body 10, and the pressing force is applied evenly to the pad 12 portion. This enables suitable implementation.

Regarding the conductor pattern layer 24 that is prone to cracking during press-fitting in conventional packages, by providing a gap 30 between the conductor pattern layer 24 and the heat sink 14, pressing force does not directly act on the conductor pattern layer 24. , will not cause cracks.

2-4 illustrate other embodiments of pad grid array packages.

In the embodiment shown in FIG. 2, like the embodiment shown in FIG. 1, a gap 30 is provided between the heat sink 14 and the conductor pattern layer 24, so that the pressing force that presses the package during mounting directly acts on the conductor pattern layer 24. I tried not to do that.

In this embodiment as well, a heat sink 14 is provided and the semiconductor chip 16 is supported by the heat sink 14, as in the above example, but in this embodiment, the heat sink 14 is The package body 10 is not provided on the entire surface of the package body 10.
installed in the center of the Since the heat sink 14 is pressed during mounting, the outer peripheral position of the heat sink 14 is pressed over a wider area than the inner peripheral position of the pad forming surface of the package body 10, so that the pressing force acts on the pad 12 as evenly as possible.

FIG. 3 shows an example in which a support layer 34 for supporting the semiconductor chip 16 is provided on the package body 10 without attaching a heat sink to the package body 10. A recess 32 is provided on the back side of the support layer 34, so that when the package body 10 is pressed when a semiconductor device is mounted, the pressing force acts evenly on the pads 12, and the support layer 34 and the conductor pattern layer 24 are pressed. Prevents pressure from acting directly.

In the embodiment shown in FIG. 4, a ceramic bottom hole 36 is formed integrally with the package body 10 instead of the heat sink.
This is an example in which a semiconductor chip 16 is bonded to and supported by a bottom plate 36. A gap 30 is provided between the bottom plate 36 and the conductive pattern layer 24 as in the above example. The pad grid array package of the embodiment shown in FIGS. 3 and 4 has the advantage that it can be formed as a ceramic package with a bottom plate 36 by simultaneous firing.

As shown in the above embodiments, the pad grid array package according to the present invention provides a gap on the back side of the conductor pattern layer where the stress due to the suppressing force during mounting acts most concentratedly, thereby reducing the pressing force. This prevents it from acting directly on the conductor pattern layer. Therefore, various methods can be used to form the voids, and the void forming range may be set appropriately. Furthermore, since there are various conductor pattern layers depending on the product, such as a single layer or multiple layers, the gap formation range is set depending on each product.

Although the present invention has been variously explained above using preferred embodiments, the present invention is not limited to these embodiments.
Of course, many modifications can be made without departing from the spirit of the invention.

(Effects of the Invention) According to the pad grid array package according to the present invention, as described above, the pressing force at the time of mounting acts evenly on the pads, making it possible to perform reliable mounting, and also to prevent crack-prone conductor pattern layers. It can be mounted without directly applying pressing force, and it can be mounted suitably without causing cracks in the package. Further, this provides remarkable effects such as being able to effectively cope with the increase in the size of the package.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of an embodiment of a semiconductor device using a pad grid array package according to the present invention;
4 to 4 are sectional views of other embodiments, and FIGS. 5 and 6 are sectional views and plan views of conventional examples of a semiconductor device using a pad grid array package. 10...Package body, 12...Pad,
14... Pl-sink, 16... Semiconductor chip, 18... Lid, 20... Mounting board,
22... Storage recess, 24... Conductor pattern layer,
30...Gap, 32...Recess.

Claims (1)

[Claims] 1. In a pad grid array package mounted by pressing a package body against a mounting board and soldering or press-fitting the package body, a conductor pattern is formed to connect to a semiconductor chip mounted on the package body. A pad grid array package characterized in that a concave portion is formed on the pressing surface of the package body to form a gap on the back side of the conductive pattern layer in approximately the same area as the pattern surface on which the conductive pattern is formed. . 2. The pad grid array package according to claim 1, wherein a heat sink is attached to the pressing surface of the package body, and a gap is provided between the semiconductor chip mounting surface of the heat sink and the back surface of the conductor pattern layer.