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JPS5992556A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5992556A
JPS5992556A JP57201956A JP20195682A JPS5992556A JP S5992556 A JPS5992556 A JP S5992556A JP 57201956 A JP57201956 A JP 57201956A JP 20195682 A JP20195682 A JP 20195682A JP S5992556 A JPS5992556 A JP S5992556A
Authority
JP
Japan
Prior art keywords
pellet
semiconductor
semiconductor pellet
inner lead
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57201956A
Other languages
Japanese (ja)
Inventor
Kunihiko Nishi
邦彦 西
Yoshiaki Wakashima
若島　喜昭
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57201956A priority Critical patent/JPS5992556A/en
Publication of JPS5992556A publication Critical patent/JPS5992556A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive to mount with a high density by mounting a semiconductor pellet at inner lead parts of a lead frame. CONSTITUTION:The semiconductor pellet 1 is mounted by superposing the tip of the inner lead part 3 of the lead frame 2 on the periphery of the pellet 1. On the lower surface of the tip of the lead part 3, the upper surface close to the periphery of the pellet 1 is mounted via a junction layer 4. The junction layer 4 can join the lower surface of the lead part 3 on an insulation layer by utilizing the layer formed at regions other than bonding pads 5 of the pellet 1. The lead parts 3 are connected to the bonding pads 5 of the pellet 1 by means of wires 6.

Description

【発明の詳細な説明】 本発明は半導体装置に関し５％に、高密度化を実現でき
る半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and relates to a semiconductor device that can realize a 5% higher density.

従来、半導体装置の製造において半導体ペレットをリー
ドフレームに取り付ける方式の場合、半導体ペレットは
リードフレームのタブと呼ばれるペレット取付部に取り
付けている。Conventionally, in a method of attaching a semiconductor pellet to a lead frame in manufacturing a semiconductor device, the semiconductor pellet is attached to a pellet attaching portion called a tab of the lead frame.

その場合、タブに取シ付けられる半導体ペレットとリー
ドフレームのインナーリード部との間には隙間が形成さ
れ、この隙間をまたいで半導体ペレットのポンディング
パッドとリードフレームのインナーリード部とをワイヤ
でボンディングすることによシ結線を行なっていた。In that case, a gap is formed between the semiconductor pellet attached to the tab and the inner lead part of the lead frame, and a wire is passed across this gap to connect the bonding pad of the semiconductor pellet and the inner lead part of the lead frame. Wire connections were made by bonding.

そのため、従来の半導体装置では、半導体ペレットとリ
ードフレームのインナーリード部との間に隙間が形成さ
れる分だけ空間的な余裕を設けることが必要であり、半
導体ペレットの寸法が大きくなると実装が困難になると
いう問題があった。Therefore, in conventional semiconductor devices, it is necessary to provide space to compensate for the gap formed between the semiconductor pellet and the inner lead part of the lead frame, and mounting becomes difficult when the size of the semiconductor pellet becomes large. There was a problem with becoming.

本発明の目的は、前記従来技術の問題点を解決し、大き
い寸法の半導体ペレットでも有効に実装でき、高密度化
を達成できる半導体装置を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the problems of the prior art described above, to provide a semiconductor device that can be effectively mounted even with large-sized semiconductor pellets, and that can achieve high density.

以下、本発明を図面に示す一実施例にしたがって詳細に
説明する。Hereinafter, the present invention will be explained in detail according to an embodiment shown in the drawings.

第１図は本発明による半導体装置の一実施例の要部を示
す部分平面図、第２図は本発明による半導体装置の一実
施例の断面図である。FIG. 1 is a partial plan view showing essential parts of an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a sectional view of an embodiment of the semiconductor device according to the present invention.

この実施例においては、半導体ペレット１はシリコン（
Ｓｔ）基板上に集積回路を多層配線技術によ多形成した
ものよシなる。In this example, the semiconductor pellet 1 is silicon (
St) A device in which multiple integrated circuits are formed on a substrate using multilayer wiring technology.

一方、この半導体ペレット１を取シ付けるリードフレー
ム２は通常タブと呼ばれているペレット取付部を有して
おらず、半導体ペレット１はり−ドフレーム２のインナ
ーリード部３の先端を該半導体ペレット１の周辺部と重
なシ合わせることによυ、該インナーリード部３の先端
部に直接数シ付けられている。On the other hand, the lead frame 2 to which the semiconductor pellet 1 is mounted does not have a pellet mounting part usually called a tab, and the tip of the inner lead part 3 of the semiconductor pellet 1 is attached to the semiconductor pellet. By overlapping the peripheral part of the inner lead part 1, several parts are attached directly to the tip of the inner lead part 3.

すなわち１本実施例におけるリードフレーム２のインナ
ーリード部３はその先端部が半導体ペレット１の周辺部
の上方に重なシ合っておシ、インナーリード部３の先端
部の下面には、半導体ペレット１の周辺部近くの上面が
接合層４を介して取り付けられている。この接合層４は
半導体ペレット１のポンディングパッド５とは別の領域
に形成された多層配線層のうちの５ｉＯ１層の如き絶縁
層を利用してその絶縁層上にインナーリード部３の下面
を接合することができ、その場合には接合層４自体は導
電性でもよいが、半導体ペレット１の上面の導電層上に
インナーリード部３を取シ付ける場合には、接合層４自
体を絶縁物で構成するのがよい。That is, the inner lead portion 3 of the lead frame 2 in this embodiment has its tip portion overlapped above the peripheral portion of the semiconductor pellet 1, and the lower surface of the tip portion of the inner lead portion 3 has the semiconductor pellet. The upper surface near the periphery of 1 is attached via a bonding layer 4. This bonding layer 4 utilizes an insulating layer such as a 5iO1 layer of a multilayer wiring layer formed in a region different from the bonding pad 5 of the semiconductor pellet 1, and forms the lower surface of the inner lead portion 3 on the insulating layer. In that case, the bonding layer 4 itself may be conductive, but when the inner lead part 3 is attached to the conductive layer on the upper surface of the semiconductor pellet 1, the bonding layer 4 itself may be made of an insulating material. It is better to consist of

このようにしてリードフレーム２のインナーリード部３
の下面に半導体ペレット１を取シ付けた後、インナーリ
ード部３と半導体ペレット１のポンディングパッド５け
ワイヤ６をボンディングすることにより互いに電気的に
接続される。In this way, the inner lead portion 3 of the lead frame 2
After attaching the semiconductor pellet 1 to the lower surface of the semiconductor pellet 1, the inner lead portion 3 and the bonding pad 5 of the semiconductor pellet 1 are electrically connected to each other by bonding the wire 6 to each other.

その後、半導体ペレット１．リードフレーム２のインナ
ーリード部３．接合層４．ワイヤ６等はレジンモールド
型パッケージ７の中に封止される。After that, semiconductor pellets 1. Inner lead portion 3 of lead frame 2. Bonding layer 4. The wire 6 and the like are sealed in a resin molded package 7.

本実施例においては、半導体ペレット１がＩＪ　−ドフ
レーム２のインナーリード部３に直接数シ付けられてい
るので、従来のように半導体ペレットをタブ上に取シ付
け、該半導体ペレットとインナー　リード部との間に隙
間が形成される場合に比して、空間的な無駄がなく、よ
り大きい寸法の半導体ペレットを実装することができ、
高密度実装化が可能となる。In this embodiment, since the semiconductor pellet 1 is directly attached to the inner lead portion 3 of the IJ-deframe 2, the semiconductor pellet is attached on the tab as in the conventional case, and the semiconductor pellet and the inner lead are attached to each other. Compared to the case where a gap is formed between the parts, there is no waste of space, and a semiconductor pellet of a larger size can be mounted.
High-density packaging becomes possible.

なお１本発明は前記実施例に限定されるものではガく、
たとえば半導体ペレット１をリードフレーム２のインナ
ーリード部３の上面に取υ付けること等も可能である。Note that the present invention is not limited to the above embodiments,
For example, it is also possible to attach the semiconductor pellet 1 to the upper surface of the inner lead portion 3 of the lead frame 2.

また１本発明はレジンモールド型の半導体装置に限定さ
れるものではなく。Furthermore, the present invention is not limited to resin mold type semiconductor devices.

たとえばセラミックパッケージで気密封止するもの等も
含むものである。For example, it also includes those hermetically sealed with ceramic packages.

以上説明したように１本発明によれば、半導体ペレット
をリードフレームのインナーリード部に取シ付けること
によシ、大きな寸法の半導体ペレットでも実装でき、高
密度実装化が可能である。As explained above, according to the present invention, by attaching the semiconductor pellet to the inner lead portion of the lead frame, even large-sized semiconductor pellets can be mounted, and high-density packaging is possible.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による半導体装置の一実施例の要部を示
す部分平面図。 第２図は本発明による半導体装置の一実施例の断面図で
ある。 １・・・半導体ベレット、２・・・リードフレーム、３
・・・インナーリード部、４・・・接合層、５・・・ポ
ンディングパッド、６・・・ワイヤ、７・・・レジンモ
ールド型パッケージ。 第　　１　　図 第　　２　　図FIG. 1 is a partial plan view showing essential parts of an embodiment of a semiconductor device according to the present invention. FIG. 2 is a sectional view of one embodiment of a semiconductor device according to the present invention. 1... Semiconductor pellet, 2... Lead frame, 3
... Inner lead part, 4... Bonding layer, 5... Ponding pad, 6... Wire, 7... Resin mold type package. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] １、　リードフレームに半導体ペレットを取り付けてな
る半導体装置において、半導体ペレットをリードフレー
ムのインナーリード部に取シ付けたことを特徴とする半
導体装置。1. A semiconductor device comprising a semiconductor pellet attached to a lead frame, characterized in that the semiconductor pellet is attached to an inner lead portion of the lead frame.
JP57201956A 1982-11-19 1982-11-19 Semiconductor device Pending JPS5992556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57201956A JPS5992556A (en) 1982-11-19 1982-11-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57201956A JPS5992556A (en) 1982-11-19 1982-11-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5992556A true JPS5992556A (en) 1984-05-28

Family

ID=16449551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57201956A Pending JPS5992556A (en) 1982-11-19 1982-11-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5992556A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61218139A (en) * 1985-03-25 1986-09-27 Hitachi Chiyou Lsi Eng Kk Semiconductor device
JPS63141329A (en) * 1986-12-03 1988-06-13 Mitsubishi Electric Corp Ic package
JPH01231333A (en) * 1988-03-10 1989-09-14 Hitachi Ltd Manufacture of semiconductor device
JPH02251149A (en) * 1989-03-24 1990-10-08 Nec Corp Semiconductor device
US5358904A (en) * 1988-09-20 1994-10-25 Hitachi, Ltd. Semiconductor device
US5365113A (en) * 1987-06-30 1994-11-15 Hitachi, Ltd. Semiconductor device
JPH08227967A (en) * 1995-12-28 1996-09-03 Hitachi Vlsi Eng Corp Manufacture of semiconductor device
JPH08227968A (en) * 1995-12-28 1996-09-03 Hitachi Vlsi Eng Corp Semiconductor device
JPH08227903A (en) * 1995-12-28 1996-09-03 Hitachi Vlsi Eng Corp Semiconductor device
JPH08241905A (en) * 1996-03-21 1996-09-17 Hitachi Ltd Semiconductor device
JPH08274243A (en) * 1996-03-21 1996-10-18 Hitachi Ltd Semiconductor device
US5840599A (en) * 1989-06-30 1998-11-24 Texas Instruments Incorporated Process of packaging an integrated circuit with a conductive material between a lead frame and the face of the circuit
US5863817A (en) * 1988-09-20 1999-01-26 Hitachi, Ltd. Semiconductor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5240062A (en) * 1975-09-26 1977-03-28 Hitachi Ltd Process for production of semiconductor devices
JPS57114261A (en) * 1981-01-07 1982-07-16 Hitachi Ltd Lead frame structure

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5240062A (en) * 1975-09-26 1977-03-28 Hitachi Ltd Process for production of semiconductor devices
JPS57114261A (en) * 1981-01-07 1982-07-16 Hitachi Ltd Lead frame structure

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61218139A (en) * 1985-03-25 1986-09-27 Hitachi Chiyou Lsi Eng Kk Semiconductor device
JPS63141329A (en) * 1986-12-03 1988-06-13 Mitsubishi Electric Corp Ic package
JPH0543294B2 (en) * 1986-12-03 1993-07-01 Mitsubishi Electric Corp
US5742101A (en) * 1987-06-30 1998-04-21 Hitachi, Ltd. Semiconductor device
US5365113A (en) * 1987-06-30 1994-11-15 Hitachi, Ltd. Semiconductor device
US5514905A (en) * 1987-06-30 1996-05-07 Hitachi, Ltd. Semiconductor device
JPH01231333A (en) * 1988-03-10 1989-09-14 Hitachi Ltd Manufacture of semiconductor device
US6130114A (en) * 1988-03-20 2000-10-10 Hitachi, Ltd. Semiconductor device
US6081023A (en) * 1988-03-20 2000-06-27 Hitachi, Ltd. Semiconductor device
US6072231A (en) * 1988-03-20 2000-06-06 Hitachi, Ltd. Semiconductor device
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