JPH06163547A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH06163547A JPH06163547A JP31521592A JP31521592A JPH06163547A JP H06163547 A JPH06163547 A JP H06163547A JP 31521592 A JP31521592 A JP 31521592A JP 31521592 A JP31521592 A JP 31521592A JP H06163547 A JPH06163547 A JP H06163547A
- Authority
- JP
- Japan
- Prior art keywords
- opening
- electrode pad
- protective film
- bump
- surface protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Wire Bonding (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は、バンプを有する半導
体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having bumps.
【0002】[0002]
【従来の技術】図4は、従来の半導体装置に用いられて
いるバンプ付近の構造を示す断面図であり、図におい
て、1は集積回路(図示せず)が形成される半導体基
板、2は半導体基板1上に形成され、集積回路の入出力
端子となる電極パッド、3は半導体基板1及び電極パッ
ド2を覆うように形成され、電極パッド2の中央部を露
出するための開口部3aを有する表面保護膜、4は開口
部3aを完全に覆うように電極パッド2及び表面保護膜
3上に形成され、バリアメタルとなるバンプ下地金属
膜、5はバンプ下地金属膜4を介して形成された突起電
極であるバンプである。2. Description of the Related Art FIG. 4 is a sectional view showing a structure near a bump used in a conventional semiconductor device. In the figure, 1 is a semiconductor substrate on which an integrated circuit (not shown) is formed, and 2 is a semiconductor substrate. Electrode pads 3, which are formed on the semiconductor substrate 1 and serve as input / output terminals of the integrated circuit, are formed so as to cover the semiconductor substrate 1 and the electrode pads 2, and have an opening 3a for exposing the central portion of the electrode pad 2. The surface protection film 4 which it has is formed on the electrode pad 2 and the surface protection film 3 so as to completely cover the opening 3a, and the bump base metal film 5 serving as a barrier metal is formed via the bump base metal film 4. The bumps are bump electrodes.
【0003】この図に示すように、バンプ下地金属膜4
は表面保護膜3の開口部3aによる段差を反映する凹部
を有する形状となる。さらに、バンプ5の下面はバンプ
下地金属膜4の表面形状を反映し、中央に凸部を有する
形状となるため、バンプ5の上面は中央に凹部5aを有
する形状となる。すなわち、表面保護膜3が開口部3a
を有するために、バンプ5の上面は凹部5aを有する表
面形状となる。As shown in this figure, the bump base metal film 4 is formed.
Is a shape having a concave portion that reflects a step due to the opening 3 a of the surface protective film 3. Furthermore, since the lower surface of the bump 5 reflects the surface shape of the bump underlying metal film 4 and has a convex portion in the center, the upper surface of the bump 5 has a concave portion 5a in the center. That is, the surface protective film 3 has the opening 3a.
Therefore, the upper surface of the bump 5 has a surface shape having the concave portion 5a.
【0004】このように構成された半導体素子をパッケ
ージングする方法の1つであるフィルムキャリア方式に
より実装する場合には、図5に示すように、電極パッド
2とフィルムキャリアのリード端子6とは、電極パッド
2上に形成されたバンプ5を介して接合される。ところ
が、バンプ5の上面には上述のように凹部5aが存在し
ているため、中央に隙間ができてしまい、バンプ5は周
辺部だけでリード端子6と接続している。When mounting the semiconductor device having the above structure by a film carrier method, which is one of the methods for packaging, the electrode pad 2 and the lead terminal 6 of the film carrier are separated from each other as shown in FIG. , And is bonded via the bumps 5 formed on the electrode pads 2. However, since the recess 5a exists on the upper surface of the bump 5 as described above, a gap is formed in the center, and the bump 5 is connected to the lead terminal 6 only at the peripheral portion.
【0005】[0005]
【発明が解決しようとする課題】従来の半導体装置は、
以上のように構成されていたので、バンプ5とリード線
端子6とはバンプ5の周辺部で接合され、バンプ5とリ
ード端子6との接合強度が低下してしまうという課題が
あった。また、リード端子6をバンプ5に接続する際に
リード端子6からバンプ5に及ぼされる機械的応力及び
熱は、バンプ5の周辺部のみを介して与えられるため、
バンプ5を介してバンプ下地金属膜4等に作用する機械
的応力及び熱的応力は、バンプ5下面の周辺部に局部的
に集中してしまう。このため、半導体基板1、電極パッ
ド2、表面保護膜3及びバンプ下地金属膜4が、この応
力集中によって破壊してしまうという課題があった。The conventional semiconductor device is
With the above-described structure, the bump 5 and the lead wire terminal 6 are bonded to each other in the peripheral portion of the bump 5, and the bonding strength between the bump 5 and the lead terminal 6 is reduced. Further, since mechanical stress and heat exerted on the bump 5 from the lead terminal 6 when connecting the lead terminal 6 to the bump 5 are given only through the peripheral portion of the bump 5,
Mechanical stress and thermal stress acting on the bump underlying metal film 4 and the like via the bumps 5 are locally concentrated on the peripheral portion of the lower surface of the bumps 5. Therefore, there is a problem that the semiconductor substrate 1, the electrode pad 2, the surface protective film 3, and the bump underlying metal film 4 are destroyed by the stress concentration.
【0006】この発明は上記のような課題を解消するた
めになされたもので、バンプとリード端子との接合強度
を上げることができるとともに、バンプ下面からバンプ
下地金属膜等に作用する機械的応力及び熱的応力の局部
的集中を回避することにより、バンプ下地金属膜等が破
壊することがなく信頼性の高い半導体装置を得ることを
目的とする。The present invention has been made in order to solve the above problems, and it is possible to increase the bonding strength between the bump and the lead terminal, and at the same time, the mechanical stress acting on the bump underlying metal film or the like from the lower surface of the bump. Further, by avoiding local concentration of thermal stress, it is an object to obtain a highly reliable semiconductor device in which a bump underlying metal film or the like is not destroyed.
【0007】[0007]
【課題を解決するための手段】この発明の請求項1に係
る半導体装置は、開口部の真下の位置の半導体基板上
に、開口部と同一の大きさで表面保護膜と同一の厚さの
電極パッド下地を形成したものである。According to a first aspect of the present invention, there is provided a semiconductor device having the same size as the opening and the same thickness as the surface protective film on the semiconductor substrate immediately below the opening. The electrode pad base is formed.
【0008】この発明の請求項2に係る半導体装置は、
開口部の真下の位置の半導体基板に環状の溝が形成さ
れ、溝の内径は開口部の外径と同一であり、溝の深さは
表面保護膜の厚さと同一であるものである。A semiconductor device according to claim 2 of the present invention is
An annular groove is formed in the semiconductor substrate immediately below the opening, the inner diameter of the groove is the same as the outer diameter of the opening, and the depth of the groove is the same as the thickness of the surface protective film.
【0009】[0009]
【作用】この発明の請求項1に係る半導体装置において
は、開口部と同一の大きさで表面保護膜と同一の厚さで
開口部の真下の位置の半導体基板上に電極パッド下地を
設けているので、表面保護膜を形成した際に電極パッド
の上面と表面保護膜の上面との間に段差が生じないよう
になる。In the semiconductor device according to the first aspect of the present invention, the electrode pad base is provided on the semiconductor substrate having the same size as the opening and the same thickness as the surface protection film and directly below the opening. Therefore, when the surface protective film is formed, no step is formed between the upper surface of the electrode pad and the upper surface of the surface protective film.
【0010】この発明の請求項2に係る半導体装置にお
いては、半導体基板に所定の寸法の溝を設けることによ
り、電極パッドの上面と表面保護膜の上面との間に段差
が生じないようになる。In the semiconductor device according to the second aspect of the present invention, by providing the semiconductor substrate with a groove having a predetermined size, no step is formed between the upper surface of the electrode pad and the upper surface of the surface protective film. .
【0011】[0011]
実施例1.この実施例1は、この発明の請求項1に係る
一実施例である。図1はこの発明の実施例1を示す断面
図であり、図において、図4、図5に示した従来の半導
体装置と同一又は相当部分には同一符号を付し、その説
明は省略する。7は表面保護膜3の開口部3aの真下の
位置の半導体基板1上に、開口部3aとほぼ同一の大き
さで表面保護膜3とほぼ同一の厚さに形成された電極パ
ッド下地である。Example 1. The first embodiment is an embodiment according to claim 1 of the present invention. 1 is a cross-sectional view showing a first embodiment of the present invention. In the figure, the same or corresponding parts as those of the conventional semiconductor device shown in FIGS. 4 and 5 are designated by the same reference numerals, and the description thereof will be omitted. Reference numeral 7 denotes an electrode pad base formed on the semiconductor substrate 1 directly below the opening 3a of the surface protection film 3 and having a size substantially the same as the opening 3a and a thickness substantially the same as the surface protection film 3. .
【0012】このように、電極パッド下地7を設けて、
その大きさ及び厚さを上記のように設定することによ
り、電極パッド下地7を覆って形成される電極パッド2
には、電極パッド下地7とほぼ同一の大きさで表面保護
膜3の厚さとほぼ同一の高さの突起部2aが形成され
る。さらに、突起部2aの部分に開口部3aがくるよう
に表面保護膜3を形成すれば、上述のように突起部2a
の高さと表面保護膜3の厚さはほぼ同一であるから、表
面保護膜3の上面と電極パッド2の突起部2aの上面と
の間には段差が生じない。In this way, the electrode pad base 7 is provided,
By setting the size and thickness as described above, the electrode pad 2 formed to cover the electrode pad base 7 is formed.
Is formed with a protrusion 2a having substantially the same size as the electrode pad base 7 and the same height as the thickness of the surface protective film 3. Further, if the surface protection film 3 is formed so that the opening 3a is located at the protruding portion 2a, as described above, the protruding portion 2a is formed.
Since the height of the surface protection film 3 and the thickness of the surface protection film 3 are substantially the same, no step is formed between the upper surface of the surface protection film 3 and the upper surface of the protrusion 2a of the electrode pad 2.
【0013】さらに、図2に示すように、表面保護膜3
の上にバンプ下地金属膜4を形成すれば、当然この表面
保護膜3の上面も段差のない平坦な形成となり、表面保
護膜3の上に形成されるバンプ5の下面も平坦な形成と
なる。従って、バンプ5の上面も凹凸のない平坦な形成
となる。そして、このバンプ5の上にリード端子6を接
合すれば、リード端子6はバンプ5の上面と全面で接続
するため、従来の場合のように機械的応力や熱的応力が
局部的に集中するおそれがない。Further, as shown in FIG. 2, the surface protective film 3
If the bump underlying metal film 4 is formed on the surface of the bump protective layer 3, the upper surface of the surface protective film 3 is naturally flat without steps, and the lower surface of the bump 5 formed on the surface protective film 3 is also flat. . Therefore, the upper surface of the bump 5 is also formed flat without any unevenness. When the lead terminals 6 are joined onto the bumps 5, the lead terminals 6 are entirely connected to the upper surfaces of the bumps 5, so that mechanical stress and thermal stress are locally concentrated as in the conventional case. There is no fear.
【0014】なお、電極パッド下地7の形成について
は、半導体基板1上に集積回路を形成する工程で一般に
使用されるSiO2や多結晶Si等を用いて形成すること
とすれば、電極パッド下地7を形成するための特別の工
程を追加する必要はなく、容易に電極パッド下地7を形
成することができる。Regarding the formation of the electrode pad base 7, if the electrode pad base 7 is formed using SiO 2 or polycrystalline Si which is generally used in the step of forming an integrated circuit on the semiconductor substrate 1, The electrode pad base 7 can be easily formed without adding a special step for forming 7.
【0015】実施例2.この実施例2は、この発明の請
求項2に係る一実施例である。上記実施例1では電極パ
ッド下地7を設けることによって、電極パッド2の上面
と表面保護膜3の上面との間に段差が生じないようにし
たが、この実施例2では、図3に示すように半導体基板
1にドーナツ状の溝1aを形成することによって、電極
パッド2の上面と表面保護膜3の上面との間に段差が生
じないようにしている。この場合、溝1aの内径は表面
保護膜3の開口部3aの大きさとほぼ同一で、溝1aの
深さは表面保護膜3の厚さとほぼ同一とされている。Example 2. The second embodiment is an embodiment according to claim 2 of the present invention. In the first embodiment, the electrode pad base 7 is provided to prevent a step from occurring between the upper surface of the electrode pad 2 and the upper surface of the surface protective film 3. However, in the second embodiment, as shown in FIG. By forming the doughnut-shaped groove 1a in the semiconductor substrate 1, a step is not generated between the upper surface of the electrode pad 2 and the upper surface of the surface protective film 3. In this case, the inner diameter of the groove 1a is substantially the same as the size of the opening 3a of the surface protective film 3, and the depth of the groove 1a is substantially the same as the thickness of the surface protective film 3.
【0016】この構成により、電極パッド2に突起部2
aができることとなり、突起部2aの高さは溝1aの深
さとほぼ同一になる。溝1aの深さは表面保護膜3の厚
さとほぼ同一であるから突起部2aの高さは表面保護膜
3の厚さとほぼ同一となる。従って、表面保護膜3の上
面と電極パッド2の突起部2aの上面との間に段差は生
じず、上記実施例1と同様の効果を奏する。With this structure, the projection 2 is formed on the electrode pad 2.
As a result, the height of the protrusion 2a becomes substantially the same as the depth of the groove 1a. Since the depth of the groove 1a is substantially the same as the thickness of the surface protective film 3, the height of the protrusion 2a is substantially the same as the thickness of the surface protective film 3. Therefore, no step is formed between the upper surface of the surface protective film 3 and the upper surface of the protrusion 2a of the electrode pad 2, and the same effect as that of the above-described first embodiment is obtained.
【0017】[0017]
【発明の効果】この発明は以上のように構成されている
ので、以下に記載されるような効果を奏する。Since the present invention is constructed as described above, it has the following effects.
【0018】この発明の請求項1の半導体装置によれ
ば、半導体基板上の開口部の真下の位置に、開口部と同
一の大きさで表面保護膜と同一の厚さの電極パッド下地
を形成したので、バンプとリード端子との接合強度を上
げることができるとともに、バンプ下地金属膜等が破壊
することがなく信頼性が高くなるという効果がある。According to the semiconductor device of the first aspect of the present invention, the electrode pad base having the same size as the opening and the same thickness as the surface protection film is formed immediately below the opening on the semiconductor substrate. Therefore, there is an effect that the bonding strength between the bump and the lead terminal can be increased, and the bump underlying metal film or the like is not broken, and the reliability is increased.
【0019】この発明の請求項2の半導体装置によれ
ば、開口部の真下の位置の半導体基板上に環状の溝が形
成され、溝の内径は開口部の外径と同一であり、溝の深
さは表面保護膜の厚さと同一であるので、請求項1と同
様の効果を奏する。According to the semiconductor device of the second aspect of the present invention, the annular groove is formed on the semiconductor substrate immediately below the opening, and the inner diameter of the groove is the same as the outer diameter of the opening. Since the depth is the same as the thickness of the surface protective film, the same effect as in claim 1 can be obtained.
【図1】この発明の実施例1におけるバンプ形成前の状
態を示す断面図である。FIG. 1 is a cross-sectional view showing a state before forming bumps according to a first embodiment of the present invention.
【図2】この発明の実施例1を示す断面図である。FIG. 2 is a sectional view showing Embodiment 1 of the present invention.
【図3】この発明の実施例2におけるバンプ形成前の状
態を示す断面図である。FIG. 3 is a cross-sectional view showing a state before forming bumps according to a second embodiment of the present invention.
【図4】従来の半導体装置に用いられているバンプ付近
の構造を示す断面図である。FIG. 4 is a cross-sectional view showing a structure near a bump used in a conventional semiconductor device.
【図5】従来の半導体装置においてバンプとリード端子
とが接合した状態を示す断面図である。FIG. 5 is a cross-sectional view showing a state in which a bump and a lead terminal are joined in a conventional semiconductor device.
1 半導体基板 1a 溝 2 電極パッド 3 表面保護膜 3a 開口部 5 バンプ 7 電極パッド下地 1 Semiconductor Substrate 1a Groove 2 Electrode Pad 3 Surface Protection Film 3a Opening 5 Bump 7 Electrode Pad Base
Claims (2)
に接続された電極パッドと、 前記半導体基板及び前記電極パッドを覆うように形成さ
れ、前記電極パッド上に開口部を有する表面保護膜と、 前記開口部を完全に覆うように形成され、前記集積回路
の入出力信号を外部に接続するためのバンプと、を備え
た半導体装置において、 前記開口部の真下の位置の前記半導体基板上に、前記開
口部と同一の大きさで前記表面保護膜と同一の厚さの電
極パッド下地を形成したことを特徴とする半導体装置。1. A semiconductor substrate on which an integrated circuit is formed, an electrode pad formed on the semiconductor substrate and electrically connected to the integrated circuit, and formed so as to cover the semiconductor substrate and the electrode pad. A semiconductor device having a surface protection film having an opening on the electrode pad, and a bump formed to completely cover the opening and connecting an input / output signal of the integrated circuit to the outside. 2. The semiconductor device according to claim 1, wherein an electrode pad base having the same size as the opening and the same thickness as the surface protective film is formed on the semiconductor substrate directly below the opening.
に接続された電極パッドと、 前記半導体基板及び前記電極パッドを覆うように形成さ
れ、前記電極パッド上に開口部を有する表面保護膜と、 前記開口部を完全に覆うように形成され、前記集積回路
の入出力信号を外部に接続するためのバンプと、を備え
た半導体装置において、 前記開口部の真下の位置の前記半導体基板上に環状の溝
が形成され、この溝の内径は前記開口部の外径と同一で
あり、前記溝の深さは前記表面保護膜の厚さと同一であ
ることを特徴とする半導体装置。2. A semiconductor substrate on which an integrated circuit is formed, an electrode pad formed on the semiconductor substrate and electrically connected to the integrated circuit, and formed so as to cover the semiconductor substrate and the electrode pad. A semiconductor device having a surface protection film having an opening on the electrode pad, and a bump formed to completely cover the opening and connecting an input / output signal of the integrated circuit to the outside. In, an annular groove is formed on the semiconductor substrate at a position directly below the opening, the inner diameter of the groove is the same as the outer diameter of the opening, and the depth of the groove is the thickness of the surface protective film. And a semiconductor device which is the same as the semiconductor device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31521592A JPH06163547A (en) | 1992-11-25 | 1992-11-25 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31521592A JPH06163547A (en) | 1992-11-25 | 1992-11-25 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH06163547A true JPH06163547A (en) | 1994-06-10 |
Family
ID=18062788
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31521592A Pending JPH06163547A (en) | 1992-11-25 | 1992-11-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH06163547A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000228486A (en) * | 1999-02-08 | 2000-08-15 | Rohm Co Ltd | Semiconductor chip and semiconductor device of chip-on- chip structure |
US6657309B1 (en) | 1999-02-08 | 2003-12-02 | Rohm Co., Ltd. | Semiconductor chip and semiconductor device of chip-on-chip structure |
-
1992
- 1992-11-25 JP JP31521592A patent/JPH06163547A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000228486A (en) * | 1999-02-08 | 2000-08-15 | Rohm Co Ltd | Semiconductor chip and semiconductor device of chip-on- chip structure |
US6657309B1 (en) | 1999-02-08 | 2003-12-02 | Rohm Co., Ltd. | Semiconductor chip and semiconductor device of chip-on-chip structure |
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