JP7457763B2 - chip resistor - Google Patents

Description

The present invention relates to chip resistors.

Chip resistors used in electronic devices have been known for a long time. For example, a chip resistor includes two plate-shaped electrodes and a resistor. Resistors are placed on the two electrodes. For example, a chip resistor is disclosed in Patent Document 1.

Japanese Patent Application Publication No. 2007-142148

In conventional chip resistors, it is necessary to maintain the strength of the chip resistor itself, so the thickness of the plate-shaped electrode cannot be made very thin. Therefore, conventional chip resistors cannot be made thinner. Furthermore, there has been a demand for improved heat dissipation of chip resistors.

The present invention was conceived under the above circumstances, and its main objective is to provide a chip resistor that can be made thinner. The present invention was conceived under the above circumstances, and its main objective is to provide a chip resistor that can improve heat dissipation.

According to a first aspect of the present invention, an insulating substrate, a resistor embedded in the substrate, a first electrode electrically connected to the resistor, and a first electrode electrically connected to the resistor and connected to the resistor are electrically connected to the resistor. A chip resistor is provided, which includes a second electrode located in a second direction opposite to the first direction perpendicular to the thickness direction of the substrate with respect to one electrode.

Preferably, the substrate has a substrate surface and a substrate main surface facing opposite to each other in the thickness direction of the substrate, and the resistor is arranged from the substrate surface toward the substrate main surface. I'm completely absorbed in it.

Preferably, the entire resistor overlaps the substrate in the thickness direction of the substrate.

Preferably, the substrate is in direct contact with the resistor.

Preferably, the substrate includes a resin portion and a glass fiber portion located within the resin portion, and the resistor is in direct contact with the glass fiber portion.

Preferably, the resin part is made of epoxy resin.

Preferably, the resin portion constitutes a surface of the substrate and a main surface of the substrate.

Preferably, the maximum thickness of the substrate is between 60 and 300 μm.

Preferably, the substrate has a side surface facing the first direction, and the resistor includes:
The resistor side surface faces the first direction, and the substrate side surface and the resistor side surface are flush with each other.

Preferably, the side surface of the substrate is directly covered by the first electrode.

Preferably, the resistor has a resistor surface and a resistor main surface facing opposite to each other, and the resistor main surface is in direct contact with the substrate.

Preferably, the resistor surface is flush with the substrate surface.

Preferably, the resistor has a thickness of 50 to 200 μm.

Preferably, the device further includes an insulating layer covering the resistor.

Preferably, the insulating layer has an insulating layer surface and an insulating layer main surface facing opposite to each other in the thickness direction of the substrate, and the insulating layer main surface is in direct contact with the substrate and the resistor. There is.

Preferably, the insulating layer has a portion interposed between the resistor and the first electrode, and a portion interposed between the resistor and the second electrode.

Preferably, the first electrode and the second electrode are formed on the surface of the insulating layer.

Preferably, a portion of the surface of the insulating layer is exposed from the first electrode and the second electrode.

Preferably, the thermal conductivity of the insulating layer is 1.0 W/(m·K) to 5.0 W/(m·K).

Preferably, the insulating layer has an insulating layer end face, the substrate has a substrate end face, and the substrate end face and the insulating layer end face both face in a third direction perpendicular to both the thickness direction of the substrate and the first direction, and are flush with each other.

Preferably, the first electrode includes a plating layer formed by plating.

Preferably, the plating layer includes a Cu layer and a Sn layer, and the Cu layer is interposed between the Sn layer and the resistor.

Preferably, the plating layer includes a Ni layer, and the Ni layer is interposed between the Cu layer and the Sn layer.

Preferably, the first electrode includes a base layer in direct contact with the resistor, and the base layer is interposed between the plating layer and the resistor.

Preferably, the underlayer overlaps the resistor when viewed in the thickness direction of the substrate, and has a portion spaced apart from the resistor in the thickness direction.

Preferably, the thickness of the underlayer is 100 to 500 nm.

Preferably, the undercoat layer is formed by PVD, CVD, or printing.

Preferably, the base layer is formed by sputtering.

Preferably, the base layer is made of Ni-Cr.

Preferably, the resistor has a serpentine shape.

Preferably, the resistor is made of manganin, geranin, Ni--Cr alloy, Cu--Ni alloy, or Fe--Cr alloy.

According to the second aspect of the invention, a resistor, an insulating layer covering the resistor, a first electrode electrically connected to the resistor, and a first electrode electrically connected to the resistor and connected to the first electrode. and a second electrode located in a second direction opposite to the first direction, and the first electrode includes a base layer directly in contact with the resistor and a plating layer covering the base layer. A chip resistor is provided, wherein the insulating layer is interposed between the base layer and the resistor.

Preferably, the base layer is interposed between the plating layer and the insulating layer.

Preferably, the dimension of the base layer in the first direction is one quarter or more of the dimension of the resistor in the first direction.

Preferably, the dimension of the base layer in the first direction is one third or more of the dimension of the resistor in the first direction.

Preferably, the dimension of the base layer in the first direction is 600 to 3200 μm.

Preferably, the thickness of the base layer is thinner than the thickness of the resistor.

Preferably, the thickness of the underlayer is 100 to 500 nm.

Preferably, the underlayer is formed by PVD, CVD, or printing.

Preferably, the base layer is formed by sputtering.

Preferably, the base layer is made of Ni-Cr.

Preferably, the plating layer is in direct contact with the insulating layer.

Preferably, the plating layer is in direct contact with a portion of the insulating layer located closer to the second direction than the base layer.

Preferably, the plating layer has a Cu layer and a Sn layer, and the Cu layer is interposed between the Sn layer and the resistor.

Preferably, the plating layer has a Ni layer, and the Ni layer is interposed between the Cu layer and the Sn layer.

Preferably, the resistor has a first resistor side facing the first direction, the underlayer has a first underlayer side facing the first direction, and the first resistor side is flush with the first underlayer side.

Preferably, the first resistor side surface and the first base layer side surface are covered with the plating layer.

Preferably, the resistor has a resistor surface and a resistor main surface facing opposite to each other, and the resistor surface is in direct contact with the insulating layer.

Preferably, the insulating layer has an insulating layer surface and an insulating layer main surface facing in opposite directions, and the insulating layer surface is in direct contact with the base layer.

Preferably, the insulating layer has a portion interposed between the resistor and the first electrode, and a portion interposed between the resistor and the second electrode.

Preferably, the first electrode and the second electrode are formed on the surface of the insulating layer.

Preferably, a portion of the surface of the insulating layer is exposed from the first electrode and the second electrode.

Preferably, the thermal conductivity of the insulating layer is 1.0 W/(m·K) to 5.0 W/(m·K).

Preferably, the device further includes a substrate on which the resistor is arranged.

Preferably, the substrate is made of an insulating material.

Preferably, the substrate has a substrate end surface, the insulating layer has an insulating layer end surface, and both the substrate end surface and the insulating layer end surface are arranged in a thickness direction of the substrate and in the first direction. They face a third direction perpendicular to the same, and are flush with each other.

Preferably, the substrate has a substrate surface and a main substrate surface facing opposite to each other, the resistor is disposed on the substrate surface side, and the substrate main surface is exposed.

Preferably, the thermal conductivity of the material forming the insulating layer is higher than the thermal conductivity of the material forming the substrate.

Preferably, the device further includes a bonding layer interposed between the substrate and the resistor.

Preferably, the bonding layer is made of an epoxy-based material.

Preferably, the resistor has a serpentine shape.

Preferably, the resistor is made of manganin, geranin, Ni--Cr alloy, Cu--Ni alloy, or Fe--Cr alloy.

According to a third aspect of the present invention, there is provided a chip resistor provided by the first aspect or the second aspect of the present invention, a mounting board on which the chip resistor is mounted, and the mounting board and the chip resistor. and a conductive joint interposed between the chip resistor and the chip resistor.

Other features and advantages of the invention will become more apparent from the detailed description given below with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view of a mounting structure of a chip resistor according to a first embodiment of the present invention. FIG. 2 is a view (partially see-through) of the chip resistor taken along line II-II in FIG. 3 is a cross-sectional view of the chip resistor taken along line III-III in FIG. 1 and FIG. 2. FIG. 3 is a cross-sectional view of the chip resistor taken along line IV-IV in FIGS. 1 and 2. FIG. FIG. 3 is a diagram (partially transparent) in which the first plating layer and the second plating layer are omitted from FIG. 2; 2 is a right side view (partially transparent) of the chip resistor shown in FIG. 1. FIG. FIG. 2 is a left side view (partially see-through) of the chip resistor shown in FIG. 1 . FIG. 2 is a front view of the chip resistor shown in FIG. 2 is a rear view of the chip resistor shown in FIG. 1. FIG. 2 is a plan view showing a step in a method of manufacturing the chip resistor shown in FIG. 1 . 11 is a sectional view taken along the line XI-XI in FIG. 10. FIG. 11 is a back view showing one step following FIG. 10. FIG. 13 is a sectional view taken along line XIII-XIII in FIG. 12. FIG. 13 is a back view showing one step following FIG. 12. FIG. 15 is a cross-sectional view taken along line XV-XV in FIG. 14. 15 is a back view showing one step following FIG. 14. FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 16. It is a sectional view showing a first modification of the first embodiment of the present invention. It is a sectional view showing the 2nd modification of the 1st embodiment of the present invention. FIG. 3 is a cross-sectional view of a chip resistor mounting structure according to a second embodiment of the present invention. 21 is a view (partially transparent) of the chip resistor taken along line XXI-XXI in FIG. 20; FIG. 22 is a cross-sectional view of the chip resistor taken along the line XXII-XXII in FIGS. 20 and 21. FIG. FIG. 22 is a cross-sectional view of the chip resistor taken along line XXIII-XXIII in FIGS. 20 and 21. FIG. 22 is a view (partially see-through) in which the first plating layer and the second plating layer are omitted from FIG. 21 . 21 is a right side view (partially transparent) of the chip resistor shown in FIG. 20. FIG. 21 is a left side view (partially transparent) of the chip resistor shown in FIG. 20. FIG. 21 is a front view of the chip resistor shown in FIG. 20. FIG. 21 is a rear view of the chip resistor shown in FIG. 20. FIG. 21 is a cross-sectional view showing a step in a method of manufacturing the chip resistor shown in FIG. 20. FIG. 30 is a plan view showing one step following FIG. 29; 31 is a sectional view taken along line XXXI-XXXI in FIG. 30. FIG. 31 is a back view showing one step following FIG. 30. FIG. This is a cross-sectional view taken along line XXXIII-XXXIII in Figure 32. 33 is a back view showing one step following FIG. 32. FIG. 35 is a cross-sectional view taken along line XXXV-XXXV in FIG. 34. FIG. 35 is a back view showing one step following FIG. 34. FIG. 37 is a cross-sectional view taken along line XXXVII-XXXVII in FIG. 36. FIG. It is a sectional view showing the first modification of the second embodiment of the present invention. FIG. 11 is a cross-sectional view showing a second modified example of the second embodiment of the present invention.

Embodiments of the present invention will be specifically described below with reference to the drawings.

First Embodiment
A first embodiment of the present invention will be described with reference to FIGS. 1 to 19. FIG.

FIG. 1 is a cross-sectional view of a chip resistor mounting structure according to a first embodiment of the present invention.

A chip resistor mounting structure 891 shown in the figure includes a chip resistor 100, a mounting board 893, and a conductive joint 895.

The mounting substrate 893 is, for example, a printed wiring board. The mounting substrate 893 includes, for example, an insulating substrate and a pattern electrode (not shown) formed on the insulating substrate. The insulating substrate is, for example, a glass epoxy resin substrate. The chip resistor 100 is mounted on the mounting substrate 893. A conductive joint 895 is interposed between the chip resistor 100 and the mounting substrate 893. The conductive joint 895 joins the chip resistor 100 and the mounting substrate 893. The conductive joint 895 is, for example, made of solder.

FIG. 2 is a view (partially transparent) of the chip resistor taken along line II-II in FIG. FIG. 3 is a cross-sectional view of the chip resistor taken along line III--III in FIGS. 1 and 2. FIG. 4 is a cross-sectional view of the chip resistor taken along line IV-IV in FIGS. 1 and 2. FIG. 5 is a diagram in which the first plating layer and the second plating layer are omitted from FIG. 2 (partially transparent). FIG. 6 is a right side view (partially transparent) of the chip resistor shown in FIG. FIG. 7 is a left side view (partially transparent) of the chip resistor shown in FIG. FIG. 8 is a front view of the chip resistor shown in FIG. 1. FIG. 9 is a rear view of the chip resistor shown in FIG. 1.

A chip resistor 100 shown in these figures includes a substrate 1 , a resistor 2 , a first electrode 4 , a second electrode 5 , and an insulating layer 6 .

The substrate 1 is plate-shaped. The substrate 1 is insulating or conductive. When the substrate 1 is insulating, the material constituting the substrate 1 includes, for example, resin or ceramic. When the material constituting the substrate 1 includes resin, the resin constituting the substrate 1 is, for example, an epoxy resin. When the material constituting the substrate 1 includes ceramic, examples of such ceramic include Al2O3, AlN, and SiC. When the substrate 1 is conductive, the material forming the substrate 1 is, for example, Cu or Ag. Note that in this embodiment, the substrate 1 is a glass epoxy resin substrate.

The substrate 1 has a substrate surface 11, a substrate main surface 12, a first substrate side surface 13, a second substrate side surface 14, a first substrate end surface 15, and a second substrate end surface 16.

The substrate surface 11, the main substrate surface 12, the first substrate side surface 13, the second substrate side surface 14, the first substrate end surface 15, and the second substrate end surface 16 are all flat. As shown in FIG. 1, the vertical direction in the figure is defined as the thickness direction Z1 of the substrate 1. As shown in FIG. As shown in FIG. 2, the right direction in the figure is a first direction X1, the left direction is a second direction X2, the upward direction is a third direction X3, and the downward direction is a fourth direction X4. The maximum thickness (maximum dimension in the thickness direction Z1) of the substrate 1 is, for example, 60 to 300 μm. The thickness direction Z1 is orthogonal to the first direction X1, the second direction X2, the third direction X3, and the fourth direction X4. Further, the first direction X1 and the second direction X2 are orthogonal to the third direction X3 and the fourth direction X4, respectively.

The dimension of the chip resistor 100 in the first direction X1 is, for example, 5 to 10 mm, and the dimension of the chip resistor 100 in the third direction X3 is, for example, 2 to 10 mm.

The substrate surface 11 and the substrate main surface 12 face in opposite directions. The first substrate side surface 13 faces in the first direction X1. The second substrate side surface 14 faces in the second direction X2. That is, the first substrate side surface 13 and the second substrate side surface 14 face in opposite directions. The first substrate end surface 15 faces in the third direction X3. The second substrate end surface 16 faces in the fourth direction X4. That is, the first substrate end surface 15 and the second substrate end surface 16 face in opposite directions.

As described above, in this embodiment, the substrate 1 is a glass epoxy resin substrate. Therefore, the substrate 1 includes a glass fiber portion 191 and a resin portion 192.

The resin portion 192 defines the outer shape of the substrate 1. The resin portion 192 is made of, for example, epoxy resin. The resin portion 192 constitutes the substrate surface 11 and the substrate main surface 12.

The glass fiber section 191 is made of glass fiber. Specifically, the glass fiber section 191 is a layer of glass fiber cloth. The glass fiber section 191 constitutes a part of the first substrate side surface 13, a part of the second substrate side surface 14, a part of the first substrate end surface 15, and a part of the second substrate end surface 16.

Unlike this embodiment, the substrate 1 does not have to be a glass epoxy resin substrate. In this case, the substrate 1 does not include the glass fiber portion 191.

As shown in FIG. 1, the resistor 2 is disposed on the substrate 1. Specifically, the resistor 2 is disposed on the substrate surface 11 side of the substrate 1. The thickness (dimension in the thickness direction Z1) of the resistor 2 is, for example, 50 to 200 μm. In this embodiment, the resistor 2 is serpentine-shaped when viewed in the thickness direction Z1. The resistor 2 being serpentine-shaped is preferable in that the resistance value of the resistor 2 can be increased. Unlike this embodiment, the resistor 2 may not be serpentine-shaped, but may be, for example, a band-like shape extending in the X1-X2 direction. The resistor 2 is made of a metal resistive material, and examples of such metal resistive materials include manganin, geranine, Ni-Cr alloy, Cu-Ni alloy, and Fe-Cr alloy.

As shown in FIGS. 1 and 3, the resistor 2 has a resistor surface 21, a resistor main surface 22, a first resistor side surface 23, and a second resistor side surface 24. The resistor surface 21, the resistor main surface 22, the first resistor side surface 23, and the second resistor side surface 24 are all flat.

The resistor surface 21 and the resistor main surface 22 face opposite to each other. The resistor surface 21 faces in the same direction as the substrate surface 11 (ie, downward in FIG. 1). On the other hand, the resistor main surface 22 faces in the same direction as the substrate main surface 12 (that is, upward in FIG. 1). The main surface 22 of the resistor faces toward the substrate 1 . The first resistor side surface 23 faces in the first direction X1. In this embodiment, the first resistor side surface 23 is flush with the first substrate side surface 13. The second resistor side surface 24 faces the second direction X2. In this embodiment, the second resistor side surface 24 is flush with the second substrate side surface 14.

In this embodiment, the resistor 2 is embedded in the substrate 1. Specifically, the chip resistor 100 has the following configuration.

The resistor 2 is recessed into the substrate 1 from the substrate surface 11 toward the main substrate surface 12 . In the thickness direction Z1, the entire resistor 2 overlaps the substrate 1. The resistor 2 is in direct contact with the substrate 1. Furthermore, in this embodiment in which the substrate 1 is a glass epoxy resin substrate, the resistor 2 is in direct contact with the glass fiber portion 191 of the substrate 1.

The resistor surface 21 is flush with the substrate surface 11 of the substrate 1 . This is suitable for forming an insulating layer 6, which will be described later, on the resistor surface 21 and the substrate surface 11. The main surface 22 of the resistor is in direct contact with the substrate 1 . Furthermore, in this embodiment where the substrate 1 is a glass epoxy resin substrate, the resistor main surface 22 is in direct contact with the glass fiber portion 191 of the substrate 1.

Unlike this embodiment, the resistor 2 and the substrate 1 do not need to be in direct contact with each other. For example, the resistor 2 may be embedded in the substrate 1 with a bonding layer interposed between the resistor 2 and the substrate 1. The resistor 2 does not need to be in direct contact with the glass fiber portion 191.

An insulating layer 6 covers the resistor 2. Insulating layer 6 is in direct contact with resistor 2 and substrate 1 . The insulating layer 6 is in direct contact with the resistor surface 21 of the resistor 2 and the substrate surface 11 of the substrate 1 . The insulating layer 6 exposes a portion of the resistor 2 on the first direction X1 side and a portion of the resistor 2 on the second direction X2 side. The insulating layer 6 is made of, for example, a thermosetting material. The dimensions of the insulating layer 6 in the third direction X3 are the same as the dimensions of the substrate 1 in the third direction X3. The maximum thickness (maximum dimension in the thickness direction Z1) of the insulating layer 6 is, for example, 20 to 60 μm. The insulating layer 6 is made of resin, for example. In order to easily dissipate the heat generated in the resistor 2 to the outside of the chip resistor 100, it is preferable to use a material with high thermal conductivity as the material forming the insulating layer 6. The thermal conductivity of the insulating layer 6 is preferably higher than the thermal conductivity of the material forming the substrate 1 (in this embodiment, the material forming the resin portion 192). The thermal conductivity of the insulating layer 6 is preferably 1.0 W/(m·K) to 5.0 W/(m·K), for example.

The insulating layer 6 includes an insulating layer surface 61, an insulating layer main surface 62, a first insulating layer side surface 63, a second insulating layer side surface 64, a first insulating layer end surface 65, a second insulating layer end surface 66, has.

The insulating layer surface 61 and the insulating layer main surface 62 face in opposite directions. The insulating layer surface 61 faces in the same direction as the resistor surface 21 faces (i.e., downward in FIG. 1). The first electrode 4 and the second electrode 5 are formed on the insulating layer surface 61. A part of the insulating layer surface 61 (a region of the insulating layer surface 61 sandwiched between the first electrode 4 and the second electrode 5) is exposed from the first electrode 4 and the second electrode 5. The insulating layer main surface 62 faces in the same direction as the resistor main surface 22 faces (i.e., upward in FIG. 1). In this embodiment, the insulating layer main surface 62 is in direct contact with the resistor 2 and the substrate 1. Specifically, the insulating layer main surface 62 is in direct contact with the resistor surface 21 and the substrate surface 11. The first insulating layer side surface 63 faces in the first direction X1. The second insulating layer side surface 64 faces in the second direction X2. The first insulating layer end surface 65 faces the third direction X3. In this embodiment, the first insulating layer end surface 65 is flush with the first substrate end surface 15. The second insulating layer end surface 66 faces the fourth direction X4. The second insulating layer end surface 66 is flush with the second substrate end surface 16.

The first electrode 4 is electrically connected to the resistor 2. The first electrode 4 is for supplying power to the resistor 2 from the mounting substrate 893 on which the chip resistor 100 is mounted. The first electrode 4 is in direct contact with the resistor 2. In this embodiment, the first electrode 4 is in direct contact with the resistor surface 21 of the resistor 2. In this embodiment, the first electrode 4 further covers the first resistor side surface 23 of the resistor 2 and the insulating layer 6. In this embodiment, the insulating layer 6 is interposed between the first electrode 4 and the resistor 2. In this embodiment, the first electrode 4 further does not cover the main surface 12 of the substrate. Unlike this embodiment, the first electrode 4 may cover the main surface 12 of the substrate. As shown in FIG. 1, in the mounting structure 891, the first electrode 4 is in direct contact with the conductive joint 895 and is electrically connected to the wiring pattern (not shown) on the mounting substrate 893 via the conductive joint 895.

The first electrode 4 includes a first base layer 41 and a first plating layer 43.

The first base layer 41 is in direct contact with the resistor 2 . In this embodiment, the first base layer 41 is formed in order to form the first plating layer 43 on the insulating layer 6 by plating. The first base layer 41 is in direct contact with a portion of the resistor surface 21 exposed from the insulating layer 6 . The first base layer 41 overlaps the resistor 2 when viewed in the thickness direction Z1 of the substrate 1 . Further, the first base layer 41 has a portion spaced apart from the resistor 2 in the thickness direction Z1. An insulating layer 6 is interposed between the first base layer 41 and the resistor 2 . The first base layer 41 is interposed between the first plating layer 43 and the insulating layer 6. In this embodiment, it is preferable that the first base layer 41 has a larger dimension in the first direction X1. Preferably, the dimension of the first base layer 41 in the first direction X1 is one quarter or more of the dimension of the resistor 2 in the first direction X1, and more preferably, the dimension of the resistor 2 in the first direction X1. This is more than one-third of the total. The dimension of the first base layer 41 in the first direction X1 is, for example, 600 to 3200 μm. The thickness of the first base layer 41 is thinner than the thickness of the resistor 2. The first base layer 41 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In this embodiment, the first base layer 41 is formed by sputtering of PVD. The thickness of the first base layer 41 is, for example, 100 to 500 nm. The first base layer 41 contains, for example, Ni and Cr.

The first base layer 41 has a first base layer side surface 413. The first base layer side surface 413 faces the first direction X1. In this embodiment, the first base layer side surface 413 is flush with the first substrate side surface 13 and the first resistor side surface 23 .

The first plating layer 43 directly covers the first base layer 41. The first plating layer 43 is formed on the resistor 2. The first plating layer 43 is in direct contact with the insulating layer 6. The first plating layer 43 is in direct contact with a portion of the insulating layer 6 located closer to the second direction X2 than the first base layer 41 . In the chip resistor 100 before being mounted on the mounting board 893, the first plating layer 43 is exposed to the outside. Therefore, in the mounting structure 891, as shown in FIG. (omitted). Note that in this embodiment, the first plating layer 43 covers the first resistor side surface 23 of the resistor 2 . This is preferable in that a solder fillet can be formed in the conductive joint 895.

Specifically, in this embodiment, the first plating layer 43 includes a Cu layer 43a, a Ni layer 43b, and a Sn layer 43c. The Cu layer 43a directly covers the first base layer 41. The Ni layer 43b directly covers the Cu layer 43a. Sn layer 43c directly covers Ni layer 43b. The Sn layer 43c is exposed to the outside. In the mounting structure 891 of the chip resistor 100, a conductive joint 895 (solder in this embodiment) is attached to the Sn layer 43c. The thickness of the Cu layer 43a is, for example, 10 to 50 μm, the thickness of the Ni layer 43b is, for example, 1 to 10 μm, and the thickness of the Sn layer 43c is, for example, 1 to 10 μm. Unlike this embodiment, the first plating layer 43 does not need to include the Ni layer 43b.

The second electrode 5 is located on the second direction X2 side with respect to the first electrode 4. The second electrode 5 is electrically connected to the resistor 2. The second electrode 5 is for supplying power to the resistor 2 from a mounting board 893 on which the chip resistor 100 is mounted. The second electrode 5 is in direct contact with the resistor 2. In this embodiment, the second electrode 5 is in direct contact with the resistor surface 21 of the resistor 2. In this embodiment, the second electrode 5 further covers the second resistor side surface 24 of the resistor 2 and the insulating layer 6. In this embodiment, the insulating layer 6 is interposed between the second electrode 5 and the resistor 2. In this embodiment, the second electrode 5 further does not cover the substrate main surface 12 side. Unlike this embodiment, the second electrode 5 may cover the substrate main surface 12. As shown in FIG. 1, in the mounting structure 891, the second electrode 5 is in direct contact with the conductive joint 895 and is electrically connected to the wiring pattern (not shown) on the mounting board 893 via the conductive joint 895.

The second electrode 5 includes a second base layer 51 and a second plating layer 53.

The second base layer 51 is in direct contact with the resistor 2 . In this embodiment, the second base layer 51 is formed in order to form the second plating layer 53 on the insulating layer 6 by plating. The second base layer 51 is in direct contact with a portion of the resistor surface 21 exposed from the insulating layer 6 . An insulating layer 6 is interposed between the second base layer 51 and the resistor 2 . The second base layer 51 is interposed between the second plating layer 53 and the insulating layer 6. In this embodiment, it is preferable that the second base layer 51 has a larger dimension in the second direction X2. Preferably, the dimension of the second base layer 51 in the second direction X2 is one quarter or more of the dimension of the resistor 2 in the second direction X2, and more preferably the dimension of the resistor 2 in the second direction X2. This is more than one-third of the total. The dimension of the second base layer 51 in the second direction X2 is, for example, 600 to 3200 μm. The thickness of the second base layer 51 is thinner than the thickness of the resistor 2. The second base layer 51 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In this embodiment, the second base layer 51 is formed by sputtering of PVD. The thickness of the second base layer 51 is, for example, 0.5 to 1.0 nm. The second base layer 51 contains, for example, Ni and Cr.

The second base layer 51 has a second base layer side surface 514. The second base layer side surface 514 faces the second direction X2. In this embodiment, the second base layer side surface 514 is flush with the second substrate side surface 14 and the second resistor side surface 24 .

The second plating layer 53 directly covers the second base layer 51. The second plating layer 53 is formed on the resistor 2. The second plating layer 53 is in direct contact with the insulating layer 6. The second plating layer 53 is in direct contact with a portion of the insulating layer 6 located closer to the first direction X1 than the second base layer 51 . In the chip resistor 100 before being mounted on the mounting board 893, the second plating layer 53 is exposed to the outside. Therefore, in the mounting structure 891, as shown in FIG. (omitted). Note that in this embodiment, the second plating layer 53 covers the second resistor side surface 24 of the resistor 2 . This is preferable in that a solder fillet can be formed in the conductive joint 895.

Specifically, in this embodiment, the second plating layer 53 includes a Cu layer 53a, a Ni layer 53b, and a Sn layer 53c. The Cu layer 53a directly covers the second base layer 51. The Ni layer 53b directly covers the Cu layer 53a. Sn layer 53c directly covers Ni layer 53b. The Sn layer 53c is exposed to the outside. In the mounting structure 891 of the chip resistor 100, a conductive joint 895 (solder in this embodiment) is attached to the Sn layer 53c. The thickness of the Cu layer 53a is, for example, 10 to 50 μm, the thickness of the Ni layer 53b is, for example, 1 to 10 μm, and the thickness of the Sn layer 53c is, for example, 1 to 10 μm. Unlike this embodiment, the second plating layer 53 does not need to include the Ni layer 53b.

Next, we will briefly explain the manufacturing method of the chip resistor 100.

First, as shown in FIGS. 10 and 11, a collection sheet 850 is prepared. Aggregate sheet 850 includes substrate sheet 810 and resistor aggregate 820. In this embodiment, the aggregate sheet 850 is formed such that the resistor aggregates 820 are embedded in the substrate sheet 810. The aggregate sheet 850 is formed using, for example, a vacuum press. In assembly sheet 850, resistor assembly 820 is completely fixed to substrate sheet 810.

The substrate sheet 810 becomes the substrate 1 described above. The resistor assembly 820 becomes the resistor 2 described above. Therefore, in the assembly sheet 850, the resistor assembly 820 is in direct contact with the glass fiber portion 191.

Further, the resistor assembly 820 has a plurality of portions that are to become the above-mentioned resistor 2. In this embodiment, in order to form the serpentine-shaped resistor 2, a plurality of serpentine-shaped portions are formed in the resistor assembly 820 in advance by etching or a punching die.

Next, the resistance value of the resistor 2 in the resistor assembly 820 is adjusted. The resistance value of the resistor 2 is adjusted, for example, by grinding the resistor assembly 820.

Next, as shown in FIGS. 12 and 13, an insulating film 860 is formed. The insulating film 860 becomes the above-mentioned insulating layer 6. The insulating film 860 is formed in a plurality of strips extending in one direction. The insulating film 860 is formed, for example, by printing or coating. A portion of the resistor assembly 820 is exposed from the insulating film 860.

Next, as shown in FIG. 14 and FIG. 15, a conductive material 840 is laminated on the resistor assembly 820. The conductive material 840 becomes the first underlayer 41 or the second underlayer 51 described above. The process of laminating the conductive material 840 uses PVD or CVD. Examples of PVD used to laminate the conductive material 840 include sputtering. In this embodiment, in the process of laminating the conductive material 840, the conductive material 840 is laminated in a strip-like shape along the direction in which the insulating film 860 extends. Therefore, a part of the insulating film 860 is exposed from the laminated conductive material 840. In order to laminate the conductive material 840 in a strip-like shape, for example, masking may be performed. The conductive material 840 is, for example, Ni or Cr.

Next, as shown in FIGS. 16 and 17, a plurality of solid pieces 886 are obtained by cutting the resistance assembly 820. In this embodiment, the aggregate sheet 850 (resistance aggregate 820 and substrate sheet 810) is cut at once. To obtain the solid piece 886, for example, punching or dicing is performed. In this embodiment, punching is performed to obtain the solid piece 886.

By cutting when obtaining the solid piece 886, the above-mentioned first substrate side surface 13, second substrate side surface 14, first substrate end surface 15, second substrate end surface 16, first resistor side surface 23, second resistor side surface 24, A first base layer side surface 413, a second base layer side surface 514, a first insulating layer end surface 65, and a second insulating layer end surface 66 are formed. By cutting the substrate sheet 810, the resistor assembly 820, etc. at the same time, the first substrate side surface 13, the first resistor side surface 23, and the first base layer side surface 413 are flush with each other. Similarly, by cutting the substrate sheet 810, the resistor assembly 820, etc. at the same time, the second substrate side surface 14, the second resistor side surface 24, and the second base layer side surface 514 are flush with each other. Become. Similarly, by this cutting, the first substrate end surface 15 and the first insulating layer end surface 65 become flush with each other. Similarly, by this cutting, the second substrate end surface 16 and the second insulating layer end surface 66 become flush with each other.

Next, the first plating layer 43 (Cu layer 43a, Ni layer 43b, and Sn layer 43c) and the second plating layer 53 (Cu layer 53a, Ni layer 53b, and A Sn layer 53c) is formed. For example, barrel plating is used to form the first plating layer 43 and the second plating layer 53. Through the above steps, the manufacture of the chip resistor 100 is completed.

Next, we will explain the effects of this embodiment.

In this embodiment, the resistor 2 is embedded in the substrate 1. According to such a configuration, it is possible to reduce the overall size of the assembly of the substrate 1 and the resistor 2 in the thickness direction Z1 of the substrate 1. This allows the chip resistor 100 to be made thinner.

Further, when manufacturing the chip resistor 100, an assembly sheet 850 in which the resistance assembly 820 is embedded in the substrate sheet 810 can be used. Therefore, in order to manufacture the chip resistor 100, it is sufficient to prepare the assembly sheet 850, and the effort of attaching the resistance assembly 820 to the substrate sheet 810 can be reduced. This contributes to increased efficiency in manufacturing the chip resistor 100.

In this embodiment, the thermal conductivity of the insulating layer 6 is 1.0 W/(m·K) to 5.0 W/(m·K), which is relatively high. According to such a configuration, the heat generated in the resistor 2 is easily released to the outside of the chip resistor 100 via the insulating layer 6. Therefore, chip resistor 100 can be prevented from becoming excessively high temperature.

In this embodiment, the first electrode 4 includes a first base layer 41 that is in direct contact with the resistor 2 and a first plating layer 43 that covers the first base layer 41. Insulating layer 6 is interposed between first base layer 41 and resistor 2 . According to such a configuration, it is easy to form the first plating layer 43 on the insulating layer 6. Therefore, the area of the first electrode 4 can be increased. If the area of the first electrode 4 can be increased, the heat generated in the resistor 2 can be easily released to the mounting board 893 via the first electrode 4. That is, the heat dissipation of the chip resistor 100 can be improved.

In this embodiment, the substrate 1 is made of an insulating material. With such a configuration, there is no need to use a relatively thick Cu electrode. Therefore, the effort required to process the Cu electrode can be reduced. This contributes to increased efficiency in manufacturing the chip resistor 100.

In this embodiment, both the substrate 1 and the mounting substrate 893 are glass epoxy resin substrates. In such a configuration, the coefficients of thermal expansion of each of the substrate 1 and the mounting substrate 893 are approximately the same. Therefore, even if the substrate 1 thermally expands while the chip resistor 100 is in use, it is thought that the mounting substrate 893 also thermally expands at a similar rate. Therefore, during use of the chip resistor 100, problems that may occur due to the influence of thermal expansion (for example, the chip resistor 100 breaks) can be prevented.

<First Modification of First Embodiment>
A first modification of the first embodiment of the present invention will be described with reference to FIG.

FIG. 18 is a sectional view showing a first modification of the first embodiment of the present invention.

The chip resistor 101 shown in the figure is different from the chip resistor 100 in that the first resistor side surface 23 of the resistor 2 and the second resistor side surface 24 of the resistor 2 are covered with the substrate 1. Mainly different. The other points are the same as the chip resistor 100, so the explanation will be omitted.

The chip resistor 101 also provides the same effects as described regarding the chip resistor 100.

<Second modification of the first embodiment>
A second modification of the first embodiment of the present invention will be described using FIG. 19.

FIG. 19 is a sectional view showing a second modification of the first embodiment of the present invention.

The chip resistor 102 shown in the figure has the following points: the first plating layer 43 has a surface flush with the first base layer side surface 413 of the first base layer 41, and the second plating layer 53 has the following features: The main difference from the chip resistor 100 is that the second base layer 51 has a surface that is flush with the second base layer side surface 514 . The other points are the same as the chip resistor 100, so the explanation will be omitted. Note that in order to manufacture the chip resistor 102, a plating layer is formed before the cutting process of the aggregate sheet 850 described with reference to FIGS. 16 and 17.

The chip resistor 102 also provides the same effects as described regarding the chip resistor 100.

<Second embodiment>
A second embodiment of the present invention will be described using FIGS. 20 to 39.

FIG. 20 is a cross-sectional view of a chip resistor mounting structure according to a second embodiment of the present invention.

A chip resistor mounting structure 892 shown in the figure includes a chip resistor 200, a mounting board 893, and a conductive joint 895.

Since the description given in the first embodiment can be applied to the mounting board 893 and the conductive joint part 895, the description will be omitted in this embodiment.

FIG. 21 is a view (partially transparent) of the chip resistor taken along line XXI-XXI in FIG. 20. FIG. 22 is a cross-sectional view of the chip resistor taken along line XXII-XXII in FIGS. 20 and 21. FIG. 23 is a cross-sectional view of the chip resistor taken along line XXIII-XXIII in FIGS. 20 and 21. FIG. 24 is a diagram in which the first plating layer and the second plating layer are omitted from FIG. 21 (partially transparent). FIG. 25 is a right side view (partially transparent) of the chip resistor shown in FIG. 20. FIG. 26 is a left side view (partially transparent) of the chip resistor shown in FIG. 20. FIG. 27 is a front view of the chip resistor shown in FIG. 20. FIG. 28 is a rear view of the chip resistor shown in FIG. 20.

A chip resistor 200 shown in these figures includes a substrate 1 , a resistor 2 , a bonding layer 3 , a first electrode 4 , a second electrode 5 , and an insulating layer 6 .

The substrate 1 is plate-shaped. The substrate 1 is insulating or conductive. When the substrate 1 is insulating, the material constituting the substrate 1 includes, for example, resin or ceramic. When the material constituting the substrate 1 includes resin, the resin constituting the substrate 1 is, for example, an epoxy resin. When the material constituting the substrate 1 includes ceramic, examples of such ceramic include Al2O3, AlN, and SiC. When the substrate 1 is conductive, the material forming the substrate 1 is, for example, Cu or Ag. Note that in this embodiment, the substrate 1 is a glass epoxy resin substrate.

The substrate 1 has a substrate surface 11, a substrate main surface 12, a first substrate side surface 13, a second substrate side surface 14, a first substrate end surface 15, and a second substrate end surface 16.

The substrate surface 11, the main substrate surface 12, the first substrate side surface 13, the second substrate side surface 14, the first substrate end surface 15, and the second substrate end surface 16 are all flat. As shown in FIG. 20, the vertical direction in the figure is defined as the thickness direction Z1 of the substrate 1. As shown in FIG. 21, the right direction in the figure is defined as a first direction X1, the left direction is defined as a second direction X2, the upward direction is defined as a third direction X3, and the downward direction is defined as a fourth direction X4. The maximum thickness (maximum dimension in the thickness direction Z1) of the substrate 1 is, for example, 60 to 300 μm. The thickness direction Z1 is orthogonal to the first direction X1, the second direction X2, the third direction X3, and the fourth direction X4. Further, the first direction X1 and the second direction X2 are orthogonal to the third direction X3 and the fourth direction X4, respectively.

The dimension of the chip resistor 200 in the first direction X1 is, for example, 5 to 10 mm, and the dimension of the chip resistor 200 in the third direction X3 is, for example, 2 to 10 mm.

The substrate surface 11 and the substrate main surface 12 face in opposite directions. The first substrate side surface 13 faces in the first direction X1. The second substrate side surface 14 faces in the second direction X2. That is, the first substrate side surface 13 and the second substrate side surface 14 face in opposite directions. The first substrate end surface 15 faces in the third direction X3. The second substrate end surface 16 faces in the fourth direction X4. That is, the first substrate end surface 15 and the second substrate end surface 16 face in opposite directions.

As shown in FIG. 20, the resistor 2 is placed on the substrate 1. Specifically, the resistor 2 is arranged on the substrate surface 11 side of the substrate 1. The thickness of the resistor 2 (dimension in the thickness direction Z1) is, for example, 50 to 200 μm. In this embodiment, the resistor 2 has a serpentine shape when viewed in the thickness direction Z1. It is preferable that the resistor 2 has a serpentine shape since the resistance value of the resistor 2 can be increased. Unlike this embodiment, the resistor 2 does not have a serpentine shape, but may have a strip shape extending in the X1-X2 direction, for example. The resistor 2 is made of a metal resistance material, and examples of such metal resistance materials include manganin, geranin, Ni--Cr alloy, Cu--Ni alloy, and Fe--Cr alloy.

As shown in FIGS. 21 and 22, the resistor 2 has a resistor surface 21, a resistor main surface 22, a first resistor side surface 23, and a second resistor side surface 24. The resistor surface 21, the resistor main surface 22, the first resistor side surface 23, and the second resistor side surface 24 are all flat.

The resistor surface 21 and the resistor main surface 22 face opposite to each other. The resistor surface 21 faces in the same direction as the substrate surface 11 (ie, downward in FIG. 20). On the other hand, the resistor main surface 22 faces in the same direction as the substrate main surface 12 (ie, upward in FIG. 20). The main surface 22 of the resistor faces toward the substrate 1 . The first resistor side surface 23 faces in the first direction X1. In this embodiment, the first resistor side surface 23 is flush with the first substrate side surface 13. The second resistor side surface 24 faces the second direction X2. In this embodiment, the second resistor side surface 24 is flush with the second substrate side surface 14.

Bonding layer 3 is interposed between substrate 1 and resistor 2 . Specifically, bonding layer 3 is interposed between substrate surface 11 of substrate 1 and resistor 2 . Bonding layer 3 bonds resistor 2 to substrate surface 11 . It is preferable that the bonding layer 3 is made of an insulating material. Examples of such insulating materials include epoxy-based materials. The thickness of the bonding layer 3 (dimension in the thickness direction Z1) is, for example, 30 to 100 μm. As shown in FIGS. 20 and 22, in this embodiment, the bonding layer 3 covers the entire surface of the substrate surface 11.

Unlike this embodiment, the bonding layer 3 may be formed only on a part of the substrate surface 11. For example, the bonding layer 3 may be formed only in a region of the substrate surface 11 that overlaps with the resistor 2.

As shown in FIGS. 20 and 22, the bonding layer 3 has a bonding layer surface 31 and a bonding layer main surface 32 facing opposite to each other. Bonding layer surface 31 faces in the same direction as substrate surface 11 (ie, downward in FIG. 20). Bonding layer surface 31 is in direct contact with resistor 2 . The main surface 32 of the bonding layer is in direct contact with the substrate 1 .

An insulating layer 6 covers the resistor 2. The insulating layer 6 is placed on the resistor 2 and the substrate 1 with the bonding layer 3 in between. The insulating layer 6 is in direct contact with the resistor surface 21 of the resistor 2 . The insulating layer 6 exposes a portion of the resistor 2 on the first direction X1 side and a portion of the resistor 2 on the second direction X2 side. The insulating layer 6 is made of, for example, a thermosetting material. The dimensions of the insulating layer 6 in the third direction X3 are the same as the dimensions of the substrate 1 in the third direction X3. The maximum thickness (maximum dimension in the thickness direction Z1) of the insulating layer 6 is, for example, 60 to 150 μm. The insulating layer 6 is made of resin, for example. In order to easily dissipate the heat generated in the resistor 2 to the outside of the chip resistor 200, it is preferable to use a material having high thermal conductivity as the material constituting the insulating layer 6. The thermal conductivity of the insulating layer 6 is preferably higher than that of the material forming the substrate 1. The thermal conductivity of the insulating layer 6 is preferably 1.0 W/(m·K) to 5.0 W/(m·K), for example.

The insulating layer 6 includes an insulating layer surface 61, an insulating layer main surface 62, a first insulating layer side surface 63, a second insulating layer side surface 64, a first insulating layer end surface 65, a second insulating layer end surface 66, has.

The insulating layer surface 61 and the insulating layer main surface 62 face opposite sides. The insulating layer surface 61 faces in the same direction as the resistor surface 21 (ie, downward in FIG. 20). A first electrode 4 and a second electrode 5 are formed on the insulating layer surface 61. A part of the insulating layer surface 61 (a region of the insulating layer surface 61 sandwiched between the first electrode 4 and the second electrode 5) is exposed from the first electrode 4 and the second electrode 5. The main surface 62 of the insulating layer faces in the same direction as the main surface 22 of the resistor (ie, upward in FIG. 20). In this embodiment, it is in direct contact with the bonding layer 3. Specifically, the main surface 62 of the insulating layer is in direct contact with the surface 31 of the bonding layer. The first insulating layer side surface 63 faces the first direction X1. The second insulating layer side surface 64 faces the second direction X2. The first insulating layer end surface 65 faces the third direction X3. In this embodiment, the first insulating layer end surface 65 is flush with the first substrate end surface 15. The second insulating layer end surface 66 faces the fourth direction X4. The second insulating layer end surface 66 is flush with the second substrate end surface 16.

The first electrode 4 is electrically connected to the resistor 2 . The first electrode 4 is for supplying power to the resistor 2 from the mounting board 893 on which the chip resistor 200 is mounted. The first electrode 4 is in direct contact with the resistor 2. In this embodiment, the first electrode 4 is in direct contact with the resistor surface 21 of the resistor 2 . In this embodiment, the first electrode 4 further covers the first resistor side surface 23 of the resistor 2 and the insulating layer 6. In this embodiment, an insulating layer 6 is interposed between the first electrode 4 and the resistor 2. Furthermore, in this embodiment, the first electrode 4 does not cover the substrate main surface 12 side. Unlike this embodiment, the first electrode 4 may cover the main surface 12 of the substrate. As shown in FIG. 20, in the mounting structure 892, the first electrode 4 is in direct contact with the conductive joint 895, and is connected to the wiring pattern (not shown) on the mounting board 893 via the conductive joint 895. Conductive.

As shown in FIG. 20, the first electrode 4 includes a first base layer 41 and a first plating layer 43.

The first base layer 41 is in direct contact with the resistor 2 . In this embodiment, the first base layer 41 is formed in order to form the first plating layer 43 on the insulating layer 6 by plating. The first base layer 41 is in direct contact with a portion of the resistor surface 21 exposed from the insulating layer 6 . The first base layer 41 overlaps the resistor 2 when viewed in the thickness direction Z1 of the substrate 1 . Further, the first base layer 41 has a portion spaced apart from the resistor 2 in the thickness direction Z1. An insulating layer 6 is interposed between the first base layer 41 and the resistor 2 . The first base layer 41 is interposed between the first plating layer 43 and the insulating layer 6. In this embodiment, it is preferable that the first base layer 41 has a larger dimension in the first direction X1. Preferably, the dimension of the first base layer 41 in the first direction X1 is one quarter or more of the dimension of the resistor 2 in the first direction X1, and more preferably, the dimension of the resistor 2 in the first direction X1. This is more than one-third of the total. The dimension of the first base layer 41 in the first direction X1 is, for example, 600 to 3200 μm. The thickness of the first base layer 41 is thinner than the thickness of the resistor 2. The first base layer 41 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In this embodiment, the first base layer 41 is formed by sputtering of PVD. The thickness of the first base layer 41 is, for example, 0.5 to 1.0 nm. The first base layer 41 contains, for example, Ni and Cr.

The first base layer 41 has a first base layer side surface 413. The first base layer side surface 413 faces the first direction X1. In this embodiment, the first base layer side surface 413 is flush with the first substrate side surface 13 and the first resistor side surface 23 .

The first plating layer 43 directly covers the first base layer 41. The first plating layer 43 is formed on the resistor 2. The first plating layer 43 is in direct contact with the insulating layer 6. The first plating layer 43 is in direct contact with a portion of the insulating layer 6 located closer to the second direction X2 than the first base layer 41 . In the chip resistor 200 before being mounted on the mounting board 893, the first plating layer 43 is exposed to the outside. Therefore, in the mounting structure 892, as shown in FIG. (omitted). Note that in this embodiment, the first plating layer 43 covers the first resistor side surface 23 of the resistor 2 . This is preferable in that a solder fillet can be formed in the conductive joint 895.

Specifically, in this embodiment, the first plating layer 43 has a Cu layer 43a, a Ni layer 43b, and a Sn layer 43c. The Cu layer 43a directly covers the first underlayer 41. The Ni layer 43b directly covers the Cu layer 43a. The Sn layer 43c directly covers the Ni layer 43b. The Sn layer 43c is exposed to the outside. In the mounting structure 892 of the chip resistor 200, a conductive joint 895 (solder in this embodiment) is attached to the Sn layer 43c. The thickness of the Cu layer 43a is, for example, 10 to 50 μm, the thickness of the Ni layer 43b is, for example, 1 to 10 μm, and the thickness of the Sn layer 43c is, for example, 1 to 10 μm. Unlike this embodiment, the first plating layer 43 does not need to include the Ni layer 43b.

The second electrode 5 is located on the second direction X2 side with respect to the first electrode 4. The second electrode 5 is electrically connected to the resistor 2 . The second electrode 5 is for supplying power to the resistor 2 from the mounting board 893 on which the chip resistor 200 is mounted. The second electrode 5 is in direct contact with the resistor 2. In this embodiment, the second electrode 5 is in direct contact with the resistor surface 21 of the resistor 2 . In this embodiment, the second electrode 5 further covers the second resistor side surface 24 of the resistor 2 and the insulating layer 6. In this embodiment, an insulating layer 6 is interposed between the second electrode 5 and the resistor 2. Furthermore, in this embodiment, the second electrode 5 does not cover the substrate main surface 12 side. Unlike this embodiment, the second electrode 5 may cover the main surface 12 of the substrate. As shown in FIG. 20, in the mounting structure 892, the second electrode 5 is in direct contact with the conductive joint 895, and is connected to the wiring pattern (not shown) on the mounting board 893 via the conductive joint 895. Conductive.

As shown in FIG. 20, the second electrode 5 includes a second base layer 51 and a second plating layer 53.

The second base layer 51 is in direct contact with the resistor 2 . In this embodiment, the second base layer 51 is formed in order to form the second plating layer 53 on the insulating layer 6 by plating. The second base layer 51 is in direct contact with a portion of the resistor surface 21 exposed from the insulating layer 6 . An insulating layer 6 is interposed between the second base layer 51 and the resistor 2 . The second base layer 51 is interposed between the second plating layer 53 and the insulating layer 6. In this embodiment, it is preferable that the second base layer 51 has a larger dimension in the second direction X2. Preferably, the dimension of the second base layer 51 in the second direction X2 is one quarter or more of the dimension of the resistor 2 in the second direction X2, and more preferably the dimension of the resistor 2 in the second direction X2. This is more than one-third of the total. The dimension of the second base layer 51 in the second direction X2 is, for example, 600 to 3200 μm. The thickness of the second base layer 51 is thinner than the thickness of the resistor 2. The second base layer 51 may be formed by PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), or printing. In this embodiment, the second base layer 51 is formed by sputtering of PVD. The thickness of the second base layer 51 is, for example, 0.5 to 1.0 nm. The second base layer 51 contains, for example, Ni and Cr.

The second base layer 51 has a second base layer side surface 514. The second base layer side surface 514 faces the second direction X2. In this embodiment, the second base layer side surface 514 is flush with the second substrate side surface 14 and the second resistor side surface 24 .

The second plating layer 53 directly covers the second base layer 51. The second plating layer 53 is formed on the resistor 2. The second plating layer 53 is in direct contact with the insulating layer 6. The second plating layer 53 is in direct contact with a portion of the insulating layer 6 located closer to the first direction X1 than the second base layer 51 . In the chip resistor 200 before being mounted on the mounting board 893, the second plating layer 53 is exposed to the outside. Therefore, in the mounting structure 892, as shown in FIG. (omitted). Note that in this embodiment, the second plating layer 53 covers the second resistor side surface 24 of the resistor 2 . This is preferable in that a solder fillet can be formed in the conductive joint 895.

Specifically, in this embodiment, the second plating layer 53 has a Cu layer 53a, a Ni layer 53b, and a Sn layer 53c. The Cu layer 53a directly covers the second underlayer 51. The Ni layer 53b directly covers the Cu layer 53a. The Sn layer 53c directly covers the Ni layer 53b. The Sn layer 53c is exposed to the outside. In the mounting structure 892 of the chip resistor 200, a conductive joint 895 (solder in this embodiment) is attached to the Sn layer 53c. The thickness of the Cu layer 53a is, for example, 10 to 50 μm, the thickness of the Ni layer 53b is, for example, 1 to 10 μm, and the thickness of the Sn layer 53c is, for example, 1 to 10 μm. Unlike this embodiment, the second plating layer 53 does not need to include the Ni layer 53b.

Next, a method for manufacturing the chip resistor 200 will be briefly described.

First, as shown in FIG. 29, a substrate sheet 810 is prepared. The substrate sheet 810 will become the substrate 1 described above. The substrate sheet 810 is made of an insulating material. The substrate sheet 810 is made of ceramic or resin. Examples of ceramic include Al2O3, AlN, and SiC. The substrate sheet 810 has a sheet front surface 811 and a sheet back surface 812 that face in opposite directions.

Next, as shown in FIGS. 30 and 31, a bonding material 830 is bonded to the sheet surface 811 of the substrate sheet 810. The bonding material 830 becomes the bonding layer 3 described above. In this embodiment, the bonding material 830 is a thermally conductive adhesive sheet. In the state shown in FIG. 31, a bonding material 830 is temporarily thermocompressed onto the sheet surface 811 of the substrate sheet 810.

Next, as shown in FIGS. 30 and 31, a resistance assembly 820 is bonded to the sheet surface 811 using a bonding material 830. In this embodiment, in the state shown in FIGS. 30 and 31, the resistance assembly 820 is temporarily press-bonded to the bonding material 830. The resistor assembly 820 has a plurality of portions that are to become the resistor 2 described above. In this embodiment, in order to form a serpentine-shaped resistor 2, a plurality of serpentine-shaped parts are formed on the resistance assembly 820 by etching or a punching die before the resistance assembly 820 is bonded to the sheet surface 811. ing. Next, the resistor assembly 820 is subjected to a trimming process (not shown). This is for adjusting the resistance value of the resistor 2. The trimming process is performed using, for example, a laser, sandblasting, a dicer, a grinder, or the like.

Unlike this embodiment, in order to bond the resistance assembly 820 to the sheet surface 811 of the substrate sheet 810, a liquid adhesive may be used as the bonding material 830 instead of using a sheet-like member.

Next, as shown in FIGS. 32 and 33, an insulating film 860 is formed. The insulating film 860 becomes the above-mentioned insulating layer 6. The insulating film 860 is formed in a plurality of strips extending in one direction. The insulating film 860 is formed, for example, by printing or coating. A portion of the resistor assembly 820 is exposed from the insulating film 860.

Next, as shown in FIGS. 34 and 35, a conductive material 840 is laminated on the resistance assembly 820. The conductive material 840 becomes the first base layer 41 or the second base layer 51 described above. The step of stacking the conductive material 840 uses PVD or CVD. Examples of the PVD used for stacking the conductive material 840 include sputtering. In this embodiment, in the step of laminating the conductive material 840, the conductive material 840 is laminated in a strip shape along the direction in which the insulating film 860 extends. Therefore, a portion of the insulating film 860 is exposed from the stacked conductive material 840. Note that in order to stack the conductive material 840 in a band-like manner, for example, masking may be performed. The conductive material 840 is, for example, Ni or Cr.

Next, as shown in FIGS. 36 and 37, a plurality of solid pieces 886 are obtained by cutting the resistance assembly 820. In this embodiment, the resistor assembly 820 and the substrate sheet 810 are cut at once. To obtain the solid piece 886, for example, punching or dicing is performed. In this embodiment, punching is performed to obtain the solid piece 886.

By cutting when obtaining the solid piece 886, the above-mentioned first substrate side surface 13, second substrate side surface 14, first substrate end surface 15, second substrate end surface 16, first resistor side surface 23, second resistor side surface 24, A first base layer side surface 413, a second base layer side surface 514, a first insulating layer end surface 65, and a second insulating layer end surface 66 are formed. By cutting the substrate sheet 810, the resistor assembly 820, etc. at the same time, the first substrate side surface 13, the first resistor side surface 23, and the first base layer side surface 413 are flush with each other. Similarly, by cutting the substrate sheet 810, the resistor assembly 820, etc. at the same time, the second substrate side surface 14, the second resistor side surface 24, and the second base layer side surface 514 are flush with each other. Become. Similarly, by this cutting, the first substrate end surface 15 and the first insulating layer end surface 65 become flush with each other. Similarly, by this cutting, the second substrate end surface 16 and the second insulating layer end surface 66 become flush with each other.

Next, the first plating layer 43 (Cu layer 43a, Ni layer 43b, and Sn layer 43c) and the second plating layer 53 (Cu layer 53a, Ni layer 53b, and A Sn layer 53c) is formed. For example, barrel plating is used to form the first plating layer 43 and the second plating layer 53. By going through the above steps, the chip resistor 200
The production of is completed.

Next, the effects of this embodiment will be explained.

In this embodiment, the thermal conductivity of the insulating layer 6 is 1.0 W/(m·K) to 5.0 W/(m·K), which is relatively high. According to such a configuration, the heat generated in the resistor 2 is easily released to the outside of the chip resistor 200 via the insulating layer 6. Therefore, chip resistor 200 can be prevented from becoming excessively high temperature.

In this embodiment, the first electrode 4 includes a first underlayer 41 that is in direct contact with the resistor 2, and a first plating layer 43 that covers the first underlayer 41. The insulating layer 6 is interposed between the first underlayer 41 and the resistor 2. With this configuration, it is easy to form the first plating layer 43 on the insulating layer 6. Therefore, the area of the first electrode 4 can be increased. If the area of the first electrode 4 can be increased, it becomes easier to dissipate heat generated in the resistor 2 to the mounting board 893 via the first electrode 4. In other words, the heat dissipation of the chip resistor 200 can be improved. This prevents the chip resistor 200 from becoming excessively hot.

In this embodiment, the substrate 1 is made of an insulating material. With such a configuration, there is no need to use a relatively thick Cu electrode. Therefore, the effort required to process the Cu electrode can be reduced. This contributes to increasing the efficiency of manufacturing the chip resistor 200.

In this embodiment, both the substrate 1 and the mounting substrate 893 are glass epoxy resin substrates. In such a configuration, the coefficients of thermal expansion of each of the substrate 1 and the mounting substrate 893 are approximately the same. Therefore, even if the substrate 1 thermally expands while the chip resistor 200 is in use, it is thought that the mounting substrate 893 will also thermally expand at a similar rate. Therefore, during use of the chip resistor 200, problems that may occur due to the influence of thermal expansion (for example, the chip resistor 200 breaks) can be prevented.

<First modification of the second embodiment>
A first modification of the second embodiment of the present invention will be described using FIG. 38.

FIG. 38 is a sectional view showing a first modification of the second embodiment of the present invention.

The chip resistor 201 shown in the figure is different from the chip resistor 201 in that the first resistor side surface 23 of the resistor 2 and the second resistor side surface 24 of the resistor 2 are covered with the insulating layer 6. The main difference is The other points are the same as the chip resistor 200, so the explanation will be omitted.

Chip resistor 201 also provides the same effects as those described for chip resistor 200.

<Second modification of second embodiment>
A second modification of the second embodiment of the present invention will be described using FIG. 39.

FIG. 39 is a sectional view showing a second modification of the second embodiment of the present invention.

The chip resistor 202 shown in the figure has the following points: the first plating layer 43 has a surface that is flush with the first base layer side surface 413 of the first base layer 41, and the second plating layer 53 has the following features: The main difference from the chip resistor 200 is that the second base layer 51 has a surface that is flush with the second base layer side surface 514 . The other points are the same as the chip resistor 200, so the explanation will be omitted. In order to manufacture the chip resistor 202, a plating layer is formed before the step of cutting the substrate 1 sheet 810 and the resistor assembly 820 as described with reference to FIGS. 36 and 37.

The chip resistor 202 also provides the same effects as described regarding the chip resistor 200.

The present invention is not limited to the embodiments described above. The specific configuration of each part of the present invention can be changed in design in various ways.

1 Substrate 100, 101, 102, 200, 201, 202 Chip resistor 11 Substrate surface 12 Substrate main surface 13 First substrate side surface 14 Second substrate side surface 15 First substrate end surface 16 Second substrate end surface 191 Glass fiber part 192 Resin part 2 Resistor 21 Resistor surface 22 Resistor main surface 23 First resistor side surface 24 Second resistor side surface 3 Bonding layer 31 Bonding layer surface 32 Bonding layer main surface 4 First electrode 41 First base layer 413 First base layer side surface 43 First plating layer 43a Cu layer 43b Ni layer 43c Sn layer 5 Second electrode 51 Second base layer 514 Second base layer side surface 53 Second plating layer 53a Cu layer 53b Ni layer 53c Sn layer 6 Insulating layer 61 Insulating layer surface 62 Insulating layer main surface 63 First insulating layer side surface 64 Second insulating layer side surface 65 First insulating layer end surface 66 Second insulating layer end surface 810 Substrate sheet 811 Sheet surface 812 Sheet back surface 820 Resistor assembly 830 Joint material 840 Conductive material 850 Assembly sheet 860 Insulating film 886 Solid pieces 891, 892 Mounting structure 893 Mounting substrate 895 Conductive joint X1 First direction X2 Second direction X3 Third direction X4 Fourth direction Z1 Thickness direction

Claims (8)

A substrate;
A resistor;
a bonding layer interposed between the substrate and the resistor;
an insulating layer covering the resistor;
a first electrode located on a side opposite to the substrate with respect to the insulating layer in a thickness direction of the substrate, electrically connected to the resistor, and located on a first direction side;
a second electrode located on an opposite side of the insulating layer to the substrate in a thickness direction of the substrate, electrically connected to the resistor, and located on a second direction side opposite to the first direction with respect to the first electrode;
the substrate has a first substrate side surface facing the first direction;
the resistor has a first resistor side surface that is a surface formed by a portion of the resistor that is located closest to the first direction and faces the first direction,
A chip resistor, wherein the first resistor side is located closer to the second direction than the first substrate side and is covered with the insulating layer. The insulating layer has a first insulating layer outer surface facing in the first direction,
The chip resistor according to claim 1, wherein the outer side surface of the first insulating layer and the side surface of the first substrate are flush with each other. the first electrode includes a first base layer that is in direct contact with the resistor and a first plating layer that covers the first base layer;
the first plating layer includes a first metal layer directly covering the first underlayer, a second metal layer directly covering the first metal layer, and a third metal layer directly covering the second metal layer;
The chip resistor according to claim 2 , wherein the third metal layer overlaps a portion of an outer surface of the first insulating layer when viewed in the first direction. The chip resistor according to claim 3, wherein the second metal layer overlaps a part of the outer surface of the first insulating layer when viewed in the first direction. The substrate has a second substrate side face facing the second direction,
The resistor has a second resistor side face facing the second direction,
5. The chip resistor according to claim 1, wherein the second resistor side surface is located closer to the first direction than the second substrate side surface and is covered with the insulating layer. The insulating layer has a second insulating layer outer surface facing in the second direction,
The chip resistor according to claim 5, wherein the outer side surface of the second insulating layer and the side surface of the second substrate are flush with each other. the second electrode includes a second base layer that is in direct contact with the resistor and a second plating layer that covers the second base layer,
the second plating layer includes a fourth metal layer directly covering the second underlayer, a fifth metal layer directly covering the fourth metal layer, and a sixth metal layer directly covering the fifth metal layer;
The chip resistor according to claim 6 , wherein the sixth metal layer overlaps a portion of an outer surface of the second insulating layer when viewed in the first direction. The chip resistor according to claim 7, wherein the fifth metal layer overlaps a part of the outer surface of the second insulating layer when viewed in the first direction.

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