JP7067702B2 - Gallium nitride based semiconductor device and its manufacturing method - Google Patents

Description

The present invention relates to a gallium nitride based semiconductor device having excellent interfacial characteristics between a semiconductor layer and an insulator layer, and a method for manufacturing the same.

Gallium nitride-based semiconductors are attracting attention not only as short-wavelength optical devices such as blue semiconductor lasers, but also as high-frequency power devices due to their high dielectric breakdown electric field strength, high thermal conductivity, and high electron saturation rate. There is. For example, in the case of a GaN semiconductor, its bandgap is 3.4 eV, which is more than twice the saturated electron velocity (V _sat ) compared to Si and GaAs, about 10 times that of Si, and about 7.5 times that of GaAs. It has a dielectric breakdown electric field strength (E _c ). When compared with the Johnson index expressed by V _sat · E _c / 2π, which is often used as an index to compare the performance of high-frequency and high-power amplifiers using semiconductors, GaN is about 27 times that of Si, and GaAs. Even when compared, the size is about 15 times larger, and from these facts, GaN is recognized as a semiconductor having an overwhelming advantage.

However. A gate leak current may be generated between the gate and drain due to the reaction between the oxide on the surface of the semiconductor and the adhered metal.

In order to suppress the generation of this gate leak current, there is an embodiment in which an insulating film such as a SiN film (silicon nitride film) or a SiO ₂ film (silicon oxide film) is deposited on the surface of a gallium nitride based semiconductor. Due to the presence of oxides on the surface of the semiconductor of the system, an interface state is generated at the interface between the surface of the semiconductor and the insulating film, and trap sites are easily introduced. Therefore, in such a mode of MISFET or MOSFET, there arises a problem that the characteristics are likely to change depending on the frequency.

In order to avoid such a problem, in Patent Document 1, gallium nitride represented by (In _x Al _1-x ) _y Ga _1-y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1) A thermal oxide gallium oxide (Ga ₂ O ₃ ) thermal oxide film is formed on the surface of the semiconductor of the system, and an insulating film such as SiO ₂ by plasma CVD is formed on the formed thermal oxide film, and further, the insulating film is formed. It has a structure in which a gate electrode is formed on the gate electrode.

Japanese Patent Application Laid-Open No. 2003-258258

Surf. Sci. Pp.532-535, pp.759-763 (2003)

The present invention solves the above-mentioned problems of gate leakage current and deterioration of frequency characteristics in a gallium nitride based semiconductor device, particularly a MISFET or MOSFET using a gallium nitride based semiconductor, and has a semiconductor layer and an insulator layer. It is an object of the present invention to provide a gallium nitride based semiconductor device having excellent interfacial characteristics and a method for manufacturing the same.

According to one aspect of the present invention, the semiconductor device comprises a semiconductor layer containing gallium nitride, a gate electrode, and an insulator layer provided between the semiconductor layer and the gate electrode, and gallium nitride is a single crystal. The insulator layer has at least a first insulating film containing a gallium oxide crystal in a portion adjacent to the semiconductor layer, and the gallium oxide crystal has a gallium nitride crystal lattice and an in-plane lattice constant a. It is consistent.

According to a specific example of the present invention, in a semiconductor device, gallium nitride is a single crystal having a wurtzite structure, and gallium oxide crystals are hexagonal crystals having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. It is a crystal.

According to a specific example of the present invention, in a semiconductor device, gallium nitride is a single crystal having a wurtzite structure, and gallium oxide crystals are cubic crystals having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. It is a crystal.

According to a specific example of the present invention, in a semiconductor device, gallium nitride is a single crystal having a wurtzite structure, and gallium oxide crystals are hexagonal crystals having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. It is a cubic crystal.

According to one specific example of the present invention, in a semiconductor device, at least one crystal of gallium oxide is selected from the group consisting of gallium oxide having an ε structure, gallium oxide having a γ structure, and a combination thereof.

According to a specific example of the present invention, in a semiconductor device, the crystal planes of gallium oxide crystals are arranged so as to be aligned with the crystal planes of the semiconductor layer.

According to a specific example of the present invention, in the semiconductor device, the film thickness of the first insulating film is not less than the thickness of the monoatomic layer of the gallium oxide crystal and not more than 10 nm.

According to a specific example of the present invention, the film thickness of the first insulating film is 5 nm or less in the semiconductor device.

According to a specific example of the present invention, in the semiconductor device, the first insulating film is a gallium oxide crystal in which the gallium nitride crystal lattice and the in-plane lattice constant a are matched, or the a-axis lattice constant is 0. In the case of having a gallium oxide crystal which is at least one of hexagonal crystal and cubic crystal of 28 nm or more and 0.34 nm or less, the ratio of the volume occupied by the gallium oxide crystal in the first insulating film is 95% or more. Is.

According to a specific example of the present invention, in a semiconductor device, the first insulating film has a combination of gallium oxide having an ε structure and gallium oxide having a γ structure, and the first insulating film has an oxidation of the ε structure. The volume ratio of the gallium crystals is 70% or more and 90% or less, and the residual portion of the first insulating film is occupied by the gallium oxide crystals having a γ structure.

According to a specific example of the present invention, in the first insulating film of the semiconductor device, the volume ratio of the gallium oxide crystal having the ε structure is 80%, and the ratio of the gallium oxide crystal having the γ structure is 80%. It is 20%.

According to one specific example of the present invention, in a semiconductor device, when the first insulating film has a combination of gallium oxide having an ε structure and gallium oxide having a γ structure, the oxidation of the ε structure in the first insulating film. The volume ratio of gallium and gallium oxide having a γ structure is 95% or more.

According to a specific example of the present invention, in the semiconductor device, the insulator layer includes a second insulating film provided between the gate electrode and the first insulating film, and the second insulating film is aluminum. An element consisting of (Al), silicon (Si), hafnium (Hf), zirconium (Zr), tantalum (Ta), titanium (Ti), gallium (Ga), yttrium (Y), scandium (Sc), and rare earth elements. It has an oxide, nitride, or oxynitride of at least one element selected from the group.

According to a specific example of the present invention, in a semiconductor device, the gate electrodes are aluminum (Al), titanium (Ti), tungsten (W), platinum (Pt), gold (Au), silver (Ag), and ruthenium (Ag). It has at least one selected from the group consisting of Ru), rhodium (Rh), palladium (Pd), nickel (Ni), tin (Sn), zinc (Zn) and poly-Si.

According to a specific example of the present invention, the method for manufacturing a semiconductor device includes a semiconductor layer preparation step for preparing a semiconductor layer, an insulator layer forming step for forming an insulator layer, and a gate electrode forming for forming a gate electrode. It has at least a process.

According to one specific example of the present invention, in the method for manufacturing a semiconductor device, in the insulator layer forming step, the semiconductor layer is formed of sulfuric acid, hydrogen peroxide solution, ammonia, fluoroacid, hydrochloric acid, nitric acid, phosphoric acid, and hydroxylation. It comprises the step of forming a first insulating film by surface treatment with at least one selected from the group consisting of potassium.

According to a specific example of the present invention, in the method for manufacturing a semiconductor device, in the insulator layer forming step, the semiconductor layer is subjected to plasma oxidation treatment and / or ozone oxidation treatment at 500 ° C. or lower to obtain a first insulation. Includes steps to form a membrane.

According to one specific example of the present invention, in the method for manufacturing a semiconductor device, the insulator layer forming step is performed on the semiconductor layer at 700 ° C. or lower by using an electron beam vapor deposition method and / or an MBE method at 870 ° C. First insulation using the CVD method below, using the HVPE method below 700 ° C, using the ALD method below 500 ° C, and / or using the sputtering method below 500 ° C. Including the step of laminating the film.

According to a specific example of the present invention, in the method for manufacturing a semiconductor device, in the insulator layer forming step, gallium oxide crystals are formed on the semiconductor layer by heat treatment at 500 ° C. or higher and 870 ° C. or lower, and then etching is performed. The step of forming the first insulating film by reducing the thickness of the gallium oxide crystal to 10 nm or less is included.

According to the present invention, by reducing the number of trap sites due to the interface state between the semiconductor layer and the insulator layer, a gallium nitride based semiconductor device having good electrical characteristics and a method for manufacturing the same are provided. Here, the gallium nitride based semiconductor device means a semiconductor device having a semiconductor layer containing gallium nitride.

It should be noted that other objects, features and advantages of the present invention will be clarified from the following description of the embodiments of the present invention with respect to the accompanying drawings.

It is sectional drawing of the semiconductor device as 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of 1st Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of 2nd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of 3rd Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of 3rd Embodiment of this invention. It is the schematic sectional drawing of the MIS capacitor as an Example of this invention. FIG. 7 is a characteristic diagram showing an XPS Ga _3d spectrum after surface treatment in the manufacturing process of the MIS capacitor of FIG. 7. FIG. 7 is a partially enlarged cross-sectional view of the MIS capacitor of FIG. 7 on the Miller index [1-100] plane by TEM (Transmission Electron Microscope). FIG. 7 is a partially enlarged cross-sectional view of the MIS capacitor shown in FIG. 7 on the Miller index [11-20] plane by TEM. It is a characteristic diagram which shows the CV (capacity-voltage) characteristic of the MIS capacitor of FIG. (100) It is a structural diagram of the cubic crystal of gallium oxide seen from the plane. (111) It is a structural diagram of the cubic crystal of gallium oxide seen from the plane. It is a structural diagram which shows the arrangement of the oxygen atom in the cut end when the cubic gallium oxide is sliced by the (111) plane. It is sectional drawing which shows the manufacturing process of the semiconductor device of 4th Embodiment of this invention. It is sectional drawing which shows the manufacturing process of the semiconductor device of 4th Embodiment of this invention. FIG. 3 is a cross-sectional TEM observation image and an FFT diagram showing the structure of the insulating film of the present invention.

Hereinafter, examples of the present invention will be described with reference to the drawings, but the present invention is not limited to these examples.

<Embodiment 1>
In the first embodiment, the gallium nitride based semiconductor device 100, which is a horizontal MISFET, will be described with reference to FIG.
The semiconductor device 100 is an insulator provided between a semiconductor layer (channel layer) 101 containing gallium nitride formed on a gallium nitride self-supporting substrate 111, a gate electrode 105, and the semiconductor layer 101 and the gate electrode 105. A layer (gate insulating film) 102 is provided.
The gallium nitride of the semiconductor layer 101 is preferably a single crystal, and the gallium nitride is more preferably a single crystal having a wurtzite structure. Further, it is more preferable that the semiconductor layer 101 is made of single crystal gallium nitride.

The insulator layer 102 includes a first insulating film 103 in a portion adjacent to the semiconductor layer 101. Further, the insulator layer 102 may include a second insulating film 104 provided between the gate electrode 105 and the first insulating film 103. Here, the second insulating film 104 may be a single-layer film or a laminated film composed of a plurality of films.
Further, the semiconductor device 100 may include a source region 107 and a drain region 108 by injecting impurities into the semiconductor layer 101 in order to form a MISFET. For example, when the semiconductor layer 101 is n-type gallium nitride, the source region 107 and the drain region 108 are formed by injecting a p-type impurity into the semiconductor layer 101.
The semiconductor device 100 includes a source electrode 109 and a drain electrode 110 on the source region 107 and the drain region 108, respectively.

The first insulating film 103 includes a gallium oxide crystal in which the in-plane lattice constant a is matched with the gallium nitride crystal lattice constituting the semiconductor layer 101.
Here, the fact that the in-plane lattice constants a match means that the difference between the crystal lattice constants a of gallium nitride and gallium oxide is within ± 15%. When the difference between the crystal lattice constants a of gallium nitride and gallium oxide is within ± 15%, the generation of trap sites in the insulator layer 102 is suppressed.

As the single crystal of gallium nitride constituting the semiconductor layer 101, a single crystal having a wurtzite structure can be preferably mentioned because of the stability of the crystal. When a single crystal having a wurtzite structure is used as the gallium nitride constituting the semiconductor layer 101, the gallium oxide crystal constituting the first insulating film 103 has an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. It is preferably at least one of hexagonal crystals and cubic crystals.

Here, the a-axis lattice constant in the present invention refers to a normal a-axis lattice constant in the case of a hexagonal crystal, and in the case of a cubic crystal, the crystal lattice at the cut end when sliced on the (111) plane. Refers to the lattice constant of.

FIG. 11 is a view of a cubic gallium oxide, for example, a crystal of γ-Ga ₂ O ₃ viewed from the (100) plane. In the figure, 1 is an oxygen atom (O) and 2 is a gallium atom (Ga). show. Hexagonal oxygen atom configurations are not observed on the plane (inplane) sliced on the (100) plane, and lattice matching does not occur with the GaN semiconductor in contact with this plane.

FIG. 12 is a view of a cubic gallium oxide, for example, a crystal of γ-Ga ₂ O ₃ viewed from the (111) plane. Here, 1 in FIG. 12 represents an oxygen atom (O) and 2 represents a gallium atom (Ga), as in the case of FIG. 11. Then, when this crystal is sliced on the (111) plane and at a place where oxygen atom 1 is located, the arrangement of atoms located at the cut end is shown in FIG. As can be seen from FIG. 13, the oxygen atom 1 (in this inplane) at this cut has the same crystal arrangement (crystal lattice 11) as the hexagonal crystal.
In the present invention, a1 shown in 21 of FIG. ₁₃ , a2 shown in 22 and a3 shown in 23 are used as the lattice constants of the a _- axis in this inplane _, but since they form a substantially regular hexagon, a The values of ₁ , a ₂ and a ₃ are almost equal and are expressed by the lattice constant a.

The crystal structure of gallium nitride in the wurtzite structure is a hexagonal crystal with an a-axis lattice constant of 0.319 nm. The inventor has found that when gallium oxide has a hexagonal structure having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, the lattices are aligned and the generation of trap sites is sufficiently suppressed. Further, the inventor found that when gallium oxide is a (111) plane cubic crystal, gallium nitride and a lattice having a wurtzite structure having a hexagonal structure are sufficiently sufficient when the lattice constant of the a-axis is 0.28 nm or more and 0.34 nm or less. It was found that the occurrence of trap sites was sufficiently suppressed. Furthermore, the inventor found that when gallium oxide is composed of hexagonal gallium oxide having a lattice constant of 0.28 nm or more and 0.34 nm or less and gallium oxide having a cubic structure, the lattice is matched and the trap site is trapped. It was found that the occurrence of was sufficiently suppressed.

Further, the first insulating film 103 may be composed of gamma oxide having an ε structure or gamma oxide having a γ structure, or may be composed of a combination of gamma oxide having an ε structure and gamma oxide having a γ structure.
Here, gallium oxide having an ε structure has a hexagonal crystal structure, and its a-axis crystal lattice constant is 0.290 nm. Further, gallium oxide having a γ structure has a cubic crystal structure, and its a-axis crystal lattice constant on the (111) plane is 0.291 nm.
Incidentally, the thermally oxidized gallium oxide shown in Patent Document 1 is β-Ga ₂ O ₃ because it is formed in a dry oxygen atmosphere at 900 ° C. β-Ga ₂ O ₃ is a monoclinic system, and its lattice constants are a = 1.2214 nm, b = 0.33071 nm, and c = 0.57981 nm. Further, α = γ = 90 ° and β = 108.83 °, and β-Ga ₂ O ₃ is lattice-matched with gallium nitride having a wurtzite structure.

The crystal planes of gallium oxide constituting the first insulating film 103 are preferably arranged so as to be aligned with the crystal planes of the semiconductor layer 101. For example, the first insulating film 103 may be formed so that the crystal planes of gallium oxide, which is a hexagonal single crystal, are aligned on the crystal planes of the Miller index [0001] of gallium nitride in the semiconductor layer 101.

The film thickness of the first insulating film 103 is preferably 10 nm or less. This is because when the size is larger than 10 nm, lattice mismatch is likely to occur in the formed gallium oxide crystals, and trap sites increase. Further, the film thickness of the first insulating film 103 is more preferably 5 nm or less. As described above, it is preferable to reduce the film thickness of the first insulating film 103 as much as possible. On the other hand, the film thickness of the first insulating film 103 needs to be at least the thickness of the monoatomic layer of gallium oxide in order to ensure that gallium oxide is formed on the semiconductor layer 101. Further, when the film thickness of the first insulating film 103 is set to be equal to or larger than the thickness of the diatomic layer of gallium oxide, there is an effect that the generation of defective portions is reduced.

When the first insulating film 103 has a gallium nitride crystal whose in-plane lattice constant a is matched with gallium nitride, when the gallium nitride and the in-plane lattice constant a of the gallium oxide in the first insulating film 103 are matched with each other, The ratio of the volume occupied by the crystals is preferably 95% or more. When the first insulating film 103 has a gallium oxide crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less, which is at least one of hexagonal crystals and cubic crystals, the first insulating film 103 The volume ratio of the gallium oxide crystal having at least one of hexagonal crystals and cubic crystals having a lattice constant of 0.28 nm or more and 0.34 nm or less in the a-axis is preferably 95% or more. With this configuration, the generation of trap sites in the gate insulating film 102 formed between the gallium nitride based semiconductor layer 101 and the gate electrode 105 is sufficiently suppressed.

When the first insulating film 103 is composed of a combination of ε-structured gallium oxide and γ-structured gallium oxide, the ratio of ε-structured gallium oxide to the volume of the first insulating film 103 is 70% or more. 90% or less, the ratio of gallium oxide having a γ structure is 10% or more and 30% or less, and the ratio of the total of gallium oxide having an ε structure and gamma oxide having a γ structure is 95% or more and 100% or less. It is preferable that it is. For example, in the volume of the first insulating film 103, the ratio of gallium oxide having an ε structure is 80%, and the remaining 20% of the first insulating film 103 is occupied by gamma oxide having a γ structure. May be good. Further, in the volume of the first insulating film 103, the proportion of gallium oxide having an ε structure is 78%, the proportion of gallium oxide having a γ structure is 18%, and the proportion of gallium oxide having an ε structure and the gamma structure is γ. The ratio of the total of ε-structured gallium oxide and γ-structured gallium oxide may be 96% so that the ratio of non-gamma oxide is 4%. With this configuration, the generation of trap sites in the gate insulating film 102 formed between the gallium nitride based semiconductor layer 101 and the gate electrode 105 is sufficiently suppressed.

The second insulating film 104 of the insulator layer 102 is provided on the first insulating film 103, and is provided with aluminum (Al), silicon (Si), hafnium (Hf), zirconium (Zr), tantalum (Ta), and titanium. It is formed from an oxide, nitride, or oxynitride of at least one element selected from the group of elements consisting of (Ti), gallium (Ga), yttrium (Y), scandium (Sc), and rare earth elements. .. Specific materials of the second insulating film 104 include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , and Si. ₃ N ₄ , SiON and the like can be mentioned.
The film thickness of the second insulating film is preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less. If it is 3 nm or less, tunnel current is likely to occur, and gate withstand voltage failure is likely to occur. At 100 nm or more, FET characteristics such as current drive capability (Gm) tend to be insufficient.

The gate electrode 105 is provided on the second insulating film 104, and is provided with aluminum (Al), titanium (Ti), tungsten (W), platinum (Pt), gold (Au), silver (Ag), and ruthenium (Ru). , Rhodium (Rh), Palladium (Pd), Nickel (Ni), Tin (Sn), Zinc (Zn), poly-Si (Polysilicon). In addition to these metals, alloys containing at least one selected from these groups, and compounds such as nitrides, carbides, and carbides containing at least one selected from these groups may be used. Then, the optimum material is selected from these in consideration of the work function as the gate electrode of the MISFET, the resistivity, the heat resistance in the manufacturing process, the contamination and the processability.

Next, the manufacturing process of the gallium nitride based semiconductor device 101 according to the first embodiment will be described with reference to FIG. 2, which shows the manufacturing flow in a schematic cross-sectional view.
As used herein, n or p means that electrons or holes are multiple carriers, respectively. Also, for + or-described on the right shoulder of n or p, + means that the carrier concentration is higher than that not described, and-means that the carrier concentration is lower than that not described. do.

Hereinafter, in order to make the explanation easy to understand, a case where an n ⁺ type GaN single crystal substrate is used as the self-supporting substrate 111 will be described. When a p-type substrate is used, n may be replaced with p and p may be replaced with n below. Further, in the present specification, "upper" and "upper" mean the first direction which is the direction from the self-standing substrate 111 to the semiconductor layer 101.

First, the semiconductor layer 101 is formed on the self-standing substrate 111 (FIG. 2A). For example, an n ⁺ type GaN single crystal substrate is used as the self-supporting substrate 111, and the p-type GaN layer is epitaxially formed in the first direction to a thickness of about 2 μm as the semiconductor layer 101 by directly contacting the n + type GaN single crystal substrate. As an example of the p-type impurity with respect to GaN, Mg (magnesium) can be mentioned.

Next, the screen layer 151 is formed on the entire surface of the main surface in direct contact with the main surface of the semiconductor layer 101 (FIG. 2 (b)). As the screen layer 151, for example, SiO ₂ having a thickness of about 20 nm in the first direction can be mentioned. The screen layer 151 has a function of preventing channeling that occurs in the semiconductor layer 101 during ion implantation.

After that, impurities are injected into the semiconductor layer 101 via the screen layer 151 to form the source region 107 and the drain region 108 (FIG. 2 (c)). This injection can be performed using the photoresist layer 161 as a mask, but ions can also be drawn and injected without a mask. Examples of the impurities (n-type) to be injected include Si, but the impurities are not limited to Si, and O (oxygen) or the like may be used. When injecting Si, for example, 5 × 10 ¹⁵ cm ^-2 is injected at 45 keV. The photoresist layer 161 is thick enough to shield Si, and Si is not injected into the channel forming region. A hard mask such as SiO ₂ may be used instead of the photoresist layer 161.

After that, the photoresist layer 161 is removed (FIG. 2 (d)), and the insulating layer 152 is subsequently formed on the screen layer 151 (FIG. 2 (e)). As a result, the cap layer 153 composed of the screen layer 151 and the insulating layer 152 is formed on the entire main surface.

If the screen layer 151 is once removed immediately after the impurity injection step of forming the source region 107 and the drain region 108, the surfaces of the source region 107 and the drain region 108 in an amorphous state are exposed. This state is active and quickly combines with oxygen to form gallium oxide. Therefore, as in this example, the insulating layer 152 is stacked without removing the screen layer 151.

On the other hand, after removing the screen layer 151, the insulating layer 152 may be provided in contact with the main surface. In this case, only the insulating layer 152 becomes the cap layer 153. Thereby, impurities mixed in the screen layer 151 at the time of ion implantation can be removed together with the screen layer 151.

As the insulating layer 152, for example, SiO ₂ having a thickness of about 480 nm in the first direction can be mentioned. By further stacking the insulating layer 152 on the screen layer 151, the thickness of the cap layer 153 becomes about 500 nm in this case. As the cap layer 153, Al ₂ O ₃ , SiN and Al N can also be used.
When the impurity in the semiconductor layer 101 is Mg, Al ₂ O ₃ , SiN and Al N are less likely to absorb Mg in the semiconductor layer 101 than in SiO ₂ . In this case, it is desirable to use SiO ₂ as the cap layer 153 for the purpose of allowing the cap layer 153 to absorb Mg in the vicinity of the main surface of the semiconductor layer 101.

After that, annealing is performed. The annealing temperature can be, for example, 1050 ° C or higher and 1200 ° C or lower. Examples of the atmospheric gas include Ar (argon) and / or N ₂ (nitrogen), but the gas is not limited to this gas.

The cap layer 20 can absorb impurities (for example, Mg) in the semiconductor layer 101 at this annealing step. When the p-type GaN layer containing Mg as an impurity is used as the semiconductor layer 101, the concentration of the p-type impurity in the semiconductor layer 101 is substantially lowered, so that the n-type source region 16 and drain region 18 have low resistance. can do. When SiO ₂ is used for the cap layer 153, the cap layer 153 does not absorb Si because it contains Si.

After that, the cap layer 153 is removed (FIG. 2 (f)). The source region 107 and the drain region 108 are recrystallized by the annealing. If the cap layer 153 is removed before annealing, the source region 107 and the drain region 108 may be peeled off together with the cap layer 153. Removing the cap layer 153 after annealing can prevent the source region 107 and the drain region 108 from peeling off.

Next, the first insulating film 103 and the second insulating film 104 are sequentially formed on the main surface, and the insulating layer 102 composed of the insulating film 103 and the second insulating film 104 is formed (FIG. 2 (g)). ).
Here, the first insulating film 103 is an insulating film having a gallium oxide crystal in which the above-mentioned gallium nitride and the in-plane lattice constant a are matched. Alternatively, the first insulating film 103 is an insulating film having a gallium oxide crystal having at least one of hexagonal crystals and cubic crystals having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less.

Alternatively, the first insulating film 103 is an insulating film containing gallium oxide crystals, and is, for example, an insulating film having the above-mentioned ε-structured gallium oxide and / or γ-structured gallium oxide.
Generally, the β structure of a gamma oxide crystal is a stable structure, and the ε structure and the γ structure are semi-stable structures. However, by using the first insulating film 103 as a gamma oxide crystal having an ε structure or a γ structure. , It is possible to form an insulating film 103 in a good interface state with few trap sites, which is suitable as a gate insulating film.

In the first method of forming the first insulating film 103, the surface of the semiconductor layer 101 containing gallium nitride is composed of sulfuric acid, hydrogen peroxide solution, ammonia, phosphoric acid, hydrochloric acid, nitric acid, phosphoric acid, and potassium hydroxide. A method of oxidizing with at least one chemical solution selected from the group.
Examples of this oxidation method include SC1 (Standard Cleaning solution 1) (NH ₄ OH (hydrogen water) -H ₂ O ₂ (hydrogen hydrogen) -H ₂ O (water)), SC2 (Standard Cleaning solution 2) (HCl (HCl). Hydrochloride) -H ₂ O ₂ -H ₂ O), SPM (Sulfuric acid hydrogen Peroxide Mixture) (H ₂ SO ₄ (sulfuric acid) -H ₂ O ₂ -H ₂ O), Buffered Hydrogen Fluoride: BHF) and the like, which are usually used for cleaning, can be mentioned. A buffered hydrofluoric acid solution is usually known as a method for removing an oxide film, but an oxide film having gallium oxide crystals in which gallium nitride and the in-plane lattice constant a are matched with the gallium nitride produced by the removal, or an oxide film having an ε structure can be used. An oxide film having gallium oxide and / or gallium oxide having a γ structure is a suitable film as the first insulating film 103.

According to this first method, the crystal planes (crystal planes of gallium oxide) of the first insulating film 103 are arranged so as to be aligned with the crystal planes on the surface of the semiconductor layer 101. Therefore, the first method is particularly preferable for forming a high-quality insulating film 102 with few traps.

In addition, light irradiation may be used together with this first method (Photo-Erctrochemical Oxidation). For example, the semiconductor layer 101 is immersed in a chemical solution such as potassium hydroxide, phosphoric acid, glycol, etc., and the surface of the semiconductor layer 101 is exposed to ultraviolet (UV) light having a wavelength of 280 nm or more and less than 380 nm or far-sighted external light having a wavelength of 190 nm or more and less than 280 nm. By irradiating with DUV), the surface of the semiconductor layer 101 may be oxidized to form the first insulating film 103.
Further, the first method is characterized in that the heat load is smaller than that of the thermal oxidation treatment because the treatment is at room temperature or at 280 ° C. or lower even if heat treatment is applied. When a large heat load is applied, problems such as a change in the profile of the injected impurities and stress are likely to occur.

In the second method of forming the first insulating film 103, the surface of the semiconductor layer 101 is oxidized by plasma oxidation treatment in an atmosphere of 500 ° C. or lower, and gallium nitride and the in-plane lattice constant a are matched. An oxide film having gallium crystals, a hexagonal crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an oxide film having at least one cubic gallium oxide crystal, or gallium oxide having an ε structure and / Or a method for forming gallium oxide having a γ structure. Further, an oxide film having a gallium oxide crystal in which gallium nitride and the in-plane lattice constant a are matched by oxidizing the surface of the semiconductor layer 101 by ozone oxidation treatment in an atmosphere of 500 ° C. or lower, an a-axis lattice. Even if a hexagonal crystal having a constant of 0.28 nm or more and 0.34 nm or less, an oxide film having at least one gallium oxide crystal of cubic crystal, or gallium oxide having a ε structure and / or gallium oxide having a γ structure is formed. good.

A third method for forming the first insulating film 103 is gallium nitride on the surface of the semiconductor layer 101 by an electron beam epitaxy method and / or a molecular beam epitaxy (MBE) method in an atmosphere of 700 ° C. or lower. An oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched, a hexagonal crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less, or a gallium oxide crystal having at least one of cubic crystals. It is a method of depositing an oxide film having an oxide film, or gallium oxide having an ε structure and / or gallium oxide having a γ structure. Further, an oxide film having gallium nitride crystals whose in-plane lattice constant a is matched with gallium nitride by a chemical vapor deposition (CVD) method in an atmosphere of 870 ° C. or lower on the surface of the semiconductor layer 101. , A hexagonal crystal with an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an oxide film having at least one cubic gallium oxide crystal, or ε-structured gallium oxide and / or γ-structured gallium oxide. May be deposited. Further, on the surface of the semiconductor layer 101, an oxide film having gallium oxide crystals in which gallium nitride and the in-plane lattice constant a are matched by a hydride vapor phase growth (HVPE) method in an atmosphere of 700 ° C. or lower. , A hexagonal crystal with an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an oxide film having at least one cubic gallium oxide crystal, or gallium oxide having an ε structure and / or gallium oxide having a γ structure. May be deposited. Further, an oxide film having a gallium oxide crystal in which gallium nitride and an in-plane lattice constant a are matched on the surface of the semiconductor layer 101 by an atomic layer deposition (ALD) method in an atmosphere of 500 ° C. or lower, a. An oxide film having a hexagonal crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less, a gallium oxide crystal having at least one of cubic crystals, or a gallium oxide having an ε structure and / or a gallium oxide having a γ structure is deposited. You may let it. Further, gallium oxide is deposited on the surface of the semiconductor layer 101 by a sputtering method in an atmosphere of 500 ° C. or lower, and then annealed to obtain an oxide film having gallium oxide crystals in which gallium nitride and the in-plane lattice constant a are matched. , A hexagonal crystal with an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an oxide film having at least one cubic gallium oxide crystal, or ε-structured gallium oxide and / or γ-structured gallium oxide. May be deposited.

When the first insulating film is formed under oxygen-rich conditions, gallium oxide having an ε structure and / or gallium oxide having a γ structure is formed.

In the fourth method of forming the first insulating film 103, gallium oxide is formed on the surface of the semiconductor layer 101 by heat treatment at 500 ° C. or higher, and then etching is performed to reduce the thickness of the gallium oxide to 10 nm or less. This is a method for forming the first insulating film.

The second insulating film 104 is an oxide, a nitride, or an acid of at least one element selected from the group of elements consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and rare earth elements. The nitride is formed by a sputtering method, a CVD method, an ALD method, or the like. Specific materials for the second insulating film 104 include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , and Si. Examples thereof include _3N4 and SiON. For example, when Al ₂ O ₃ is formed as a _second insulating film by a sputtering method, Al can be used as a target and DC sputtering can be performed in oxygen gas. RF sputtering can also be performed using Al ₂ O ₃ as a target. It can also be formed by the ALD method using trimethylaluminum.

After that, the gate electrode 105 is formed on the insulator layer 102 (FIG. 2 (h)).
In the gate electrode 105, after depositing the gate material constituting the gate electrode on the entire surface of the insulator layer 102, a photoresist layer having a desired pattern is formed by lithography, and the photoresist layer is used as an etching mask to etch the gate material. And form. The gate electrode material is formed from at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly—Si. In addition to these metals, alloys containing at least one selected from these groups, and compounds such as nitrides, carbides, and carbides containing at least one selected from these groups may be used. Examples of the method for depositing the gate electrode material include a sputtering method, a vapor deposition method using an electron beam, a vapor deposition method by heating, and a CVD method. This method is characterized by high gate electrode processing accuracy.
Further, after forming a photoresist layer for lift-off, a gate material is deposited by a vapor deposition method using an electron beam, a vapor deposition method by heating, a sputtering method, a CVD method, or the like, and the photoresist layer is peeled off to form a gate electrode 105. May be formed. This method is characterized in that the semiconductor device is not damaged by etching.
Further, an interlayer film having an opening at a place where the gate electrode is formed is formed on the insulator layer 102, and after depositing the gate electrode material, gate insulation is performed by a CMP (Chemical Mechanical Polishing) method, an etch back method, or the like. The material may be embedded in the opening of the interlayer film to form the gate electrode 105. This method is characterized in that even when an electrode material that is difficult to etch is used, processing with sufficiently high accuracy is possible, and damage to the semiconductor device due to etching is less likely to occur.

After that, the source electrode 109 and the drain electrode 110 are formed (FIG. 2 (i)). At this time, an opening is opened in advance in the insulator layer 102 of the source electrode 109 and the drain electrode 110 by etching so that the source electrode 109 and the source region 107 and the drain electrode 110 and the drain region 108 are in electrical contact with each other. Keep it. Ohmic contact is preferred for this electrical contact. The source electrode 109 and the drain electrode 110 may be a laminate of Ti (titanium) and Al (aluminum), but are not limited thereto. The source electrode 109 and the drain electrode 110 are from at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si. It may be formed. In addition to these metals, alloys containing at least one selected from these groups, and compounds such as nitrides, carbides, and carbides containing at least one selected from these groups may be used.
The MISFET 100 is manufactured by the above steps.

The MISFET 100 according to the manufacturing method of the first embodiment is characterized in that it is easy to obtain predetermined electrical characteristics because it is possible to perform a desired heat treatment for impurities in the semiconductor layer 101 and its profile before forming the gate electrode 105.

<Embodiment 2>
The semiconductor device of the second embodiment is a gallium nitride based semiconductor device 100 which is a horizontal MISFET as in the first embodiment, but its manufacturing method is different from that of the first embodiment. The manufacturing method will be described with reference to FIG. 3, which is a schematic cross-sectional view.

First, the semiconductor layer 101 is formed on the self-standing substrate 111 (FIG. 3A).
Next, the first insulating film 103 and the second insulating film 104 are sequentially formed on the main surface of the semiconductor layer 101, and the insulating layer 102 composed of the insulating film 103 and the second insulating film 104 is formed (FIG. 3 (b)).
Here, the first insulating film 103 is an insulating film containing a gallium oxide crystal, for example, an oxide film having a gallium oxide crystal in which gallium nitride and an in-plane lattice constant a are matched, and an a-axis lattice constant. An oxide film having at least one gallium oxide crystal having a hexagonal crystal or a cubic structure of 0.28 nm or more and 0.34 nm or less, or an insulating film having the above-mentioned ε-structured gallium oxide and / or γ-structured gallium oxide. Is.
The first insulating film 103 is an oxide film having gallium nitride and gallium oxide crystals in which the in-plane lattice constant a is matched, a hexagonal crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, or at least a cubic crystal. By using an oxide film having any one gallium oxide crystal or gallium oxide having an ε structure or a γ structure, it is possible to form an insulating film 103 in a good interface state with few trap sites suitable as a gate insulating film. can.

In the first method of forming the first insulating film 103, the surface of the semiconductor layer 101 containing gallium nitride is composed of sulfuric acid, hydrogen peroxide solution, ammonia, phosphoric acid, hydrochloric acid, nitric acid, phosphoric acid, and potassium hydroxide. A method of oxidizing with at least one chemical solution selected from the group.
Examples of this oxidation method include methods usually used for washing such as SC1, SC2, SPM, and buffered hydrofluoric acid solution.
According to this first method, the crystal planes of the first insulating film 103 are aligned with the crystal planes on the surface of the semiconductor layer 101. Therefore, the first method is particularly preferable for forming a high-quality insulating film 102 with few traps.

In addition, light irradiation may be used together with this first method. For example, the semiconductor layer 101 is immersed in a chemical solution such as potassium hydroxide, phosphoric acid, glycol, etc., and the surface of the semiconductor layer 101 is exposed to ultraviolet (UV) light having a wavelength of 280 nm or more and less than 380 nm or far-sighted external light having a wavelength of 190 nm or more and less than 280 nm. By irradiating with DUV), the surface of the semiconductor layer 101 may be oxidized to form the first insulating film 103.
Further, the first method is characterized in that the heat load is smaller than that of the thermal oxidation treatment because the treatment is at room temperature or at 280 ° C. or lower even if heat treatment is applied. When a large heat load is applied, problems such as a change in the profile of the injected impurities and stress are likely to occur.

In the second method of forming the first insulating film 103, the surface of the semiconductor layer 101 is oxidized by plasma oxidation treatment in an atmosphere of 500 ° C. or lower, and gallium nitride and the in-plane lattice constant a are matched. An oxide film having gallium crystals, a hexagonal crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an oxide film having at least one cubic gallium oxide crystal, or gallium oxide having an ε structure and / Or a method for forming gallium oxide having a γ structure. Further, an oxide film having a gallium oxide crystal in which gallium nitride and the in-plane lattice constant a are matched by oxidizing the surface of the semiconductor layer 101 by ozone oxidation treatment in an atmosphere of 500 ° C. or lower, an a-axis lattice. Even if a hexagonal crystal having a constant of 0.28 nm or more and 0.34 nm or less, an oxide film having at least one gallium oxide crystal of cubic crystal, or gallium oxide having a ε structure and / or gallium oxide having a γ structure is formed. good.

In the third method of forming the first insulating film 103, gallium nitride and the in-plane lattice constant a are matched on the surface of the semiconductor layer 101 by an electron beam vapor deposition method and / or an MBE method in an atmosphere of 700 ° C. or lower. An oxide film having gallium oxide crystals, a hexagonal crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an oxide film having at least one cubic gallium oxide crystal, or oxidation of an ε structure. It is a method of depositing gallium and / or gallium oxide having a γ structure. Further, an oxide film having gallium oxide crystals in which gallium nitride and the in-plane lattice constant a are matched by the CVD method in an atmosphere of 870 ° C. or lower on the surface of the semiconductor layer 101, and the lattice constant of the a-axis is 0.28 nm or more. An oxide film having at least one gallium oxide crystal having a hexagonal crystal or a cubic crystal having a diameter of 0.34 nm or less, or gallium oxide having an ε structure and / or gallium oxide having a γ structure may be deposited. Further, an oxide film having a gallium oxide crystal in which gallium nitride and an in-plane lattice constant a are matched by the HVPE method on the surface of the semiconductor layer 101 in an atmosphere of 700 ° C. or lower, and an a-axis lattice constant of 0.28 nm or more. An oxide film having at least one gallium oxide crystal of hexagonal crystal or cubic crystal having a diameter of 0.34 nm or less, or gallium oxide having an ε structure and / or gallium oxide having a γ structure may be deposited. Further, an oxide film having a gallium oxide crystal in which gallium nitride and an in-plane lattice constant a are matched by the ALD method on the surface of the semiconductor layer 101 in an atmosphere of 500 ° C. or lower, and an a-axis lattice constant of 0.28 nm or more. An oxide film having at least one gallium oxide crystal having a hexagonal crystal or a cubic crystal having a diameter of 0.34 nm or less, or gallium oxide having an ε structure and / or gallium oxide having a γ structure may be deposited. Further, gallium oxide is deposited on the surface of the semiconductor layer 101 by a sputtering method in an atmosphere of 500 ° C. or lower, and then annealed to obtain an oxide film having gallium oxide crystals in which gallium nitride and the in-plane lattice constant a are matched. , A hexagonal crystal with an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an oxide film having at least one cubic gallium oxide crystal, or ε-structured gallium oxide and / or γ-structured gallium oxide. May be deposited.

In the fourth method of forming the first insulating film 103, gallium oxide is formed on the surface of the semiconductor layer 101 by heat treatment at 500 ° C. or higher and 870 ° C. or lower, and then etching is performed to determine the thickness of the gallium oxide. This is a method of forming the first insulating film with a thickness of 10 nm or less.

The second insulating film 104 is an oxide, a nitride, or an acid of at least one element selected from the group of elements consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and rare earth elements. The nitride is formed by a sputtering method, a CVD method, an ALD method, or the like. Specific materials for the second insulating film 104 include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , and Si. Examples thereof include _3N4 and SiON. For example, when Al ₂ O ₃ is formed as a _second insulating film by a sputtering method, Al can be used as a target and DC sputtering can be performed in oxygen gas. RF sputtering can also be performed using Al ₂ O ₃ as a target. It can also be formed by the ALD method using trimethylaluminum.

After that, the gate electrode 105 is formed on the insulator layer 102 (FIG. 3 (c)).
In the gate electrode 105, after depositing the gate material constituting the gate electrode on the entire surface of the insulator layer 102, a photoresist layer having a desired pattern is formed by lithography, and the photoresist layer is used as an etching mask to etch the gate material. And form. The gate electrode material is formed from at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly—Si. In addition to these metals, alloys containing at least one selected from these groups, and compounds such as nitrides, carbides, and carbides containing at least one selected from these groups may be used. Examples of the method for depositing the gate electrode material include a sputtering method, a vapor deposition method using an electron beam, a vapor deposition method by heating, and a CVD method. This method is characterized by high gate electrode processing accuracy.
Further, after forming a photoresist layer for lift-off, a gate material is deposited by a vapor deposition method using an electron beam, a vapor deposition method by heating, a sputtering method, a CVD method, or the like, and the photoresist layer is peeled off to form a gate electrode 105. May be formed. This method is characterized in that the semiconductor device is not damaged by etching.
Further, an interlayer film having an opening at a place where the gate electrode is formed is formed on the insulator layer 102, the gate electrode material is deposited, and then the gate insulating material is applied to the interlayer film by a CMP method or an etchback method. The gate electrode 105 may be formed by embedding it in the opening. This method is characterized in that even when an electrode material that is difficult to etch is used, processing with sufficiently high accuracy is possible, and damage to the semiconductor device due to etching is less likely to occur.

After that, impurities are injected into the semiconductor layer 101 using the gate electrode as a mask to form the source region 107 and the drain region 108 (FIG. 3 (d)). The impurities to be injected are the same as those in the first embodiment.

After that, the source electrode 109 and the drain electrode 110 are formed (FIG. 3 (e)). At this time, an opening is opened in advance in the insulator layer 102 of the source electrode 109 and the drain electrode 110 by etching so that the source electrode 109 and the source region 107 and the drain electrode 110 and the drain region 108 are in electrical contact with each other. Keep it. Ohmic contact is preferred for this electrical contact. The source electrode 109 and the drain electrode 110 may be a laminate of Ti (titanium) and Al (aluminum), but are not limited thereto. The source electrode 109 and the drain electrode 110 are from at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si. It may be formed. In addition to these metals, alloys containing at least one selected from these groups, and compounds such as nitrides, carbides, and carbides containing at least one selected from these groups may be used.
The MISFET 100 is manufactured by the above steps.

In the MISFET 100 according to the manufacturing method of the second embodiment, the source region 107, the drain region 108, and the channel region are self-aligned with the gate electrode 105 as a mask. It has the characteristic that it is easy to obtain accuracy. Therefore, the manufacturing method of the second embodiment is a suitable method for performing high integration.

<Embodiment 3>
In the third embodiment, the vertical MISFET 300 will be described with reference to FIGS. 4 to 6.

In the present specification, the surface of the n-type semiconductor substrate 350 on the side where the gate electrode 340 is provided is referred to as the front surface for convenience, and the surface of the n-type semiconductor substrate 350 on the side where the drain electrode 346 is provided is referred to as the back surface for convenience. .. Further, the direction from the back surface to the front surface is referred to as a front surface direction, and the direction from the front surface to the back surface is referred to as a back surface direction. The surface of the layer or film on the front side is referred to as the front surface side, and the surface on the back surface direction side is referred to as the back surface side.
Further, in the present specification, n or p means that electrons or holes are a large number of carriers, respectively. Also, for + or-described on the right shoulder of n or p, + means that the carrier concentration is higher than that not described, and-means that the carrier concentration is lower than that not described. do.
In the present specification, the first conductive type is referred to as p-type or p ⁺ type, and the second conductive type is referred to as n-type or n ⁺ type. However, in another example, the first conductive type may be n type or n ⁺ type, and the second conductive type may be p type or p ⁺ type.

The vertical MISFET 300 is provided on the n-type semiconductor substrate 350 (see FIG. 6C). A source electrode 344 is provided on a part of the surface of the n-type semiconductor substrate 350. Further, an insulator layer 342 serving as a gate insulating film is provided on the other part of the surface of the n-type semiconductor substrate 350. A gate electrode 340 is provided on the surface side of the gate insulating film (insulator layer) 342. The source electrode 344 may be provided so as to sandwich or surround the gate insulating film 342 and the gate electrode 340.

The gate insulating film 342 is a laminated film of the first insulating film 351 and the second insulating film 352, and the first insulating film 351 is provided on the n-type semiconductor substrate 350 side.

The first insulating film 351 is an insulating film containing a gallium oxide crystal, and in particular, an oxide film having a gallium oxide crystal in which gallium nitride and an in-plane lattice constant a are matched, and the a-axis lattice constant is 0. A hexagonal crystal of 28 nm or more and 0.34 nm or less, an oxide film having at least one gallium oxide crystal of a cubic crystal, or a gallium oxide composed of ε-structured gallium oxide or γ-structured gallium oxide or ε-structured gallium oxide and A film composed of a combination of gallium oxide having a γ structure is preferable.

Further, the crystal planes of the first insulating film 351 are arranged so as to be aligned with the crystal planes of the n-type semiconductor substrate 350. For example, the first insulating film 351 may be formed so that the crystal planes of gallium oxide, which is a hexagonal single crystal, are aligned on the crystal planes of the Miller index [0001] of gallium nitride of the n-type semiconductor substrate 350.

The film thickness of the first insulating film 351 is preferably 10 nm or less. If it is larger than 10 nm, lattice mismatch is likely to occur in the formed gallium oxide, and trap sites increase. Further, the film thickness of the first insulating film 351 is more preferably 5 nm or less. As described above, it is preferable to reduce the film thickness of the first insulating film 351 as much as possible. On the other hand, the film thickness of the first insulating film 351 needs to be at least one atomic layer of gallium oxide in order to ensure that gallium oxide crystals are formed on the n-type semiconductor substrate 350. be. Further, if the film thickness of the first insulating film 351 is set to a thickness of two or more atomic layers of gallium oxide, there is an effect that the generation of defective portions is not small.

When the first insulating film 351 has a gallium nitride crystal in which gallium nitride and the in-plane lattice constant a are matched, a gallium oxide crystal in which the gallium nitride and the in-plane lattice constant a in the first insulating film 351 are matched. The proportion of the volume occupied by the gallium is preferably 95% or more. When the first insulating film 351 has a gallium oxide crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less, which is at least one of hexagonal crystals and cubic crystals, the first insulating film 351 The volume ratio of the gallium oxide crystal having at least one of hexagonal crystals and cubic crystals having a lattice constant of 0.28 nm or more and 0.34 nm or less in the a-axis is preferably 95% or more. With this configuration, the generation of trap sites in the gate insulating film 342 formed between the n-type semiconductor substrate 350, which is a gallium nitride based semiconductor layer, and the gate electrode 105 is sufficiently suppressed.

When the first insulating film 351 is composed of a combination of ε-structured gallium oxide and γ-structured gallium oxide, the ratio of ε-structured gallium oxide to the volume of the first insulating film 351 is 70. % Or more and 90% or less, the ratio of gamma oxide having a γ structure is 10% or more and 30% or less, and the total ratio of gallium oxide having an ε structure and gamma oxide having a γ structure is 95% or more and 100%. It is preferable that it is as follows. For example, in the volume of the first insulating film 103, the ratio of gallium oxide having an ε structure is 80%, and the remaining 20% of the first insulating film 351 is occupied by gamma oxide having a γ structure. May be good. Further, in the volume of the first insulating film 351, the proportion of gallium oxide having an ε structure is 78%, the proportion of gallium oxide having a γ structure is 18%, and the proportion of gallium oxide having an ε structure and the gamma structure is γ. The ratio of the total of ε-structured gallium oxide and γ-structured gallium oxide may be 96% so that the ratio of non-gamma oxide is 4%. With this configuration, the generation of trap sites in the gate insulating film 342 formed between the n-type semiconductor substrate 350, which is a gallium nitride based semiconductor layer, and the gate electrode 105 is sufficiently suppressed.

The second insulating film 352 of the gate insulating film 342 is provided on the first insulating film 351 and is composed of a group of elements consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and rare earth elements. It is formed from oxides, nitrides, or oxynitrides of at least one selected element. Specific materials of the second insulating film 104 include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , and Si. ₃ N ₄ , SiON and the like can be mentioned.
The film thickness of the second insulating film is preferably 3 nm or more and 100 nm or less, and more preferably 5 nm or more and 50 nm or less. If it is 3 nm or less, tunnel current is likely to occur, and gate withstand voltage failure is likely to occur. At 100 nm or more, FET characteristics such as current drive capability (Gm) tend to be insufficient.

A drain electrode 346 is provided on the back surface of the n-type semiconductor substrate 350. An n ⁺ type semiconductor layer 332 is provided on the back surface side of the n-type semiconductor substrate 350 in a region in contact with the drain electrode 346. The n ⁺ type semiconductor layer 332 may have a predetermined thickness. The n ⁺ type semiconductor layer 332 has an impurity concentration higher than the impurity concentration in the n-type semiconductor substrate 350 in order to reduce the contact resistance with the drain electrode 346.

The vertical MISFET 300 has an n-type drift layer 330 as a second conductive type drift layer and a current cutoff layer 320 provided on the surface side of the n-type drift layer 330. The n-type semiconductor substrate 350 further includes a p-type semiconductor layer 310 as a first conductive type semiconductor layer provided on the surface side of the current cutoff layer 320. The p-type semiconductor layer 310 is GaN.

The current cutoff layer 320 of this example is p-type and has a higher concentration of impurities than the p-type semiconductor layer 310. The p-type semiconductor layer 310 of this example is an epitaxial layer provided in contact with the current cutoff layer 320. When the current cutoff layer 320 is a p ⁺ type semiconductor layer as in this example, the current cutoff layer 320 and the p-type semiconductor layer 310 are electrically connected to each other.

The current cutoff layer 320 is located between the end portion on the back surface side of the n-type source side region 312 and the end portion on the back surface side of the n-type source side region 312 from the source electrode 344 to the n-type drift layer 330. The current flowing through the drain electrode 346 is cut off. In another example, the current cutoff layer 320 may be an insulating layer. However, when the current cutoff layer 320 is not an insulating layer but a semiconductor region and a large current flows from the drain electrode to the source electrode, the current cutoff layer 320 may pass a current.

The p-type semiconductor layer 310 has an n-type source-side region 312 and an n-type drain-side region 314 as a source-side region and a drain-side region of the second conductive type. The n-type source side region 312 and the n-type drain side region 314 are provided apart from each other on the surface of the p-type semiconductor layer 310.

The n-type source side region 312 and the n-type drain side region 314 are formed to the same depth in the p-type semiconductor layer 310. In forming the n-type source side region 312 and the n-type drain side region 314, the impurity doping process is performed only once. In the one-time impurity doping process, the channel length 343 is defined by the distance between the n-type source side region 312 and the n-type drain side region 314. The channel length 343 is a part of the p-type semiconductor layer 310 on the back surface side of the gate insulating film.

On the back surface side of the current cutoff layer 320 on the back surface side of the p-type semiconductor layer 310, the n-type drift layer 330 is in contact with the end portion of the n-type drain side region 314 on the back surface side. On the other hand, due to the presence of the current cutoff layer 320, the n-type drift layer 330 is not in contact with the end portion on the back surface side of the n-type source side region 312.

The depletion layer between the current cutoff layer 320 and the n-type drift layer 330 and the depletion between the current cutoff layer 320 and the n-type drain side region 314 under the off condition where the drain electrode 346 and the gate electrode 340 are set to the Low potential. The layer expands. The depletion layer reaches the entire space between the n-type drift layer 330 and the end portion on the back surface side of the n-type drain side region 314. As a result, the current from the drain electrode 346 to the source electrode 344 under the off condition is surely cut off.

The vertical MISFET 300 further includes an n ⁺ type contact layer 318 as a second conductive type contact layer. The n ⁺ type contact layer 318 is provided to reduce the contact resistance between the n-type semiconductor substrate 350 and the source electrode 344. For the same purpose, a p ⁺ type contact layer 316 is provided on the back surface side of the source electrode 344.

At least a part of the n ⁺ type contact layer 318 is formed in the n type source side region 312. The n ⁺ type contact layer 318 has a higher concentration of impurities than any of the n-type drain side region 314 and the n-type source side region 312.

In this example, the distance L2 from the n-type drain side region 314 to the n ⁺ type contact layer 318 is larger than the distance L1 from the n-type drain side region 314 to the n-type source side region 312. That is, L1 <L2.

The distance L2 may be the shortest distance from the n-type drain side region 314 to the n ⁺ type contact layer 318 on the surface of the n-type semiconductor substrate 350. Alternatively, the distance L2 may be the shortest distance from the n-type drain side region 314 to the n ⁺ -type contact layer 318 at the depth position of the back surface side end portion of the n ⁺ type contact layer 318.

Further, the distance L1 may be the shortest distance from the n-type drain side region 314 to the n-type source side region 312 on the surface of the n-type semiconductor substrate 350. Alternatively, the distance L1 may be the shortest distance from the n-type drain side region 314 to the n-type source side region 312 at the depth position of the back surface side end portion of the n ⁺ type contact layer 318.

In the vertical MISFET 300 of this example, the n ⁺ type contact layer 318 has nothing to do with defining the channel length. The channel length is defined only by the distance between the n-type source side region 312 and the n-type drain side region 314. Therefore, in the vertical MISFET 300 of this example, the channel length can be precisely controlled. That is, the vertical MISFET 300 of this example is excellent in controllability of the channel length.

In another example, the distance L2 from the n-type drain side region 314 to the n ⁺ type contact layer 318 may be equal to or greater than the distance L1 from the n-type drain side region 314 to the n-type source side region 312. As is obvious from the above description, in the other example, L1 = L2 may be set. Again, the n ⁺ type contact layer 318 has nothing to do with defining the channel length. It should be noted that the accuracy at the time of manufacturing the n ⁺ type contact layer 318 is required to be higher in the case of L1 = L2 than in the case of L1 <L2. Therefore, the case of L1 <L2 is easier to manufacture.

Further, in still another example, the n ⁺ type contact layer 318 may be formed so as to extend from the n-type source side region 312 in the direction opposite to the n-type drain side region 314. That is, the source electrode 344 may be mainly in contact with the n ⁺ type contact layer 318 instead of the p ⁺ type contact layer 316. A contact layer having a higher concentration of impurities than the n-type drain side region 314 is not formed on the surface of the n-type drain side region 314.

Next, a method of manufacturing the vertical MISFET 300 will be described.
As described above, the n-type semiconductor substrate 350 is GaN. The p-type impurity may be magnesium (Mg), calcium (Ca) or beryllium (Be), and the n-type impurity may be silicon (Si) or oxygen (O). In FIGS. 4 to 6, an example in which the n-type semiconductor substrate 350 is GaN will be described.

FIG. 4A is a diagram showing a stage of forming the current cutoff layer 320. First, a patterned photoresist layer 360 is formed on the surface of the GaN n-type semiconductor substrate 350. The photoresist layer 360 may have a linear shape extending in a direction perpendicular to the paper surface, or may have a rectangular island shape.

Next, the photoresist layer 360 is used as a mask to dope the p-type impurities from the surface side of the n-type semiconductor substrate 350. Regions other than the region provided with the photoresist layer 360 are doped with p-type impurities. The p-type impurities constitute a box profile having a constant impurity concentration at a depth in a predetermined range.

The p-type impurity may be Mg. The total dose amount may be 1 × 10 ¹⁴ or more and 5 × 10 ¹⁵ cm ^-2 or less. The p-type impurities may be doped to a depth of 0.5 μm from the front surface of the n-type semiconductor substrate 350 toward the back surface. The thickness and impurity concentration of the n-type semiconductor substrate 350 may be appropriately determined according to the withstand voltage.

After doping with p-type impurities, annealing is performed at 1000 ° C. or higher and 1500 ° C. or lower. As a result, the current cutoff layer 320 is formed. The current cutoff layer 320 is a p ⁺ type semiconductor layer having a higher p-type impurity concentration than the p-type semiconductor layer 310 described later.

FIG. 4B is a diagram showing a stage of forming the p-type semiconductor layer 310. After the step of forming the current cutoff layer 320, the photoresist layer 360 is removed by ashing, a stripping solution, or the like, and then the p-type semiconductor layer 310 is formed on the current cutoff layer 320. In this example, at the stage of forming the p-type semiconductor layer 310, the p-type semiconductor layer 10 is formed on the current cutoff layer 320 by epitaxial growth. The epitaxially grown p-type semiconductor layer 310 may have a thickness of 0.5 μm or more and 2.0 μm or less, and may contain 1 × 10 ¹⁷ cm ^-3 p-type impurities.

FIG. 4C is a diagram showing a stage of simultaneously forming the n-type source side region 312 and the n-type drain side region 314. After the step of forming the p-type semiconductor layer 310, the n-type source side region 312 and the n-type drain side region 314 are simultaneously formed. In this example, first, a patterned photoresist layer 362 is provided on the surface of the n-type semiconductor substrate 350. The photoresist layer 362 is provided so as to be separated from each other in a cross-sectional view. The photoresist layer 362 may have a striped shape, a square cell shape, or a hexagonal cell shape when viewed in a plan view.

Next, the photoresist layer 362 is used as a mask to dope the n-type impurities from the surface side of the n-type semiconductor substrate 350. Regions other than the region provided with the photoresist layer 362 are doped with n-type impurities. The n-type impurities may form a box profile. The n-type impurity may be Si or O. The total dose amount may be 5 × 10 ¹² or more and 1 × 10 ¹⁴ cm ^-2 or less.

After doping with n-type impurities, annealing is performed. As a result, the n-type source side region 312 and the n-type drain side region 314 are formed at the same time. The formed n-type source side region 312 and n-type drain side region 314 are separated from each other on the surface of the p-type semiconductor layer 310. This defines the channel length 343. The channel length 343 may be 0.5 μm or more and 2.0 μm or less.

The doped n-type impurities diffuse in the p-type semiconductor layer 310 at the time of annealing. After annealing, the back end of the n-type source side region 312 reaches the current cutoff layer 320. Further, the back surface side end portion of the n-type drain side region 314 reaches the n-type drift layer 330.

FIG. 5A is a diagram showing a stage of forming the p ⁺ type contact layer 316. After the step of simultaneously forming the n-type source side region 312 and the n-type drain side region 314, the p ⁺ type contact layer 316 is formed. First, a patterned photoresist layer 364 is provided on the surface of the n-type semiconductor substrate 350. The photoresist layer 364 of this example is formed so as to completely cover the n-type drain side region 314 and partially cover the n-type source side region 312 in cross-sectional view. The photoresist layer 364 may have a striped shape, a square cell shape, or a hexagonal cell shape when viewed in a plan view.

Next, the photoresist layer 364 is used as a mask to dope the p-type impurities from the surface side of the n-type semiconductor substrate 350. The p-type impurities doped at this stage have a higher impurity concentration than the p-type semiconductor layer 310. As a result, the region other than the region provided with the photoresist layer 364 becomes a p ⁺ type. After doping with p-type impurities, annealing is performed. This forms the p ⁺ type contact layer 316.

FIG. 5B is a diagram showing a stage of forming the n ⁺ type contact layer 318. After the step of forming the p ⁺ type contact layer 316, the n ⁺ type contact layer 318 is formed. First, a patterned photoresist layer 366 is provided on the surface of the n-type semiconductor substrate 350. The photoresist layer 366 has an opening in at least the n-type source side region 312. The photoresist layer 366 of this example may have a striped shape, a square cell shape, or a hexagonal cell shape when viewed in a plan view in a cross-sectional view.

However, of the openings of the photoresist layer 366, the opening end portion 367 on the n-type drain side region 314 side is closer to the n-type drain side than the surface side end portion 313 on the n-type drain side region 314 side of the n-type source side region 312. Not provided on the side of region 314. Of the openings of the photoresist layer 366, the opening end portion 367 on the n-type drain side region 314 side may coincide with the surface side end portion 313 on the n-type drain side region 314 side of the n-type source side region 312.

Next, the photoresist layer 366 is used as a mask to dope the n-type impurities from the surface side of the n-type semiconductor substrate 350. Regions other than the region provided with the photoresist layer 366 are doped with n-type impurities. The n-type impurities may form a box profile with a depth of 0.2 μm. The n-type impurity may be Si or O. The total dose amount may be 5 × 10 ¹⁵ cm ^{− 2} .

After doping with n-type impurities, annealing is performed. As a result, at least a part of the n ⁺ type contact layer 318 having a higher concentration of impurities than any of the n-type drain side region 314 and the n-type source side region 312 is formed in the n-type source side region 312. Further, the distance L2 from the n-type drain side region 314 to the n ⁺ type contact layer 318 is set to be equal to or greater than the distance L1 from the n-type drain side region 314 to the n-type source side region 312.

As a modification, the annealing at the stage of FIGS. 4A to 5B may be performed collectively when the annealing for forming the n ⁺ type contact layer 318 in FIG. 5B is performed. .. As a result, the manufacturing process time can be shortened.

Next, as shown in FIG. 5C, a first insulating film 351 and a second insulating film 352 are sequentially formed on the surface of the n-type semiconductor substrate 350, and the first insulating film 351 and the second insulating film 351 and the second insulating film 352 are sequentially formed. A gate insulating film 342 composed of a film 352 is formed.
Here, the first insulating film 351 is an insulating film containing gallium oxide crystals, and in particular, an oxide film having gallium oxide crystals in which the above-mentioned gallium nitride and the in-plane lattice constant a are matched, or an ε structure. It is preferable that the insulating film has gallium oxide and / or gallium oxide having a γ structure.
By using the first insulating film 351 as an oxide film having gallium oxide crystals in which gallium nitride and the in-plane lattice constant a are matched, or gallium oxide having an ε structure or a γ structure, a trap site suitable as a gate insulating film is used. It is possible to form a gate insulating film 342 in a good interface state with a small amount of water.

In the first method of forming the first insulating film 351, the surface of the n-type semiconductor substrate 350 is made of a group consisting of sulfuric acid, hydrogen peroxide solution, ammonia, phosphoric acid, hydrochloric acid, nitric acid, phosphoric acid, and potassium hydroxide. A method of oxidizing with at least one chemical solution of choice.
Examples of this oxidation method include methods usually used for washing such as SC1, SC2, SPM, and buffered hydrofluoric acid solution.
According to this first method, the crystal planes of the first insulating film 351 are arranged so as to be aligned with the crystal planes on the surface of the n-type semiconductor substrate 350. Therefore, the first method is particularly preferable for forming a high-quality gate insulating film 342 with few traps.

In addition, light irradiation may be used together with this first method. For example, the n-type semiconductor substrate 350 is immersed in a chemical solution of potassium hydroxide, phosphoric acid, glycol, etc., and the surface of the n-type semiconductor substrate 350 is exposed to ultraviolet (UV) light having a wavelength of 280 nm or more and less than 380 nm or an ultraviolet (UV) light having a wavelength of 190 nm or more and less than 280 nm. By irradiating with far-sighted external light (DUV), the surface of the n-type semiconductor substrate 350 may be oxidized to form the first insulating film 351.
Further, the first method is characterized in that the heat load is smaller than that of the thermal oxidation treatment because the treatment is at room temperature or at 280 ° C. or lower even if heat treatment is applied. When a large heat load is applied, problems such as a change in the profile of the injected impurities and stress are likely to occur.

In the second method of forming the first insulating film 351, the surface of the n-type semiconductor substrate 350 is oxidized by plasma oxidation treatment in an atmosphere of 500 ° C. or lower, and gallium nitride and the in-plane lattice constant a are matched. Oxidation with gallium oxide crystals, hexagonal crystal with a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, oxide film with at least one cubic gallium oxide crystal, or oxidation of ε structure A method for forming gallium and / or gallium oxide having a γ structure. Further, an oxide film having gallium oxide crystals in which gallium nitride and the in-plane lattice constant a are matched by oxidizing the surface of the n-type semiconductor substrate 350 by ozone oxidation treatment in an atmosphere of 500 ° C. or lower, a-axis. Form an oxide film having a hexagonal crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less, a gallium oxide crystal having at least one of cubic crystals, or a gallium oxide having an ε structure and / or a gallium oxide having a γ structure. May be.

In the third method of forming the first insulating film 351, gallium nitride and the in-plane lattice constant a are formed on the surface of the n-type semiconductor substrate 350 by an electron beam vapor deposition method and / or an MBE method in an atmosphere of 700 ° C. or lower. An oxide film having matched gallium oxide crystals, a hexagonal crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an oxide film having at least one cubic gallium oxide crystal, or an ε structure. It is a method of depositing gallium oxide and / or gallium oxide having a γ structure. Further, an oxide film having gallium oxide crystals in which gallium nitride and the in-plane lattice constant a are matched by the CVD method in an atmosphere of 870 ° C. or lower on the surface of the n-type semiconductor substrate 350, and the lattice constant of the a-axis is 0. A hexagonal crystal having a size of 28 nm or more and 0.34 nm or less, an oxide film having at least one gallium oxide crystal having a cubic structure, or gallium oxide having an ε structure and / or gallium oxide having a γ structure may be deposited. Further, an oxide film having a gallium oxide crystal in which gallium nitride and the in-plane lattice constant a are matched by the HVPE method in an atmosphere of 700 ° C. or lower on the surface of the n-type semiconductor substrate 350, and the lattice constant of the a-axis is 0. A hexagonal crystal having a size of 28 nm or more and 0.34 nm or less, an oxide film having at least one gallium oxide crystal having a cubic structure, or a gallium oxide having an ε structure and / or a gallium oxide having a γ structure may be deposited. Further, an oxide film having a gallium oxide crystal in which gallium nitride and the in-plane lattice constant a are matched by the ALD method in an atmosphere of 500 ° C. or lower on the surface of the n-type semiconductor substrate 350, and the lattice constant of the a-axis is 0. An oxide film having at least one gallium oxide crystal having a hexagonal crystal or a cubic structure of 28 nm or more and 0.34 nm or less, or gallium oxide having an ε structure and / or gallium oxide having a γ structure may be deposited. Further, it has a gallium oxide crystal in which gallium nitride is deposited on the surface of the n-type semiconductor substrate 350 by a sputtering method in an atmosphere of 500 ° C. or lower, and then annealed to match gallium nitride with the in-plane lattice constant a. An oxide film, a hexagonal crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an oxide film having a gallium oxide crystal having at least one of cubic crystals, or a gallium oxide having an ε structure and / or a γ structure. Gallium oxide may be deposited.

The fourth method of forming the first insulating film 351 is to form gallium oxide crystals on the surface of the n-type semiconductor substrate 350 by heat treatment at 500 ° C. or higher and 870 ° C. or lower, and then etching the gallium oxide. This is a method of forming the first insulating film by reducing the thickness of the material to 10 nm or less.

The second insulating film 352 is an oxide, a nitride, or an acid of at least one element selected from the group of elements consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and rare earth elements. The nitride is formed by a sputtering method, a CVD method, an ALD method, or the like. Specific materials for the second insulating film 352 include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , and Si. Examples thereof include _3N4 and SiON. For example, when Al ₂ O ₃ is formed as a _second insulating film by a sputtering method, Al can be used as a target and DC sputtering can be performed in oxygen gas. RF sputtering can also be performed using Al ₂ O ₃ as a target. It can also be formed by the ALD method using trimethylaluminum.

Next, as shown in FIG. 6A, a gate electrode 340 is provided on the surface side of the gate insulating film 342.
In the gate electrode 340, the gate material constituting the gate electrode is deposited on the entire surface of the gate insulating film 342, a photoresist layer having a desired pattern is formed by lithography, and the photoresist layer is used as an etching mask to etch the gate material. And form. Examples of the method for depositing the gate electrode material include a sputtering method, a vapor deposition method using an electron beam, a vapor deposition method by heating, and a CVD method. This method is characterized by high gate electrode processing accuracy.

Next, as shown in FIG. 6B, a source electrode 344 is provided in contact with the p ⁺ type contact layer 316 and the n ⁺ type contact layer 318.
Then, as shown in FIG. 6C, the back surface of the n-type semiconductor substrate 350 is doped with n-type impurities to form the n ⁺ type semiconductor layer 332, and then the n ⁺ type semiconductor layer 332 is drained on the back surface. An electrode 346 is provided. The gate electrode 340, the source electrode 344, and the drain electrode 346 are at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly-Si. May be formed from. In addition to these metals, alloys containing at least one selected from these groups, and compounds such as nitrides, carbides, and carbides containing at least one selected from these groups may be used.
With the above, the vertical MISFET 300 is completed.

The MISFET 300 according to the manufacturing method of the third embodiment is a vertical MISFET using a gallium nitride based semiconductor as a semiconductor layer, and is characterized by having a gate insulating film in a good interface state with few trap sites. Therefore, the MISFET 300 according to the manufacturing method of the third embodiment is a MISFET having excellent frequency characteristics and less hysteresis.

In the first to third embodiments, the gallium nitride gate insulating film has an oxide film having a gallium nitride crystal in which the in-plane lattice constant a is matched with the gallium nitride, and the a-axis lattice constant is 0.28 nm or more. The case where an oxide film having at least one gallium oxide crystal having a hexagonal crystal or a cubic crystal of 34 nm or less, or a gallium oxide film having an ε structure and / or a gallium oxide film having a γ structure is applied is shown. An oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched, a hexagonal crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less, or a gallium oxide crystal having at least one of cubic crystals. The suitable application of the oxide film having an oxide film or the gallium oxide film having an ε structure and / or a γ structure is not limited to this.
For example, even if it is used as an insulating film of a MIS capacitor, since there are few trap sites, it is possible to provide a MIS capacitor having a small hysteresis and an excellent frequency characteristic.
Further, in a high-frequency device using a gallium nitride semiconductor, an oxide film having a crystal in which the gallium nitride and the in-plane lattice constant a are matched as a layer in direct contact with the surface of the gallium nitride semiconductor, and the lattice constant of the a-axis is 0. It is also effective to use an oxide film having at least one gallium oxide crystal having a hexagonal crystal or a cubic structure of 28 nm or more and 0.34 nm or less, or a passion film having a gallium oxide having a ε structure and / or a gallium oxide having a γ structure. Is. In this case, there is an effect that the current collapse in the high frequency device can be sufficiently suppressed. Here, the passivation film is at least one of gallium nitride and an oxide film having a gallium oxide crystal in which the in-plane lattice constant a is matched, a hexagonal crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, or a cubic crystal. It may be a structure composed of an oxide film having gallium oxide crystals of 1 or a multilayer film including a film having gallium oxide having an ε structure and / or gallium oxide having a γ structure.

<Embodiment 4>
In the fourth embodiment, the DMOS (Double-Defused MOSFET) 400 will be described with reference to FIGS. 14 and 15.

14 and 15 show an outline of a process for manufacturing a power MOSFET having a planar type DMOS structure by using a sequential cross-sectional structure. FIG. 15D shows the cross-sectional structure of the produced DMOS (400) more specifically. The manufacturing process thereof will be described by performing the steps shown in FIGS. 14 (a) to 14 (d) and FIGS. 15 (a) to 15 (d).

First, an n-type GaN epitaxial layer (n ^- epi layer) 403 is grown on a high-concentration n-type GaN substrate (n ⁺ substrate) 402 using the n ⁺ substrate 402 as a seed crystal (FIG. 14 (a)). reference). Here, the crystal structure of the n ^- epi layer 403 is a wurtzite structure.

After that, a resist pattern is formed so that the region of the gate electrode to be formed later is masked, and ion implantation is performed on the substrate surface. Then, the substrate is heat-treated after ion implantation to activate the p-type impurities that have been implanted. At that time, a slight diffusion occurs at the same time as the activation. By this step, a p-type well 404 in which p-type impurities are injected is formed in a portion other than the region where the gate is formed (see FIG. 14 (b)).

Next, in order to form the n ⁺ diffusion layer 405 in the p-type well 404, a mask made of a resist is formed, and n-type impurities are injected into a range limited by the opening under high concentration and shallow conditions. I do. At this time, the resist pattern is formed so that the gate electrode region to be formed later is masked.
After this injection, heat treatment is performed to activate the injected n-type impurities. Along with this heat treatment, a slight lateral diffusion occurs. By this step, an n ⁺ diffusion layer 405 is formed (see FIG. 14 (c)).

Next, as shown in FIG. 14 (d), a gallium oxide layer 406a is formed on the surface of this sample as a first insulating film.
Here, the gallium oxide layer 406a is an insulating film containing gallium oxide crystals, and in particular, oxide having a gallium oxide crystal in which the above-mentioned n ^- epi layer 403 made of gallium nitride and the in-plane lattice constant a are matched. A film, an insulating film having at least one gallium oxide of hexagonal crystal or cubic crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less, or gallium oxide having an ε structure and / or gallium oxide having a γ structure. It is preferable that the insulating film has.
An oxide film having a gallium oxide crystal in which the n ^- epi layer 403 and the in-plane lattice constant a of the gallium oxide layer 406a are matched, and hexagonal and cubic crystals having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. An insulating film having at least one of the gallium oxides, or a laminated film with a second insulating film 407a described later by using gallium oxide having an ε structure or a γ structure, which is a trap site suitable as a gate insulating film. It is possible to form a gate insulating layer 421a having few and good interface conditions.

In the first method of forming the gallium oxide layer 406a, the surface including the exposed surface of the n ^- epi layer 403 is composed of sulfuric acid, hydrogen peroxide solution, ammonia, fluoroacid, hydrochloric acid, nitric acid, phosphoric acid, and potassium hydroxide. A method of oxidizing with at least one chemical solution selected from the group.
Examples of this oxidation method include methods usually used for washing such as SC1, SC2, SPM, and buffered hydrofluoric acid solution.
According to this first method, the crystal planes of the gallium oxide layer 406a are aligned with the crystal planes on the surface of the n ^- epi layer 403. Therefore, the first method is particularly preferable for forming a high-quality gate insulator layer 421a with few traps.

In addition, light irradiation may be used together with this first method. For example, the surface containing the n ^- epi layer 403 is immersed in a chemical solution of potassium hydroxide, phosphoric acid, glycol, etc., and the surface is exposed to ultraviolet (UV) light having a wavelength of 280 nm or more and less than 380 nm or far-field outside of a wavelength of 190 nm or more and less than 280 nm. By irradiating with light (DUV), the surface including the exposed surface of the n ^- epi layer 403 may be oxidized to form the gallium oxide layer 406a.
Here, the first method is characterized in that the heat load is smaller than that of the thermal oxidation treatment because the treatment is at room temperature or at 280 ° C. or lower even if heat treatment is applied. When a large heat load is applied, problems such as a change in the profile of the injected impurities and stress are likely to occur.

In the second method of forming the gallium oxide layer 406a, the surface including the exposed surface of the n ^- epi layer 403 is oxidized by plasma oxidation treatment in an atmosphere of 500 ° C. or lower, and the n ^- epi layer 403 and the in-plane lattice are formed. An oxide film having a gallium oxide crystal with a matched constant a, a hexagonal crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less, an insulating film having at least one cubic gallium oxide, or ε. It is a method for forming gallium oxide having a structure and / or gallium oxide having a γ structure. Further, the surface including the exposed surface of the n ^- epi layer 403 is oxidized by ozone oxidation treatment in an atmosphere of 500 ° C. or lower, and the gallium oxide crystal in which the n ^- epi layer 403 and the in-plane lattice constant a are matched. An oxide film having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an insulating film having at least one cubic gallium oxide, or a gallium oxide having a ε structure and / or a γ structure. Gallium oxide may be formed.

A third method for forming the gallium oxide layer 406a is to surface the n ^- epi layer 403 on the surface including the exposed surface of the n ^- epi layer 403 by an electron beam deposition method and / or an MBE method in an atmosphere of 700 ° C. or lower. An oxide film having gallium oxide crystals with an internal lattice constant a matched, a hexagonal crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, and an insulating film having at least one cubic gallium oxide. Alternatively, it is a method of depositing gallium oxide having an ε structure and / or gallium oxide having a γ structure.
Further, an oxide film having gallium oxide crystals in which the p ^- epi layer 403 and the in-plane lattice constant a are matched by the CVD method in an atmosphere of 870 ° C. or lower on the surface including the exposed surface of the n ^- epi layer 403, a. A hexagonal crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less, an insulating film having at least one cubic gallium oxide, or gallium oxide having an ε structure and / or gallium oxide having a γ structure is deposited. May be good.
Further, an oxide film having gallium oxide crystals in which the in-plane lattice constant a is matched with the n ^- epi layer 403 by the HVPE method in an atmosphere of 700 ° C. or lower on the surface including the exposed surface of the n ^- epi layer 403, a. A hexagonal crystal having a lattice constant of 0.28 nm or more and 0.34 nm or less, an insulating film having at least one cubic gallium oxide, or gallium oxide having an ε structure and / or gallium oxide having a γ structure is deposited. May be good.
Further, an oxide film having gallium oxide crystals in which the in-plane lattice constant a is matched with the n ^- epi layer 403 by the ALD method in an atmosphere of 500 ° C. or lower on the surface including the exposed surface of the n ^- epi layer 403, a. Hexagonal crystals with an axial lattice constant of 0.28 nm or more and 0.34 nm or less, an insulating film having at least one cubic gallium oxide, or gallium oxide having a ε structure and / or gallium oxide having a γ structure may be deposited. good.
Further, gallium oxide is deposited on the surface including the exposed surface of the n ^- epi layer 403 by a sputtering method in an atmosphere of 500 ° C. or lower, and then annealed to match the n ^- epi layer 403 with the in-plane lattice constant a. An oxide film having gallium oxide crystals, a hexagonal crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less, an insulating film having at least one cubic gallium oxide, or gallium oxide having an ε structure. / Or gallium oxide having a γ structure may be deposited.

The fourth method for forming the gallium oxide layer 406a is to form gallium oxide crystals by heat treatment at 500 ° C. or higher and 870 ° C. or lower on the surface including the exposed surface of the n ^- epi layer 403, and then etching the gallium oxide. This is a method of forming the gallium oxide layer 406a by reducing the thickness of gallium oxide to 10 nm or less.

After that, as shown in FIG. 15A, a second insulating film 407a is formed on the gallium oxide layer 406a, and a gate insulating layer 421a composed of the gallium oxide layer 406a and the second insulating film 407a is formed. ..

The second insulating film 407a is an oxide, a nitride, or an acid of at least one element selected from the group of elements consisting of Al, Si, Hf, Zr, Ta, Ti, Ga, Y, Sc, and rare earth elements. The nitride is formed by a sputtering method, a CVD method, an ALD method, or the like. Specific materials for the second insulating film 407a include Al ₂ O ₃ , SiO ₂ , HfO ₂ , ZrO ₃ , Ta ₂ O ₃ , TiO ₂ , Ga ₂ O ₃ , YO ₃ , Sc ₂ O ₃ , and Si. ₃ N ₄ , SiON and the like can be mentioned. For example, when Al ₂ O ₃ is formed as the second insulating film 407a by a sputtering method, Al can be used as a target and DC sputtering can be performed in oxygen gas, or Al ₂ O ₃ can be used as a target. RF sputtering can also be performed. It can also be formed by the ALD method using trimethylaluminum.

Next, as shown in FIG. 15B, a metal film 408a is formed on the surface of the second insulating film 407a. Here, as the metal film 408a, for example, at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, and Zn can be mentioned. The form may be a single-layer film or a laminated film. In addition to these metals, alloys containing at least one selected from these groups, and compounds such as nitrides, carbides, and carbides containing at least one selected from these groups may be used. Further, as the metal film 408a, polysilicon can be used, and a laminated film of polysilicon and the metal can also be mentioned. Examples of the method for forming the metal film 408a include a sputtering method and a thin-film deposition method.

Next, using the resist as a mask, the metal film 408a, the second insulating film 407a, and the gallium oxide layer 406a are dry-etched to form the first insulating film 406, the second insulating film 407, and the gate electrode 408. The gate shape of the DMOS is formed (see FIG. 15 (c)).

Next, a PSG film (a low-temperature oxide film containing 3% to 5% of phosphorus atoms) is formed on the entire surface of the substrate using a reduced pressure CVD method, and then a metal contact is formed to be connected to the n ⁺ diffusion layer 405. An insulating film 411 made of a PSG film having an opening portion for the purpose is formed.
Finally, a metal contact made of a metal, for example, an alloy of titanium and aluminum is formed in the opening portion to form an emitter electrode 412. On the other hand, on the back surface of the n ⁺ substrate 402, a back surface electrode made of a multilayer film made of nickel, titanium, silver, gold, etc. that obtains low resistance ohmic contact with the n ⁺ substrate is formed to form a collector electrode 401 (FIG. 15 (d). )reference).
By the above steps, DMOS (400) is produced.

The DMOS (400) according to the manufacturing method of the fourth embodiment is a MOSFET having a DMOS structure using a gallium nitride based semiconductor as a semiconductor layer, and has a gate insulating film in a good interface state with few trap sites. It is a feature. Therefore, the DMOS (400) according to the manufacturing method of the fourth embodiment is a power MOSFET in which the frequency characteristics and the switching characteristics are stable and excellent.

In Example 1, the MIS capacitor (MOS capacitor) 200 shown in FIG. 7 was manufactured, and the electrical characteristics of the MIS capacitor were evaluated.

The MIS capacitor of Example 1 is composed of a self-standing substrate 201, an n ^- GaN epitaxial layer 202 as a semiconductor layer, an insulating layer 203 composed of a first insulating film 204 and a second insulating film 205, and electrodes 206 and 207.

The method for manufacturing the MIS capacitor of Example 1 is as follows.

As a semiconductor substrate and a semiconductor layer, a self-supporting substrate 201 made of n ^- GaN having a thickness of 270 μm is subjected to a Si-doped with a film thickness of 5 μm by a metalorganic chemical vapor deposition (MOCVD) method. A layer having an n ^- GaN epitaxial layer 202 having a carrier concentration of 1 × 10 ¹⁶ cm ^-3 was prepared. Here, the crystal plane on the surface of the n ^- GaN epitaxial layer 202 is (0001).

The surface of the n ^- GaN epitaxial layer 202 was washed with an isopropyl alcohol and an acetone solution at room temperature (23 ° C.), and then surface-treated with a dilute hydrofluoric acid solution having a concentration of 3% by volume.
Subsequently, SPM consisting of H ₂ SO ₄ -H ₂ O ₂ -H ₂ O was used as an oxide film forming method to generate gallium oxide crystals (Ga ₂ O ₃ ) on the surface of the n ^- GaN epitaxial layer 202. The gallium oxide crystal layer was used as the first insulating film 204. Here, the n ^- GaN epitaxial layer 202 was immersed in an SPM solution and treated at the temperature of self-heating at the time of producing sulfuric acid hydrogen peroxide. The volume ratio of H ₂ SO ₄ and H ₂ O ₂ is 2: 1.

The surface state of the n ^- GaN epitaxial layer 202 surface-treated by SPM was measured by the XPS (X-ray Photoelectron Spectroscopy) method. FIG. 8 shows the XPS Ga _3d spectrum by the XPS method. The measurement data is indicated by □, and the simulation data is indicated by a solid line.
Data by simulation (thin solid line) obtained by adding up the Ga-N bond component (thick solid line) having a peak at the binding energy of 19.8 eV and the Ga-O bond component (thick solid line) having a peak at the binding energy of 20.3 eV. Is in good agreement with the measured data. As a result, it was confirmed that gallium oxide was generated on the surface of the n ^- GaN epitaxial layer 202 by surface-treating the surface of the n ^- GaN epitaxial layer 202 with SPM.

In addition, cross-sectional analysis by TEM (Transmission Electron Microscope) was performed to investigate the structure of gallium nitride crystals formed on the surface of the n ^- GaN epitaxial layer 202. 9A and 9B show a cross-sectional analysis diagram on the Miller index [1-100] plane and a cross-sectional analysis diagram on the Miller index [11-20] plane, respectively. As a result, the thickness of the produced gallium oxide was 1.7 nm, and it was confirmed that the crystal structure of this gallium oxide was a crystal having an ε structure and a γ structure.
Furthermore, by STEM (Scanning transmission electron microscopy), it was confirmed that this gamma oxide consists of crystals having an ε structure of 80% and a γ structure of 20% by volume.
Further, it was confirmed that the crystal planes of the ε structure and the γ structure were aligned with the crystal planes of the n ^- GaN epitaxial layer 202.

Subsequently, aluminum oxide (Al ₂ ) having a growth temperature of 300 ° C. and a film thickness of 10 nm was produced by the ALD method using trimethylaluminum (TMA) as a precursor and water vapor as an oxidation gas on the surface of the first insulating film 204. O ₃ ) was generated and used as a second insulating film 205.
Specifically, using nitrogen gas (N ₂ gas) as a purge, the four steps of TMA injection, N ₂ gas purge, water gas injection at 20 ° C, and N ₂ gas purge are set as one cycle until the film thickness reaches 10 nm. Repeated. Here, TMA and water gas were pulsed.
Then, after forming the Al ₂ O ₃ film, a heat treatment at 300 ° C. was performed in a nitrogen atmosphere gas.

Subsequently, a platinum (Pt) film having a film thickness of 100 nm was formed on the surface of the second insulating film 205 by an electron beam vapor deposition method and a photolithography process to form an electrode 206.
Finally, a titanium (Ti) film having a thickness of 20 nm and a platinum (Pt) film having a thickness of 100 nm are continuously formed on the front surface (back surface) of the n ^- GaN free-standing substrate 201 to form the ohmic contact electrode 207. Formed.
Through the above steps, the MIS capacitor 200 shown in FIG. 7 was manufactured.

FIG. 10 shows the CV characteristics of the manufactured MIS capacitor 200.
The measurement data when a voltage is applied to the forward between the electrodes 206 and 207 is indicated by a circle, and the measurement data when a voltage is applied to the reverse is indicated by a □.
It was confirmed that the hysteresis in the flat band voltage in the case of forward and the case of reverse is negligibly small. This is because there are very few trap sites due to defects in the insulating layer 203 composed of the first insulating film 204 made of gamma oxide having an ε structure and the γ structure and the second insulating film 205 made of aluminum oxide. Means.

Further, the ideal curve shown by the solid line obtained from the Fermi level of the n ^- GaN epitaxial layer 202, the work function of the electrode 206 by Pt, the film thickness and the dielectric constant of the insulating film 203, and the measurement indicated by ○ and □ marks. The data matched very well.
In Non-Patent Document 1, since the interface between the n ^- GaN epitaxial layer 202 and the insulator layer 203 is not manufactured with particular care, frequency dispersion of CV characteristics is reported, and the interface is described. It suggests that the condition is not good.

From the above, the MIS capacitor 200 in which the semiconductor layer is gallium nitride and the insulating layer 203 is composed of a first insulating film 204 made of gallium oxide having an ε structure and a γ structure and a second insulating film 205 made of aluminum oxide is trapped. It was confirmed that it had good interfacial properties with few sites.

As described above, the insulating layer 203 made of the first insulating film made of gallium oxide having the ε structure and the γ structure and the second insulating film made of aluminum oxide formed on the gallium nitride semiconductor layer has an interface with few trap sites. An insulating layer with good properties is formed, but this is not limited to MIS capacitors. When an insulating layer 203 composed of a first insulating film made of gallium oxide having an ε structure and a γ structure and an insulating layer 203 made of two insulating films is used as the gate insulating film of the MISFET (MOSFET), the gate insulating film has an interface characteristic with few trap sites. As a result, it becomes possible to provide a good MISFET (MOSFET) having excellent frequency characteristics and less hysteresis.

As the semiconductor layer on the semiconductor substrate, a commercially available n ^- GaN substrate having a thickness of 5 μm and a Si-doped carrier concentration of 2 × 10 ¹⁶ cm ^-3 was obtained. Here, the crystal plane on the surface of this semiconductor substrate is (0001).

The surface of the n ^- GaN substrate was washed with an isopropyl alcohol and an acetone solution at room temperature (23 ° C.), and then surface-treated with a dilute hydrofluoric acid solution having a concentration of 3% by volume.
Subsequently, SPM composed of H ₂ SO ₄ -H ₂ O ₂ -H ₂ O was used as an oxide film forming method to generate gallium oxide on the surface of the n ^- GaN substrate, and the gallium oxide layer was used as the first gallium oxide layer. It was used as an insulating film. That is, the n ^- GaN substrate was immersed in the SPM solution and treated at the temperature of self-heating at the time of producing sulfuric acid hydrogen peroxide. The volume ratio of H ₂ SO ₄ and H ₂ O ₂ is 2: 1.

Then, a second insulating film made of SiO ₂ having a film thickness of 100 nm was formed on the first insulating film made of gallium oxide by a plasma CVD method. The second insulating film is an amorphous film. Then, both insulating films were evaluated by TEM observation of the cross section.

FIG. 16 shows the cross-sectional TEM observation results. Here, FIG. 16 (a) is a bright field cross-sectional TEM image, (b) is a dark field cross-sectional TEM image, and (c) is a dark-field cross-sectional TEM image overlaid with a diffraction image obtained by FFT (Fast Fourier Transform) signal analysis. It is a statue. The white line in (c) and the white dot sequence with high brightness indicate the diffraction result.

As a result, as can be seen from FIG. 16 (c), from the GaN crystal region to the first insulating film, the white spots having high brightness are aligned in a straight line, and the crystal lattice of the GaN crystal and the first insulating film is formed. It was confirmed that they were consistent. It has been confirmed by slow ion scattering spectroscopy that the first insulating film is made of a gallium oxide film.

Then, the film thickness of the second insulating film was changed to 10 nm, and a MIS capacitor was produced in the same manner as in Example 1. Further, an Al ₂ O ₃ film having a film thickness of 10 nm shown in Example 1 was formed from the second insulating film, and a MIS capacitor was produced in the same manner as in Example 1. As a result, the produced MIS capacitor had good interfacial characteristics with few trap sites.

Although the above description has been made for a specific embodiment, it is clear to those skilled in the art that the present invention is not limited to this, and various changes and modifications can be made within the scope of the principles of the present invention and the accompanying claims. be.

1 Oxygen atom (O)
2 Gallium atom (Ga)
11 Crystal lattice 21 Lattice constant a ₁
22 Lattice constant a ₂
23 Lattice constant a ₃
100 Semiconductor device 101 Semiconductor layer 102 Insulator layer (gate insulating film)
103 First insulating film 104 Second insulating film 105 Gate electrode 107 Source area 108 Drain area 109 Source electrode 110 Drain electrode 111 Free-standing substrate 151 Screen layer 152 Insulation layer 153 Cap layer 161 Photo resist layer 200 MIS capacitor 201 n ^- GaN Free-standing substrate 202 n ^- GaN epitaxial layer 203 Insulator layer 204 First insulating film 205 Second insulating film 206 Electrode 207 Electrode 300 Vertical MISFET
310 p-type semiconductor layer 312 n-type source side region 313 surface side end 314 n-type drain side region 316 p ⁺ type contact layer 318 n ⁺ type contact layer 320 current cutoff layer 322 p ⁺ type column 330 drift layer 332 n ⁺ type Semiconductor layer 340 Gate electrode 342 Gate insulating film (insulator layer)
343 Channel length 344 Source electrode 346 Drain electrode 350 Semiconductor substrate 351 First insulating film 352 Second insulating film 360 photoresist layer 362 photoresist layer 364 photoresist layer 366 photoresist layer 367 open end 400 DMOS
401 Collector electrode 402 n-type GaN substrate (n ⁺ substrate)
403 GaN epitaxial layer (n ^- epi layer)
404 p-type well 405 Diffusion layer 406 First insulating film 406a Gallium oxide layer 407 Second insulating film 407a Second insulating film 408 Gate electrode 408a Metal film 411 Insulating film (PSG film)
412 Emitter electrode 421a Gate insulator layer

Claims (19)

A semiconductor layer containing gallium nitride and
With the gate electrode
An insulator layer provided between the semiconductor layer and the gate electrode is provided.
The gallium nitride is a single crystal and is
The insulator layer has at least a first insulating film containing gallium oxide crystals in a portion adjacent to the semiconductor layer.
The gallium oxide crystal is a semiconductor device in which the in-plane lattice constant a matches the gallium nitride crystal lattice. The gallium nitride is a single crystal having a wurtzite structure.
The semiconductor device according to claim 1, wherein the gallium oxide crystal is a hexagonal crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. The gallium nitride is a single crystal having a wurtzite structure.
The semiconductor device according to claim 1, wherein the gallium oxide crystal is a cubic crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. The gallium nitride is a single crystal having a wurtzite structure.
The semiconductor device according to claim 1, wherein the gallium oxide crystal is a hexagonal or cubic crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. The semiconductor device according to claim 1, wherein the gallium oxide crystal is selected from the group consisting of gallium oxide having an ε structure, gallium oxide having a γ structure, and a combination thereof. The semiconductor device according to any one of claims 1 to 5, wherein the crystal planes of gallium oxide are arranged so as to be aligned with the crystal planes of the semiconductor layer. The semiconductor device according to any one of claims 1 to 6, wherein the thickness of the first insulating film is not less than the thickness of one atomic layer of the gallium oxide crystal and not more than 10 nm. The semiconductor device according to claim 7, wherein the first insulating film has a film thickness of 5 nm or less. The first insulating film is a gallium oxide crystal in which the gallium nitride crystal lattice and the in-plane lattice constant a are matched, or a hexagonal crystal or cubic crystal having an a-axis lattice constant of 0.28 nm or more and 0.34 nm or less. Any one of claims 1 to 6, wherein the gallium oxide crystal is at least one of the above, and the ratio of the volume occupied by the gallium oxide crystal in the first insulating film is 95% or more. The semiconductor device according to paragraph 1. When the first insulating film has a combination of gallium oxide having an ε structure and gallium oxide having a γ structure, the volume ratio of the gallium oxide crystals having an ε structure in the first insulating film is 70% or more. The semiconductor device according to claim 5, wherein the semiconductor device is 90% or less, and the residual portion of the first insulating film is occupied by gallium oxide crystals having a γ structure. 13. Semiconductor device. When the first insulating film has a combination of ε-structured gallium oxide and γ-structured gallium oxide, the ratio of the volume occupied by the ε-structured gallium oxide and the γ-structured gallium oxide in the first insulating film. The semiconductor device according to claim 5, wherein is 95% or more. The insulating layer includes a second insulating film provided between the gate electrode and the first insulating film, and the second insulating film is Al, Si, Hf, Zr, Ta, Ti. , Ga, Y, Sc, the semiconductor according to any one of claims 1 to 12, having an oxide, a nitride, or an oxynitride of at least one element selected from the group of elements consisting of rare earth elements. Device. Claims 1 to 13 wherein the gate electrode has at least one selected from the group consisting of Al, Ti, W, Pt, Au, Ag, Ru, Rh, Pd, Ni, Sn, Zn, and poly—Si. The semiconductor device according to any one of the above. The method for manufacturing a semiconductor device according to any one of claims 1 to 14.
The semiconductor layer preparation process for preparing the semiconductor layer and
The insulator layer forming step for forming the insulator layer and
A manufacturing method including at least a gate electrode forming step for forming the gate electrode. In the insulator layer forming step, the semiconductor layer is surfaced using at least one selected from the group consisting of sulfuric acid, hydrogen peroxide solution, ammonia, fluoroacid, hydrochloric acid, nitric acid, phosphoric acid, and potassium hydroxide. The production method according to claim 15, which comprises a step of forming the first insulating film by processing. The production according to claim 15, wherein the insulator layer forming step includes a step of forming the first insulating film by subjecting the semiconductor layer to plasma oxidation treatment and / or ozone oxidation treatment at 500 ° C. or lower. Method. In the insulator layer forming step, an electron beam vapor deposition method and / or an MBE method is used at 700 ° C. or lower, a CVD method is used at 870 ° C. or lower, and an HVPE method is performed at 700 ° C. or lower on the semiconductor layer. 15. The production method according to claim 15, comprising the step of laminating the first insulating film using the ALD method at 500 ° C. or lower and / or using the sputtering method at 500 ° C. or lower. .. In the insulator layer forming step, gallium oxide crystals are formed on the semiconductor layer by heat treatment at 500 ° C. or higher and 870 ° C. or lower, and then etching is performed to reduce the thickness of the gallium oxide crystals to 10 nm or less. The manufacturing method according to claim 15, which comprises the step of forming the first insulating film.

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